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| REJ09B0254-0500 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7727 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7727 HD6417727 Rev. 5.00 Revision Date: Dec 12, 2005 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 5.00 Dec 12, 2005 page ii of lxxii General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are not connected to any of the internal circuitry; they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of access to undefined or reserved address Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers: the system's operation is not guaranteed if they are accessed. Rev. 5.00 Dec 12, 2005 page iii of lxxii Rev. 5.00 Dec 12, 2005 page iv of lxxii Preface The SH7727 microprocessor incorporates the 32-bit SH-3 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7727 is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timers, three serial communication interfaces (SCI, SCIF, SIOF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and AFE interface. The SH7727 can be used in a variety of applications that demand a high-speed microcomputer with low power consumption. The descriptions in this manual are based on the SH7727C. For details on using versions previous to the SH7727B please refer to Using Versions Previous to the SH7727B at the end of the manual. Note that the version is the SH7727C if "C" is engraved on the chip and the version is the SH7727B if "B" is engraved. If there is no such indication the product is a version previous to the SH7727B. (See Appendix E.) Target Readers: This manual is designed for use by people who design application systems using the SH7727. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7727. The SH-3, SH-3E, SH3-DSP Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with this manual. How to Use the Book: * To understand general functions Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order. * To understanding CPU functions Refer to the separate SH-3, SH-3E, SH3-DSP Programming Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/) Rev. 5.00 Dec 12, 2005 page v of lxxii * User manuals for SH7727 Name of Document SH7727 Hardware Manual SH-3, SH-3E, SH3-DSP Programming Manual Document No. This manual ADE-602-096B * User manuals for development tools Name of Document SuperHTM RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package V.9.00 User's Manual SuperHTM RISC engine High-Performance Embedded Workshop 3 User's Manual SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial Document No. REJ10B0152-0101 REJ10B0025-0200H REJ10B0023-0200H * Application Note Name of Document SuperH RISC engine C/C++ Compiler Package Application Note Document No. REJ05B0463-0200 Rev. 5.00 Dec 12, 2005 page vi of lxxii Revisions and Additions Page Item Timer (TMU, CMT) Previous Version Features * 3-channel auto-reload-type 32-bit timer * 1-channel 16-bit compare match timer * Choice of six counter input clocks * Maximum resolution: 2 MHz Revised Version Item Timer (TMU) Features * 3-channel auto-reload-type 32-bit timer * Choice of six counter input clocks * Maximum resolution: 2 MHz 5 to 7 Table 1.1 SH7727 Features Item Serial communication interface (SCIF) Features * 16-byte FIFO for transmission/reception * DMA can be transferred * Hardware flow control Item Serial communication interface (SCIF) Features * 16-byte FIFO for transmission/reception * DMA can be transferred * On-chip modem control function Direct memory * 4 channels access controller * Burst mode and cycle-steal mode (DMAC) * External request operating mode Direct memory * 4 channels access controller * Burst mode and cycle-steal mode (DMAC) * External request operating mode * 1-channel 16-bit compare match timer Item LCD controller (LCDC) Features * From 16 x 1 to 1024 x 1024 pixels can be supported * 1/2/4/6/8/16 bpp (bit per pixel) with 18bit color pallet * 1/2/4 bpp (bit per pixel) gray scale * 8-bit Frame rate controller * TFT/DSTN/STN * Signal polarity setting function * Hardware panel rotation * Power control function * Selectable clock source (LCLK or Bclk or Pclk) Item LCD controller (LCDC) Features * From 16 x 1 to 1024 x 1024 pixels can be supported * 4/8/15/16 bpp (bit per pixel) color modes * 1/2/4/6 bpp (bit per pixel) gray scale * 8-bit Frame rate controller * TFT/DSTN/STN * Signal polarity setting function * Hardware panel rotation * Power control function * Selectable clock source (LCLK, bus clock (B), or peripheral clock (P)) A/D converter (ADC) * 10 bits 4 LSB, 6 channels * Conversion time: 10 s * Input range: 0-Vcc (max. 3.6 V) A/D converter (ADC) * 10 bits 4 LSB, 6 channels * Conversion time: 15 s * Input range: 0-Vcc (max. 3.6 V) Product lineup Abb. SH7727 Power Supply Voltage I/O 3.3 0.3 V Internal 1.7 to 2.05 V Product lineup Operating Frequency 160 MHz Model Name HD6417727F160B Package 240-pin plastic HQFP (FP-240B) Power Supply Voltage SH7727 160 MHz products I/O Internal Operating Frequency Model Name HD6417727F160C Package 240-pin plastic HQFP (PRQP0240KC-B) 3.0 V to 1.70 V to 160 MHz 3.6 V 2.05 V HD6417727BP160B 240-pin CSP (BP-240A) 3.1 0.5 V 1.6 to 2.05 V 100 MHz HD6417727F100B 240-pin plastic HQFP (FP-240B) HD6417727BP160C 240-pin CSP (PLBG0240JA-A) 100 MHz products 2.6 V to 1.60 V to 100 MHz 3.6 V 2.05 V HD6417727F100C 240-pin plastic HQFP (PRQP0240KC-B) HD6417727BP100B 240-pin CSP (BP-240A) HD6417727BP100C 240-pin CSP (PLBG0240JA-A) 11 to 19 Table 1.2 SH7727 Pin Function Pin No. (FP-240B) Pin No. (BP-240A) Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) 167 7.1.4 Register Configuration The INTC has 12 registers listed in table 7.2. The INTC has 17 registers listed in table 7.2. Rev. 5.00 Dec 12, 2005 page vii of lxxii Page 169 Previous Version 7.2.2 IRQ Interrupt IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority level can be set by priority setting registers C, D (IPRC, IPRD) in a range from levels 0 to 15. When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1 from the corresponding bit in IRR0, then write 0 to the bit. Revised Version IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority level can be set by priority setting registers C, D (IPRC, IPRD) in a range from levels 0 to 15. When using edge sensing for IRQ interrupts, do the following to clear IR0. To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared; write 1 to the other bits. The values of the bits to which 1 is written do not change. When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to IRQ0R alone. 175 Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Source TMU1 TMU2 RTC TUNI1 TUNI2 TICPI2 ATI PRI CUI SCI0 ERI RXI TXI TEI INTEVT Code (INTEVT2 Code) H'420 (H'420) H'440 (H'440) H'460 (H'460) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) Low Low 0-15 (0) IPRB (3-0) Low High 0-15 (0) IPRA (3-0) Interrupt Priority IPR (Bit (Initial Value) Numbers) 0-15 (0) 0-15 (0) IPRA (11-8) IPRA (7-4) Priority within IPR Setting Default Priority Unit -- High Low High High Interrupt Source TMU1 TMU2 RTC TUNI1 TUNI2 ATI PRI CUI SCI0 ERI RXI TXI TEI INTEVT Code (INTEVT2 Code) H'420 (H'420) H'440 (H'440) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) Interrupt Priority (Initial Value) 0-15 (0) 0-15 (0) 0-15 (0) IPR (Bit Numbers) IPRA (11-8) IPRA (7-4) IPRA (3-0) Priority within IPR Setting Default Unit Priority -- -- High Low High 0-15 (0) IPRB (7-4) High Low Low 177 Table 7.5 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Source ADC LCDC TMU1 TMU2 ADI LCDCI TUNI1 TUNI2 TICPI2 INTEVT Code (INTEVT2 Code) H'200-3C0* (H'980) H'200-3C0* (H'9A0) H'420 (H'420) H'440 (H'440) H'460 (H'460) Interrupt Priority (Initial IPR (Bit Numbers) Value) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) IPRE (3-0) IPRF (11-8) IPRA (11-8) IPRA (7-4) Priority within IPR Setting Default Priority Unit -- -- -- High Low Low High Interrupt Source ADC LCDC TMU1 TMU2 ADI LCDCI TUNI1 TUNI2 INTEVT Code (INTEVT2 Code) H'200-3C0* (H'980) H'200-3C0* (H'9A0) H'420 (H'420) H'440 (H'440) Interrupt Priority (Initial IPR (Bit Value) Numbers) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) IPRE (3-0) IPRF (11-8) IPRA (11-8) IPRA (7-4) Priority within IPR Setting Default Unit Priority -- -- -- -- Low High Rev. 5.00 Dec 12, 2005 page viii of lxxii Page 188 Previous Version 7.3.7 Interrupt Request Register 0 (IRR0) The IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. This register is initialized to H'00 at power-on reset or manual reset, but is not initialized in standby mode. Revised Version When using edge sensing for IRQ interrupts, do the following to clear IR0. To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared; write 1 to the other bits. The values of the bits to which 1 is written do not change. When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to IRQ0R alone. 198 Figure 7.3 Interrupt Operation Flowchart Yes NMI? No Yes Yes Yes NMI? Yes Yes No IRQOUT = low Set interrupt cause in INTEVT, INTEVT2 Set interrupt cause in INTEVT, INTEVT2 199 7.4.2 Multiple Interrupts When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. Figure 7.3 shows a sample interrupt operation flowchart. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. Rev. 5.00 Dec 12, 2005 page ix of lxxii Page 234 Previous Version Table 9.1 Power-Down Modes Mode Sleep mode Transition Conditions Execute SLEEP instruction with STBY bit cleared to 0 in STBCR Set MSTP bit of STBCR to 1 Revised Version Mode Sleep mode Transition Conditions Execute SLEEP instruction with STBY bit cleared to 0 in STBCR *7 Set MSTP bit of STBCR to 1*6 Module standby function Module standby function Note 6, 7, added Section 10.1.2 "Clock Abbreviation" deleted 259 Figure 10.1 Block Diagram of Clock Pulse Generator Clock pulse generator CAP1 CKIO2 PLL circuit 1 (x 1, 2, 3, 4, 6) Divider 1 x1 x 1/2 x 1/3 x1/4 Divider 2 x1 x 1/2 x 1/3 x 1/4 x 1/6 Clock pulse generator CAP1 CKIO2 Internal clock (I) Cycle = Icyc PLL circuit 1 (x 1, 2, 3, 4, 6) CKIO Cycle = Bcyc CAP2 XTAL EXTAL Crystal oscillator PLL circuit 2 (x 1, 4) CKIO Cycle = Bcyc Divider 1 x1 x 1/2 x 1/3 x1/4 Divider 2 x1 x 1/2 x 1/3 x 1/4 x 1/6 Internal clock (I) Cycle = Icyc Peripheral clock (P) Cycle = Pcyc CAP2 XTAL EXTAL Crystal oscillator PLL circuit 2 (x 1, 4) Peripheral clock (P) Cycle = Pcyc Bus clock (P) Cycle = Bcyc Bus clock (P) Cycle = Bcyc 260 10.2.1 CPG Block Diagram 1. PLL Circuit 1 PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock frequency from the CKIO terminal. ... PLL circuit 1 doubles, triples, quadruples sextuples, or leaves unchanged the input clock frequency from the CKIO pin or PLL circuit 2. ... Rev. 5.00 Dec 12, 2005 page x of lxxii Page 265, 266 Previous Version Table 10.4 Available Combination of Clock Mode and FRQCR Values Cautions: 1. The frequency ranges of the input clock and crystal oscillator should be set within the specified frequency range based on the clock rate in table 10.4, and section 32.3, AC Characteristics. 2. The input to divider 1 becomes the output of: * PLL circuit 1 when PLL circuit 1 is on. * PLL circuit 2 when PLL circuit 1 is off and PLL circuit 2 is on. 3. The input of divider 2 becomes the output of: * PLL circuit 1 4. The frequency of the internal clock (I) becomes: * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on. * Equal to the frequency of CKIO pin when PLL circuit 1 is off. * Do not set the internal clock frequency lower than the CKIO pin frequency. 5. The frequency of the peripheral clock (P) becomes: * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2 when the clock operating mode is 0 to 2 or 7. * The peripheral clock frequency should not be set higher than the maximum frequency specified in the AC Characteristics, higher than the frequency of the CKIO pin, higher than 40 MHz, or lower than 1/8 the internal clock (I). 6. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. This frequency should be equal to or lower than the maximum frequency specified in the AC Characteristics. 7. x 1, x 2, x 3, x 4, or x 6 can be used as the multiplication ratio of PLL circuit 1. x 1, x 1/2, x 1/3, and x 1/4 can be selected as the division ratio of divider 1. x 1, x 1/2, x 1/3, x 1/4, and x 1/6 can be selected as the division ratio of divider 2. Set the rate in the frequency control register. The on/off state of PLL circuit 2 is determined by the mode. Cautions: Revised Version 1. The frequency ranges of the input clock and crystal oscillator should be set within the specified frequency range based on the clock rate in table 10.4, and section 32.3, AC Characteristics. 2. The input to divider 1 becomes the output of PLL circuit 1 when PLL circuit 1 is on. 3. The input of divider 2 becomes the output of: * PLL circuit 1 4. The frequency of the internal clock (I) becomes: * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on. * Do not set the internal clock frequency lower than the CKIO pin frequency. * Depending on the product, the clock ratio should be set to produce a frequency within one of the ranges indicated below. 100 MHz products: 24 MHz to 100 MHz 160 MHz products: 24 MHz to 160 MHz 5. Bus clock (B) frequency: * Depending on the product, the clock ratio should be set to produce a frequency within one of the ranges indicated below. 100 MHz products: 24 MHz to 50 MHz 160 MHz products: 24 MHz to 66.64 MHz 6. The frequency of the peripheral clock (P) becomes: * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2. * For all products, the peripheral clock frequency (P) should be set within the frequency range 6 MHz to 33.34 MHz and no higher than the frequency of the CKIO pin. * The peripheral clock frequency (P) should be set to 13 MHz or higher if the USB function module is used. 7. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. 8. x1, x2, x3, x4, or x6 can be used as the multiplication ratio of PLL circuit 1. x1, x1/2, x1/3, and x1/4 can be selected as the division ratio of divider 1. x1, x1/2, x1/3, x1/4, and x1/6 can be selected as the division ratio of divider 2. Set the rate in the frequency control register. The on/off state of PLL circuit 2 is determined by the mode. Rev. 5.00 Dec 12, 2005 page xi of lxxii Page 279 Previous Version 11.1.1 EXCPG The extend clock pulse generator (EXCPG) generates a divided clock from the CPU clock (I), the bus clock (B), or the external clock (UCLK). Figure 11.1 Block Diagram of EXCPG USB clock (48 MHz) P clock Select I clock Bus clock UCLK 1/1 1/2 1/3 USB function Internal clock (I) Bus clock (B) External clock (UCLK) USB host Peripheral clock (P) Revised Version The extend clock pulse generator (EXCPG) generates a divided clock from the internal clock (I), the bus clock (B), or the external clock (UCLK). USB clock (48 MHz) USB host Select 1/1 1/2 1/3 USB function 281 11.3.1 EXCPG Control Register (EXCPGCR) Bits 5 to 3--Clock Select (USBCKSEL2 to USBCKSEL0): Bits 5 to 3 110 Function (Clock Selection) External clock Bits 5 to 3 110 Function (Clock Selection) External clock (UCLK) Bits 2 to 0 Function (Dividing Ratio Selection): Bits 2 to 0 1** Function (Dividing Ratio Selection) I, CKIO, UCLK halted Bits 2 to 0 1** Function (Dividing Ratio Selection) Internal clock (I), bus clock (B), external clock (UCLK) halted Note: To reduce power consumption, set USBDIVSEL2 to 1 and halts Io, CKIO, or UCLK input. Note: To reduce power consumption, set USBDIVSEL2 to 1 and halts internal clock (I), bus clock (B), or external clock (UCLK) input. 281 11.4 Usage Notes Newly added Rev. 5.00 Dec 12, 2005 page xii of lxxii Page 303 Previous Version 12.2.5 Individual Memory Control Register (MCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- 0 R/W Revised Version Bit: 15 14 13 12 11 10 9 8 7 -- 0 R/W 6 5 4 3 2 1 0 -- 0 R/W TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS RASD AMX3 AMX2 AMX1 AMX0 RFSH RMO 1 0 1 0 DE Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS 1 0 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W AMX3 AMX2 AMX1 AMX0 RFSH RMO DE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 and 14RAS Precharge Time (TPC1, TPC0): ... However, the number of cycles inserted immediately after the precharge all banks (PALL) command is issued when performing auto-refresh or the precharge (PRE) command is issued in bank-active mode is one fewer than the number of cycles during normal operation. Do not set TPC1 to 0 and TPC0 to 0 when in bankactive mode. Note: * Immediately after the precharge all banks (PALL) command is issued when performing auto-refresh or the precharge (PRE) command is issued in bank-active mode. 304 Bit 7--SDRAM Bank Active (RASD): Specifies whether SDRAM is put into bankactive mode or auto-precharge mode. The auto-precharge mode should be used if both area 2 and area 3 are set in SDRAM space and the bus width is 16 bits. Bit 7: RASD 0 1 Description Auto-precharge mode Bank-active mode (Initial value) ... However, the number of cycles inserted immediately after the precharge all banks (PALL) command is issued when performing auto-refresh is one fewer than the number of cycles during normal operation. Note: * Immediately after the precharge all banks (PALL) command is issued when performing auto-refresh. Bit 7Reserved: This bit is always read as 0. The write value should always be 0. Table deleted 309 12.2.6 PCMCIA Control Register (PCR) Bits 8, 1, and 0Area6 OE/WE Negate Address Delay (A6TEH2, A6TEH1, and A6TEH0): Bit 8: A6TEH2 1 Bit 1: A6TEH1 0 1 Bit 0: A6TEH0 0 1 0 1 Description 4.5-cycle delay Reserved Reserved Reserved 1 Bit 8: A6TEH2 1 Bit 1: A6TEH1 0 Bit 0: A6TEH0 0 1 0 1 Description 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay Rev. 5.00 Dec 12, 2005 page xiii of lxxii Page 385 Previous Version 14.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3) To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary. If any other address is specified, correct operation is not guaranteed. Revised Version To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary. When transferring data in 16byte units, always set a value at a 16-byte boundary (16n address) as the destination address. If any other address is specified, correct operation is not guaranteed. 433 14.4.2 Register Descriptions Compare-Match Timer Control/Status Register 0 (CMCSR0) The compare-match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates a compare-match occurrence, sets enable/disable of interrupts, and sets the incrementation clock. ... The compare-match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates a compare-match occurrence and sets the incrementation clock. ... 434 Bits 1 and 0clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to CMCNT from four internal clocks which are divided from the system clock (P). When the STR bit in CMSTR is set to 1, ... Compare-Match Counter 0 (CMCNT0) When the internal clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR bit in CMSTR is set to 1, ... When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in CMSTR is set to 1, ... These bits select the clock input to CMCNT from four clocks which are divided from the peripheral clock (P). When the STR0 bit in CMSTR is set to 1, ... 435 14.4.3 Operation Period Count Operation When the internal clock is selected with the CKS1, CKS0 bits in CMCSR0 and the STR bit of the CMSTR is set to 1, When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in CMSTR is set to 1, ... Rev. 5.00 Dec 12, 2005 page xiv of lxxii Page 436 Previous Version CMCNT0 Count Timing One of four clocks (P/4, P/8, P/16, P/64) which are divided from the clock (P) can be selected with the CKS1 and CKS0 bits in CMCSR0. ... Figure 14.28 Count Timing CK Internal clock Revised Version One of four peripheral clocks (P/4, P/8, P/16, P/64) which are divided from the clock (P) can be selected with the CKS1 and CKS0 bits in CMCSR0. ... Peripheral clock (P) CMT clock Peripheral clock (P) 437 Figure 14.29 Timing of CMF Setting CK Figure 14.30 Timing of CMF Clear by the CPU CK Peripheral clock (P) Item 14, 15, added 442 443 14.6 Usage Notes 15.1.1 Features * Selection of six counter input clocks for each channel: On-chip RTC output clock (16 kHz), P/4, P/16, P/64, and P/256 * Selection of six counter input clocks for each channel: On-chip RTC output clock (16 kHz), P/4, P/16, P/64, and P/256 Note: P is the internal clock for peripheral Note deleted modules and can be selected as 1/4, 1/2, or the same frequency as that of the CPU operating clock .) See section 10, On-Chip Oscillation Circuits, for more information on the clock pulse generator. * The maximum 2 MHz operating frequency for the 32-bit counter in each channel: Operate the SH7727 so that the clock input to each channel timer counter does not exceed the maximum operating frequency, by dividing the external clock and internal clock with the prescaler) Operate the SH7727 so that the clock input to each channel timer counter does not exceed the maximum operating frequency, by dividing the external clock and peripheral clock (P) with the prescaler. Rev. 5.00 Dec 12, 2005 page xv of lxxii Page 469 Previous Version 16.2.15 RTC Control Register 1 (RCR1) RCR1 is initialized to H'00 by a power-on reset. By a manual reset, bits except the CF flag are all initialized to 0, but the CF flag is undefined. When using the CF flag, it must be initialized beforehand. This register is not initialized in standby mode. Revised Version RCR1 is an 8-bit read/write register. The CIE, AIE, and AF bits are initialized by a power-on reset or manual reset. However, the value of the CF flag is undefined after a power-on reset or manual reset. It must therefore be initialized without fail before use. This register is not initialized in standby mode. Bit: Initial value: R/W: 7 CF -- R/W 6 -- 0 R Bit: Initial value: R/W: 7 CF 0 R/W 6 -- 0 R Bit 7--Carry Flag (CF): Bit 7: CF 0 Description No carry in R64CNT or RSECCNT. Clearing condition: When 0 is written to CF (Initial value) Bit 7: CF 0 Description No carry in R64CNT or RSECCNT. Clearing condition: When 0 is written to CF Rev. 5.00 Dec 12, 2005 page xvi of lxxii Page 472, 473 Previous Version 16.3.2 Setting the Time Figure 16.2 shows how to set the time after stopping the clock. This procedure is available to set the entire calendar and clock function. This procedure can be programmed easily. Revised Version Figures 16.2 (a) and 16.2 (b) show how to set the time after stopping the clock. This procedure can be used to set the entire calendar and clock function. It can be programmed easily. Usage Notes Stop clock, reset divider circuit Set seconds, minutes, hour, day, day of the week, month and year Write 1 to RESET and 0 to START in the RCR2 register 1. Initialization Timing for 64 Hz Counter (R64CNT) If it is necessary, after initializing the counter by means of the RESET bit in the RTC's RCR2 register, to confirm that the change has taken effect by reading the R64CNT value, wait at least 107 s after setting the RESET bit to 1 before reading the R64CNT counter. Note that the divider circuit (RTC prescaler) is also initialized when the RESET bit is set to 1. 2. Incrementing RSECCNT by Initializing R64CNT Either method (a) or method (b) below may be used. (a) After setting the RESET bit to 1 and confirming that R64CNT has been initialized, set the START bit to 1. This process is shown in figure 16.2 (a). Order is irrelevant Start clock Write 1 to START in the RCR2 register Reset the divider circuits (RTC prescaler and R64CNT) and set the counter. Figure 16.2 Setting the Time (b) Set the START bit to 1 and the RESET bit to 1 at the same time. This process is shown in figure 16.2 (b). Note that the processing indicated by the asterisk (*) in figure 16.2 (b) may be omitted if nothing is written to the RCR2 register during an interval of approximately 107 s after the START bit is set to 1. Confirm R64CNT is not 0 Stop clock Reset divider circuit Set seconds, minutes, hour, day, day of the week, month and year Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Confirm R64CNT is 0 No Yes Start clock Write 1 to START in the RCR2 register Figure 16.2(a) Setting the Time * Confirm R64CNT is not 0 Stop clock Reset divider circuit Set seconds, minutes, hour, day, day of the week, month and year Start clock Reset divider circuit Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Write 1 to RESET and 1 to START in the RCR2 register * Confirm R64CNT is 0 No Yes * Write to RCR2 Figure 16.2(b) Setting the Time 481 17.1.2 Block Diagram SCI pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. ... SCI pin I/O and data control is performed by bits 3 to 0 of SCPCR and bits 1 and 0 of SCPDR. ... H'8008 484 497 Table 17.2 Registers H'A888 17.2.8 Port SC Control Register (SCPCR)/Port SC Date Register (SCPDR) SCPCR Bit: 15 14 13 12 11 10 9 8 7 6 SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: R/W: 1 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W SCPCR Bit: 15 14 13 12 11 10 9 8 7 6 SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: R/W: 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 5.00 Dec 12, 2005 page xvii of lxxii Page 563 Previous Version 19.1.1 Features * On-chip modem control functions (RTS and CTS) Revised Version * On-chip modem control functions (RTS2 and CTS2) 564 Figure 19.1 SCIF Block Diagram Bus interface Bus interface Module data bus Internal data bus Module data bus Internal data bus SCFRDR2 (16stages) SCFTDR2 (16stages) RxD2 SCRSR2 SCTSR2 TxD2 SCPCR2 SCFDR2 SCFDR2 SCFCR2 SCSSR2 SCSCR2 SCSMR2 Transmit/ receive control SCBRR2 SCFRDR2 (16stages) SCFTDR2 (16stages) Baud rate generator P P/4 P/16 P/64 TxD2 RxD2 SCRSR2 SCTSR2 SCPCR2 SCFDR2 SCFDR2 SCFCR2 SCSSR2 SCSCR2 SCSMR2 Transmit/ receive control SCBRR2 Baud rate generator P P/4 P/16 P/64 Parity generation Parity check Clock RTS2 Parity generation Parity check Clock SCIF ERI TXI BRI BRI CTS2 SCIF ERI TXI BRI BRI 565 19.1.2 Block Diagram Figures 19.2 and 19.3 show SCIF I/O ports. Bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR control an input/output and data of the SCIF pins. ... Figure 19.2 and 19.3 show SCIF I/O ports. Bits 15, 14, 9, 8 of SCPCR and bits 7 and 4 of SCPDR control an input/output and data of the SCIF pins. ... 603 20.1.1 Features * Serial clock External clock or internal clock (P_CLK) are able to be used as clock source. External clock or peripheral clock (P) are able to be used as clock source. 604 20.1.2 Block Diagram Figure 20.1 SIOF Block Diagram P_CLK TXI RXI ERI CCI Peripheral clock (P) 32 PP-BUS TXI RXI ERI CCI 32 Peripheral bus Bus I/F Bus I/F 32 32 16 32 32 32 32 16 32 32 32 32 Control register Tx_FIFO 32 bits x 16 stages Rx_FIFO 32 bits x 16 stages Control register Tx_FIFO 32 bits x 16 stages Rx_FIFO 32 bits x 16 stages Tx control data Rx control data Tx control data Rx control data Baud rate 1/n MCLK generator Timing control P/S S/P Baud rate 1/n MCLK generator Timing control P/S S/P SIOF SIOMCLK SCK_SIO SIOFSYNC TXD_SIO RXD_SIO SIOMCLK SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Rev. 5.00 Dec 12, 2005 page xviii of lxxii Page 608 Previous Version 20.2.2 Clock Select Register (SISCR) * Bit 15Master Clock Source Choice (MSSEL): Use PCLK as master clock Revised Version Use Peripheral clock (P) as master clock 628 Figure 20.2 Serial Clock Supply System BRG E SIOMCLK P_CLK BRG E SIOMCLK Peripheral clock (P) 635 20.3.5 Control Data Interface (1) Control by Slot Positions (Master Mode 1) Note: When using this method, PCLK Note: When using this method, Peripheral should be used as the master clock (Master clock should be used as master clock (Master Clock Select (MSSEL) = 1). Clock Select (MSSEL) = 1). 651 679 20.4 Usage Notes Item 7, 8, added 22.1.2 Pin Configuration Table 22.1 Pin Configuration (Digital Transceiver Signal) Name TXDPLS pin TXDMNS pin TXENL pin Symbol USB1d_TXDPLS USB1d_TXDMNS USB1d_TXENL I/O Output Output Output Description D+ transmit output pin D- transmit output pin Driver output enable pin Name TXDPLS pin TXENL pin Symbol USB1d_TXDPLS USB1d_TXENL I/O Output Output Description D+ transmit output pin Driver output enable pin 709 23.6.3 Control Transfer Figure 23.8 Status Stage Operation (Control-In) Replaced 720 758 23.9 Usage Notes Newly added 24.7 Notes on Using USB Host with Versions Previous to the SH7727C Newly added Rev. 5.00 Dec 12, 2005 page xix of lxxii Page 759 Previous Version 25.1.1 Features * Supports 1/2/4/8/15/16-bpp (bit per pixel) color modes * Supports 1/2/4-bpp grayscale modes Revised Version * Supports 4/8/15/16-bpp (bit per pixel) color modes * Supports 1/2/4/6-bpp grayscale modes Bus clock (B) Peripheral clock (P) H'F60F 760 Figure 25.1 Block Diagram CKIO P clock 762 763 Table 25.2 Register Configuration H'F606 25.2.1 LCDC Input Clock Register (LDICKR) This LCDC can select CKIO (bus clock), the P clock, or the external clock as its operation clock source. ... Bits 13, and 12Input Clock Select (ICKSEL1 and ICKSEL0): CKIO is selected P clock is selected Bus clock (B) is selected Peripheral clock (P) is selected This LCDC can select the bus clock (B), the peripheral clock (P), or the external clock as its operation clock source. ... 766 25.2.2 LCDC Module Type Register (LDMTR) Bits 5 to 0--Module Interface Type Select (MIFTYP5 to MIFTYP0): If an STN or DSTN panel is selected, display control is performed using a 24-bit space-modulation FRC consisting of the 8bit R, G, and B included in the LCDC, ... If an STN or DSTN panel is selected, display control is performed using a 24-bit space-modulation FRC (Frame Rate Controller) consisting of the 8-bit R, G, and B included in the LCDC, ... 783 25.2.17 LCDC Power Management Mode Register (LDPMMR) Bit 4DON Pin Enable (DONE): Bit 4 DONE 0 1 Description Disabled: DON pin is masked and fixed low (Initial value) Bit 4 DONE 0 1 Description Disabled: DON pin is masked and fixed low Enabled: DON pin output is asserted and negated according to the power-on or power(Initial value) off sequence Enabled: DON pin output is asserted and negated according to the power-on or poweroff sequence 784 25.2.18 LCDC Power-Supply Sequence Period Register (LDPSPR) Bit: 15 ONA3 Initial value: R/W: 0 R/W 14 ONA2 0 R/W 13 ONA1 0 R/W 12 ONA0 0 R/W 11 ONB3 0 R/W 10 ONB2 0 R/W 9 ONB1 0 R/W 8 7 6 5 4 3 2 1 0 Bit: 15 ONA3 14 ONA2 1 R/W 13 ONA1 1 R/W 12 ONA0 1 R/W 11 ONB3 0 R/W 10 ONB2 1 R/W 9 ONB1 1 R/W 8 7 6 5 4 3 2 1 0 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W Initial value: R/W: 1 R/W Rev. 5.00 Dec 12, 2005 page xx of lxxii Page 786 Previous Version 25.3.1 LCD Module Sizes which can be Displayed in this LCDC Revised Version The overhead coefficient depends on the The overhead coefficient is 1.375 if the SDRAM in CL2 uses a 32-bit bus and 1.188 bus used by the SDRAM in CL2, as indicated below. if it uses a 16-bit bus. If the hardware rotation function is not used (ROT = 0), the overhead coefficient is 1.375 if a 32-bit bus is used and 1.188 if a 16-bit bus is used. If the hardware rotation function is used (ROT = 1), the overhead coefficient is determined by the access unit select (AU) setting and the bus width, as follows. Table added Access Unit Select (AU) Setting 4-burst operation 8-burst operation 16-burst operation 32-burst operation 32-Bit Bus 2.500 1.750 1.375 1.188 16-Bit Bus 1.750 1.375 1.188 1.094 787 to 793 816 820, 821 Table 26.1 List of Multiplexed Pins Port K K K L L M M M M M Port Function (Related Module) PTK2 in/out (port) PTK1 in/out (port) PTK0 in/out (port) PTL7 in (port) PTL2 in (port) PTM7 in (port)/PINT7 in (INTC) PTM6 in (port)/PINT6 in (INTC) PTM5 in (port)/PINT5 in (INTC) PTM4 in (port)/PINT4 in (INTC) PTM3 in (port)/ PINT10 in (INTC) Other Function 1 (Related Module) CS4 out (BSC) AFE_RLYCNT out (AFE) AFE_HC1 out (AFE) AN7 in (ADC)/DA0 out (DAC) AN2 in (ADC) AFE_FS in (AFE) AFE_RXIN in (AFE) AFE_TXOUT out (AFE) AFE_RDET in (AFE) LCD15 out (LCDC) USB1d_RCV0 in (USB)*2 USB1d_SPEED0 out (USB)*2 USB1d_TXSE0 out (USB)*2 USB1d_TXMNS0 out (USB) *2 USB1d_DMNS0 in (USB)*2 USB1d_DPLS0 in (USB)*2 Other Function 2 (Related Module) 25.3.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (SDRAM) Replaced 25.5 Usage Notes Newly added Port K K K L L M M M M M Port Function (Related Module) PTK2 in/out (port) PTK1 in/out (port) PTK0 in/out (port) PTL7 in (port) PTL2 in (port) PTM7 in (port)/PINT7 in (INTC) PTM6 in (port)/PINT6 in (INTC) PTM5 in (port)/PINT5 in (INTC) PTM4 in (port)/PINT4 in (INTC) PTM3 in (port)/ PINT10 in (INTC) Other Function 1 (Related Module) CS4 out (BSC) AFE_RLYCNT out (AFE) AFE_HC1 out (AFE) AN7 in (ADC)/DA0 out (DAC) AN2 in (ADC) AFE_FS in (AFE) AFE_RXIN in (AFE) AFE_TXOUT out (AFE) AFE_RDET in (AFE) LCD15 out (LCDC) Other Function 2 (Related Module) USB1d_DMNS in (USB)* USB1d_DPLS in (USB)* 2 2 USB1d_RCV in (USB)* 2 2 USB1d_SPEED out (USB)* USB1d_TXSE0 out (USB)* 2 Port SCPT Port Function (Related Module) SCPT4 in (port)*1 SCPT4 out (port)*1 Other Function 1 (Related Module) RxD2 in (UART ch 3) TxD2 out (UART ch 3) SCK0 in/out (UART ch 1) RxD0 in (UART ch 1) TxD0 out (UART ch 1) Other Function 2 (Related Module) Port SCPT Port Function (Related Module) SCPT4 in (port)*1 SCPT4 out (port)*1 Other Function 1 (Related Module) RxD2 in (SCIF) TxD2 out (SCIF) SCK0 in/out (SCI) RxD0 in (SCI) TxD0 out (SCI) Other Function 2 (Related Module) SCPT SCPT SCPT1 in/out (port) SCPT0 in (port)*1 SCPT0 out (port)*1 SCPT SCPT SCPT1 in/out (port) SCPT0 in (port)*1 SCPT0 out (port)*1 Rev. 5.00 Dec 12, 2005 page xxi of lxxii Page 826 Bit (2n + 1) PDnMD1 0 0 1 1 Bit 2n PDnMD0 0 1 0 1 Previous Version 26.3.4 Port D Control Register (PDCR) Bit (2n + 1) Pin Function Other function (see table 26.1) Port output (n = value other than 4 or 6), reserved (n = 4 or 6) Port input (Pullup MOS: on) Port input (Pullup MOS: off) PDnMD1 0 0 1 1 Bit 2n PDnMD0 0 1 0 1 Revised Version Pin Function Other function (see table 26.1) Port output (n = value other than 4 or 6), reserved (n = 4 or 6) Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) 838 26.3.13 SC Port Control Register (SCPCR) Bits 5, 4--SCP2 Mode 1, 0 (SCP2MD1, SCP2MD0): Bit 5 SCP2MD1 0 0 1 1 Bit 4 SCP2MD0 0 1 0 1 Pin Function Transmit data output 1 (TxD1) Receive data input 1 (RxD1) General output (SCPT[2] output pin) Receive data input 1 (RxD1) SCPT[2] input pin pullup (input pin) Transmit data output 1 (TxD1) General input (SCPT[2] input pin) Transmit data output 1 (TxD1) (Initial value) 0 1 1 1 0 1 Bit 5 SCP2MD1 0 Bit 4 SCP2MD0 0 Pin Function Transmit data output 1 (TxD_SiO) Receive data input 1 (RxD_SiO) General output (SCPT[2] output pin) Receive data input 1 (RxD_SiO) SCPT[2] input pin pullup (input pin) Transmit data output 1 (TxD_SiO) General input (SCPT[2] input pin) Transmit data output 1 (TxD_SiO) (Initial value) Note: There is no combination of simultaneous I/O of SCPT[2] because one bit (SCP2DT) is accessed using two pins of TxD1 and RxD1. Note: There is no combination of simultaneous I/O of SCPT[2] because one bit (SCP2DT) is accessed using two pins of TxD_SiO and RxD_SiO. When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD1 pin is in the output state. When the TE bit is cleared to 0, the TxD1 pin is in the highimpedance state. When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD_SiO pin is in the output state. When the TE bit is cleared to 0, the TxD_SiO pin is in the high-impedance state. 909 30.3.3 Usage Notes Setting procedure when Using PC Card Controller: 1. Set bit 0 (A6PCM) in bus control register 1 (BCR1) in the bus state controller to 1. 2. Set bit 4 (P0USE) in the area 6 general control register in the PC card controller to 1. 3. Set the pin function controller to custom PC card pin functions ("other functions"). 1. Drive pin ASEMD0 high. 2. Set bit 0 (A6PCM) in bus control register 1 (BCR1) in the bus state controller to 1. 3. Set bit 4 (P0USE) in the area 6 general control register in the PC card controller to 1. 4. Set the pin function controller to custom PC card pin functions ("other functions"). Rev. 5.00 Dec 12, 2005 page xxii of lxxii Page 918, 919 Previous Version Table 31.3 Correspondence between SH7727 Pins and Boundary-Scan Register Bit 170 169 168 137 136 135 110 109 108 Pin Name PTM5/PINT5/AFE_TXOUT/ USB1d_TXSE0 PTM4/PINT4/AFE_RDET/ USB1d_TXDMNS Reserved/USB1d_SUSPEND0 MD0 PTM4/PINT4/AFE_RDET/ USB1d_TXDMNS Reserved/USB1d_SUSPEND0 PTF0/PCC0VS2/Reserved PTM4/PINT4/AFE_RDET/ USB1d_TXDMNS Reserved/USB1d_SUSPEND0 I/O Control IN IN IN OUT OUT OUT Control Control Bit 170 169 168 137 136 135 110 109 108 Revised Version Pin Name PTM5/PINT5/AFE_TXOUT/ USB1d_TXSE0 PTM4/PINT4/AFE_RDET Reserved/USB1d_SUSPEND0 MD0 PTM4/PINT4/AFE_RDET Reserved/USB1d_SUSPEND0 PTF0/PCC0VS2/Reserved PTM4/PINT4/AFE_RDET Reserved/USB1d_SUSPEND0 I/O Control IN IN IN OUT OUT OUT Control Control 925 32.1 Absolute Maximum Ratings Caution: Item 3 added 927, 928 Table 32.2 DC Characteristics (1) Item Power supply voltage Symbol VCCQ Min 3.0 2.6 Typ -- -- Max 3.6 3.6 Unit V Measurement Conditions HD6417727F160, HD6417727BP160V HD6417727F100, HD6417727BP100V See note *4 for applied voltage when mounted. VCC, VCC-PLL1, VCC-PLL2, VCC-RTC*1 1.70 -- 2.05 HD6417727F160, HD6417727BP160V See note *4 for applied voltage when mounted. 1.60 -- 2.05 HD6417727F100, HD6417727BP100V See note *4 for applied voltage when mounted. Analog (A/D, During A/D D/A) power- conversion supply During A/D current and D/A conversion Idle AICC -- -- 0.8 2.4 2 6 mA mA Analog (A/D, During A/D D/A) power- conversion supply During A/D current and D/A conversion Idle Item Power supply voltage Symbol VCCQ Min 3.0 2.6 VCC, VCC-PLL1, VCC-PLL2, VCC-RTC*1 AICC -- -- 0.8 2.4 2 6 mA mA 1.70 1.60 Typ -- -- -- -- Max 3.6 3.6 2.05 2.05 Unit V Measurement Conditions 160 MHz products 100 MHz products 160 MHz products 100 MHz products -- 0.01 5.0 mA Ta = 25C -- 0.01 5.0 mA Notes: *3 Current dissipation values shown are for VIHmin = VccQ - 0.5 V and VILmax = 0.5 V with 5 pF load. *4 The voltage range that can be applied depends on the operating frequency setting. Be sure check the operating frequency range of the AC characteristics. *5 There is no stipulation regarding the power supply in standby mode when there is no RTC clock input. 3. Current dissipation values are for VIH min = VccQ - 0.5 V and VIL max = 0.5 V with all output pins in the no-load state. 4. There is no stipulation regarding the power supply in standby mode when there is no RTC clock input. Rev. 5.00 Dec 12, 2005 page xxiii of lxxii Page 930 Previous Version 32.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Regarding the power supply and frequency specifications of the individual products, refer to tables 32.2 and 32.4. When the measuring condition range in the timing chart is wider than that in table 32.2 or 32.4, the conditions listed in table 32.2 or 32.4 apply. AC specifications vary depending on the product, so should be checked before the chip is used. Revised Version In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Regarding the power supply and frequency specifications of the individual products, refer to figure 32.2, tables 32.2 and 32.4. 931 Figure 32.2 Power Supply Voltage and Operating Frequency Newly added Table 32.4 Maximum Operating Frequencies (1) Item CPU, cache, TLB (I) External bus (B) or CKIO I/O frequency Peripheral modules (P) Symbol f Min 24 24 24 6 Max 100 33.4 50 33.4 Unit MHz Power Supply Voltage Conditions VCC = 1.60 to 2.05 V, VCCQ = 2.6 to 3.6 V VCC = 1.60 to 2.05 V, VCCQ= 2.6 to 3.6 V VCC = 1.70 to 2.05 V, VCCQ= 3.0 to 3.6 V VCC = 1.60 to 2.05 V, VCCQ = 2.6 to 3.6 V Products HD6417727F100, HD6417727BP100V 932 Item CPU, cache, TLB (I) External bus (B) or CKIO I/O frequency Symbol f Min 24 24 24 6 Max 100 33.34 50 33.34 Unit MHz Power Supply Voltage Conditions VCC = 1.60 to 2.05 V VCCQ = 2.6 to 3.6 V VCC = 1.60 to 2.05 V VCCQ = 2.6 to 3.6 V VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.60 to 2.05 V VCCQ = 2.6 to 3.6 V Reference Products -- Table 32.5 Table 32.6 -- 100 MHz products Peripheral modules (P) 932 Table 32.4 Maximum Operating Frequencies (2) Item CPU, cache, TLB (I) Symbol f Min 24 24 External bus (B) or CKIO I/O frequency Peripheral modules (P) 24 24 6 Max 144 160 48 66.67 33.4 Unit MHz Power Supply Voltage Conditions VCC = 1.70 to 2.05 V, VCCQ = 3.0 to 3.6 V VCC = 1.75 to 2.05 V, VCCQ = 3.0 to 3.6 V VCC = 1.70 to 2.05 V, VCCQ = 3.0 to 3.6 V VCC = 1.75 to 2.05 V, VCCQ = 3.0 to 3.6 V VCC = 1.70 to 2.05 V, VCCQ = 3.0 to 3.6 V Products HD6417727F160, HD6417727BP160V Item CPU, cache, TLB (I) Symbol f Min 24 24 Max 144 160 50 66.67 33.34 Unit MHz Power Supply Voltage Conditions VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.75 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.75 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V Reference Products -- -- Table 32.7 Table 32.8 -- 160 MHz products External bus (B) or CKIO I/O frequency 24 24 6 Peripheral modules (P) Rev. 5.00 Dec 12, 2005 page xxiv of lxxii Page 933 Previous Version Table 32.5 Clock Timing (1) Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.6 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, external bus maximum operating frequency = 33 MHz Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc Min 6 30.3 7 7 -- -- 24 30.3 7 7 -- -- 24 30.3 Max 33 167 -- -- 6 6 33 40 -- -- 6 6 33 40 Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns 32.3 32.2 Figure 32.1 Revised Version Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, 100 MHz products Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc Min 6 30 9 9 -- -- 24 30 9 9 -- -- 24 30 Max 33.34 166.7 -- -- 6 6 33.34 41.7 -- -- 6 6 33.34 41.7 Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns 32.5 32.4 Figure 32.3 934 Table 32.5 Clock Timing (2) Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.75 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, external bus maximum operating frequency = 66.67 MHz Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock output frequency CKIO clock output cycle time Power-on oscillation settling time Symbol f EX tEXcyc t EXL t EXH f CKI tCKIcyc t CKIL tCKIH f OP tcyc tOSC1 Min 6 15.2 1.5 1.5 24 15.2 1.5 1.5 24 15.2 10 Max 66.67 167 -- -- 66.67 40 -- -- 66.67 -- -- Unit MHz ns ns ns MHz ns ns ns MHz ns ns 32.4 32.3 32.2 Figure 32.1 Table 32.6 Clock Timing (2) Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.70 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, 100 MHz products Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock output frequency CKIO clock output cycle time Power-on oscillation settling time Symbol f EX tEXcyc t EXL t EXH f CKI tCKIcyc t CKIL tCKIH f OP tcyc tOSC1 Min 6 20 4 4 24 20 4 4 24 20 10 Max 50 166.7 -- -- 50 41.7 -- -- 50 41.7 -- Unit MHz ns ns ns MHz ns ns ns MHz ns ms 32.6 32.5 32.4 Figure 32.3 935 936 938 Figure 32.3 CKIO Clock Output Timing tCK2D tCK2D Table 32.7 Clock Timing (3) Newly added Table 32.8 Clock Timing (4) Newly added Figure 32.5 CKIO Clock Output Timing tCK2D tCK2D CKIO2 (output) VIH CKIO2 (output) tCK2OF tCK2OR VOH VOH VOL tCK2OF VOL VOH tCK2OR Rev. 5.00 Dec 12, 2005 page xxv of lxxii Page 942 Previous Version Table 32.6 Control Signal Timing 33 MHz* Min RESETP pulse width 1 RESETP setup time* RESETP hold time RESETM pulse width RESETM setup time RESETM hold time BREQ setup time BREQ hold time 1 NMI setup time * NMI hold time IRQ5-IRQ0 setup time * IRQ5-IRQ0 hold time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer-on time 1 Bus buffer-on time 2 1 2 Revised Version Table 32.9 Control Signal Timing 66.67 MHz* Min 20* 23 2 12* 3 34 10 3 10 4 10 4 -- -- 0 0 0 0 5 4 3 Max -- -- -- -- -- -- -- -- -- -- -- -- 10 16 15 15 15 15 Max -- -- -- -- -- -- -- -- -- -- -- -- 10 16 15 15 15 15 Min RESETP pulse width 1 RESETP setup time* RESETP hold time RESETM pulse width RESETM setup time RESETM hold time BREQ setup time BREQ hold time 1 NMI setup time * NMI hold time IRQ5-IRQ0 setup time * IRQ5-IRQ0 hold time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer-on time 1 Bus buffer-on time 2 1 Max -- -- -- tRESPW tRESPS tRESPH tRESMW tRESMS tRESMH tBREQS tBREQH 20 23 2 12 3 34 10 3 tRESPW tRESPS tRESPH tRESMW tRESMS tRESMH tBREQS tBREQH 20* 23 2 12 3 34 10 3 10 4 10 4 -- -- 0 0 0 0 2 *3 -- -- -- -- -- -- -- -- -- 10 16 15 15 15 15 tNMIS tNMIH tIRQS tIRQH tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2 10 4 10 4 -- -- 0 0 0 0 tNMIS tNMIH tIRQS tIRQH tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2 Notes: *1 RESETP, NMI and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock falls. When using as IRL, please observe the setup time. *2 When Vcc = 1.6 to 2.05 V and VccQ = 2.6 to 3.6 V, the upper limit of the external bus clock is 33 MHz. *3 When Vcc = 1.75 to 2.05 V and VccQ = 3.0 to 3.6 V, the upper limit of the external bus clock is 66.67 MHz. *4 In the standby mode, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100 s). When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 s). 1. RESETP, NMI and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock falls. When using as IRL, please observe the setup time. 2. In the standby mode, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100 s). When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 s). Rev. 5.00 Dec 12, 2005 page xxvi of lxxii Page 945, 946 Previous Version Table 32.7 Bus Timing 33 MHz* Item Address delay time Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read/write delay time Read/write hold time Symbol tAD tAS tAH* tBSD tCSD1 tCSD2 tRWD tRWH 3 1 Revised Version Table 32.10 Bus Timing 66.67 MHz* 2 Min 1.5 0 7 -- 1.5 1 1.5 0 -- 6 7 Max 16 -- -- 12 12 12 10 -- 10 -- -- -- -- 10 14 Min 1.5 0 7 -- 1.5 1 1.5 0 -- 6 7 0 2 1 -- Max 13 -- -- 12 12 12 10 -- 10 -- -- -- -- 10 14 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Item Address delay time Symbol Min tAD 1.5 1.5 Max 13 16 -- -- 12 12 12 10 -- 10 -- -- -- -- 10 14 Unit ns Conditions Vcc = 1.70 to 2.05 V VccQ = 3.0 to 3.6 V Other than the above Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read/write delay time Read/write hold time tAS tAH *1 tBSD tCSD1 tCSD2 tRWD tRWH 0 7 -- 1.5 1 1.5 0 -- 6 7 2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read strobe delay time tRSD Read data setup time 1 tRDS1 Read data setup time 2 tRDS2 Read data hold time 1 Read data hold time 2 tRDH1* tRDH2 4 Read strobe delay time tRSD Read data setup time 1 tRDS1 Read data setup time 2 tRDS2 Read data hold time 1 Read data hold time 2 tRDH1* tRDH2 0 2 1 -- 0 2 1 -- Write enable delay time tWED Write data delay time 1 tWDD1 Write enable delay time tWED Write data delay time 1 tWDD1 Write data delay time 2 tWDD2 -- 13 -- 13 ns Write data delay time 2 tWDD2 -- 13 ns 33 MHz* Item Write data hold time 1 Symbol tWDH1 Min 1.5 1 66.67 MHz* Min 1.5 Max -- 2 Max -- Unit ns Item Write data hold time 1 Symbol Min tWDH1 1.5 Max -- Unit ns Conditions Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time tWDH2 tWDH3 tWDH4 tWTS 1.5 2 2 6 -- -- -- -- 1.5 2 2 5 -- -- -- -- ns ns ns ns Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time tWDH2 tWDH3 tWDH4 tWTS 1.5 2 2 5 6 -- -- -- -- -- -- ns ns ns ns Vcc = 1.70 to 2.05 V VccQ = 3.0 to 3.6 V Other than the above ns WAIT hold time tWTH 0 -- 0 -- ns WAIT hold time tWTH 0 RAS delay time 2 CAS delay time 2 DQM delay time CKE delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time DACK delay time 1 tRASD2 tCASD2 tDQMD tCKED tICRSD tICWSD tIO16S tIO16H tDAKD1 1.5 1.5 1.5 1.5 -- -- 12 4 -- 12 12 10 12 12 12 -- -- 10 1.5 1.5 1.5 1.5 -- -- 12 4 -- 12 12 10 12 12 12 -- -- 10 ns ns ns ns ns ns ns ns ns RAS delay time 2 CAS delay time 2 DQM delay time CKE delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time DACK delay time 1 tRASD2 tCASD2 tDQMD tCKED tICRSD tICWSD tIO16S tIO16H tDAKD1 1.5 1.5 1.5 1.5 -- -- 12 4 -- 12 12 10 12 12 12 -- -- 10 ns ns ns ns ns ns ns ns ns Notes: *1 When Vcc = 1.6 to 2.05 V and VccQ =2.6 to 3.6 V, the upper limit of the external bus clock is 33 MHz. *2 When Vcc = 1.75 to 2.05 V and VccQ = 3.0 to 3.6 V, the upper limit of the external bus clock is 66.67 MHz. *3 tAH: This is to deal with the latest negate timing of CSn, RD, or WEn. *4 tRDH1: This is to deal with the earliest negate timing of CSn or RD. 1. tAH: This is to deal with the latest negate timing of CSn, RD, or WEn. 2. tRDH1: This is to deal with the earliest negate timing of CSn or RD. Rev. 5.00 Dec 12, 2005 page xxvii of lxxii Page 949 Previous Version Figure 32.17 Basic Bus Cycle (External Wait, WAITSEL = 1) tRDS1 D31 to D0 (read) D31 to D0 (read) Revised Version Figure 32.19 Basic Bus Cycle (External Wait, WAITSEL = 1) tRDS1 Note added Notes: tRDH1: Specified based on the earliest negate timing of CSn or RD. tAH: Specified based on the latest negate timing of CSn, RD, or WEn. 971 Table 32.8 Peripheral Module Signal Timing -66.67 Min Max Table 32.11 Peripheral Module Signal Timing Min Max Note: * Pcyc stands for "P clock cycle." 973 Figure 32.42 I/O Port Timing PORT 7 to 0 (read) (B:P clock ratio = 1:1) Note: * Pcyc stands for "peripheral clock (P) cycle." Figure 32.44 I/O Port Timing PORT A to H, J to M, SC (read) (bus clock:peripheral clock ratio = 1:1) PORT A to H, J to M, SC (read) (bus clock:peripheral clock ratio = 1:1/2) PORT A to H, J to M, SC (read) (bus clock:peripheral clock ratio = 1:1/4) PORT A to H, J to M, SC (write) PORT 7 to 0 (read) (B:P clock ratio = 1:2) PORT 7 to 0 (read) (B:P clock ratio = 1:4) PORT 7 to 0 (write) 974 Figure 32.45 TCK Input Timing tTCKcyc tTCKH TCK (input) VIH VIH 1/2VccQ VIL VIL tTCKf VIL 1/2VccQ tTCKf tTCKL Figure 32.47 TCK Input Timing tTCKcyc tTCKH TCK (input) VIH VIH 1/2 VccQ VIL VIL tTCKf VIH 1/2 VccQ tTCKf tTCKL Note: When clock is input from TCK pin Rev. 5.00 Dec 12, 2005 page xxviii of lxxii Page 981 Item UCLK external input clock frequency (48 MHz) Clock rise time Clock fall time Duty (tHIGH/tLOW) Previous Version Table 32.12 USB Module Signal Timing Symbol tFREQ tR48 tF48 tDUTY Min 47.9 -- -- 90 Max 48.1 2 2 110 Unit MHz ns ns % Figure 32.56 Item UCLK external input clock frequency (48 MHz) Clock rise time Clock fall time Revised Version Table 32.15 USB Module Signal Timing Symbol tFREQ tR48 tF48 Min 47.9 -- -- Max 48.1 6 6 Unit MHz ns ns Figure 32.58 983 Table 32.15 AFEIF Module Signal Timing Note: tPCYC is the cycle time (ns) of the peripheral clock (P clock). Table 32.18 AFEIF Module Signal Timing Note: tPCYC is the cycle time (ns) of the peripheral clock (P). 985 32.3.14 AC Characteristics Measurement Conditions * Input pulse level: Vss to 3.0 V (where RESETP, RESETM, ASEMD0, IRL3 to IRL0, ADTRG, PINT[15] to PINT[0], CA, NMI, IRQ5 to IRQ0, CKIO, and MD5 to MD0 are within VssQ to VccQ) * Input pulse level: VssQ to 3.0 V (where RESETP, RESETM, ASEMD0, IRL3 to IRL0, ADTRG, PINT[15] to PINT[0], CA, NMI, IRQ5 to IRQ0, CKIO, and MD5 to MD0 are within VssQ to VccQ) Po werOn Reset V Release/ Open Bus Privileges I/I/I/O 991, 992 Table A.1 Pin Functions (cont) Type AFE/USB digital/port related Signal Name (Initial Status: Bold) Pin No. (HQFP) I/O I/I/I/O PowerManual On Reset Reset V I/I/I/O Standby Z(V)/I/Z/O Release/ Open Bus Privileges I/I/I/O Type AFE/USB digital/port related Signal Name (Initial Status: Bold) Pin No. (HQFP) I/O I/I/I/O Manual Reset I/I/I/O Standby Z(V)/I/Z/O 118, 119, PTM[7]/PINT[7]/ AFE_FS/USB1d_RCV, 120 PTM[6]/PINT[6]/ AFE_RXIN/USB1d_SPEED, PTM[5]/PINT[5]/ AFE_TXOUT/ USB1d_TXSE0 PTM[4]/PINT[4]/ AFE_RDET/ USB1d_TXDMNS USB1d_SUSPEND 121 118, 119, PTM[7]/PINT[7]/ 120 AFE_FS/USB1d_RCV, PTM[6]/PINT[6]/ AFE_RXIN/USB1d_SPEED, PTM[5]/PINT[5]/ AFE_TXOUT/ USB1d_TXSE0 PTM[4]/PINT[4]/ AFE_RDET USB1d_SUSPEND 121 122 194 196 197 198, 201 I/I/I/O V I/I/I/O Z(V)/I/Z/O I/I/I/O I/I/I O I/IO IO/IO IO/IO I/I V O I I I Z I/I/I O Z/P Z/P Z/P Z/I Z(V)/I/Z O Z/K Z/K K/K Z/Z I/I/I O I/P IO/P IO/P I/Z 122 194 196, 197 198, 201 O I/IO IO/IO I/I O I I Z O Z/P Z/P Z/I O Z/K Z/K Z/Z O I/P IO/P I/Z Serial related SIOMCLK/SCPT[3] SCK_SIO/SCPT[5], SIOFSYNC/SCPT[6] RxD0/SCPT[0], RxD2/SCPT[4] Serial related SIOMCLK/SCPT[3] SCK_SIO/SCPT[5] SIOFSYNC/SCPT[6] RxD0/SCPT[0], RxD2/SCPT[4] 997 Table A.2 Treatment of Unused Pins (cont) Type AFE/USB digital/port related Signal Name (Initial Status: Bold) Pin No (HQFP) Pin No (CSP) V19, T18, V18 I/O Treatment when Not Used Type AFE/USB digital/port related Signal Name (Initial Status: Bold) Pin No (HQFP) Pin No (CSP) V19, T18, V18 I/O Treatment when Not Used PTM[7]/PINT[7]/AFE_FS/ 118, 119, 120 USB1d_RCV, PTM[6]/PINT[6]/AFE_RXIN/ USB1d_SPEED, PTM[5]/PINT[5]/AFE_TXOUT/ USB1d_TXSE0 PTM[4]/PINT[4]/AFE_RDET/ USB1d_TXDMNS USB1d_SUSPEND 121 122 I/I/I/O Open 118, 119, 120 PTM[7]/PINT[7]/AFE_FS/ USB1d_RCV, PTM[6]/PINT[6]/AFE_RXIN/ USB1d_SPEED, PTM[5]/PINT[5]/AFE_TXOUT/ USB1d_TXSE0 PTM[4]/PINT[4]/AFE_RDET 121 Reserved/USB1d_SUSPEND 122 I/I/I/O Open W19 V16 I/I/I/O Open O Open W19 V16 I/I/I O Open Open Rev. 5.00 Dec 12, 2005 page xxix of lxxii Page 1001 Previous Version Table A.3 Pin Status (Normal Memory/Little Endian) (cont) Note: 2. Unused pins can be switched to port function, pull-up, or pull-down. Revised Version Note: 2. Unused pins can be switched to port function, pull-up. 1003 Table A.4 Pin Status (Normal Memory/Big Endian) (cont) Note: 2. Unused pins can be switched to port function, pull-up, or pull-down. Note: 2. Unused pins can be switched to port function, pull-up. 1005 Table A.5 Pin Status (Burst ROM/Little Endian) (cont) Note: 2. Unused pins can be switched to port function, pull-up, or pull-down. Note: 2. Unused pins can be switched to port function, pull-up. 1007 Table A.6 Pin Status (Burst ROM/Big Endian) (cont) Note: 2. Unused pins can be switched to port function, pull-up, or pull-down. Note: 2. Unused pins can be switched to port function, pull-up. 1011 Table A.9 Pin Status (PCMCIA/Little Endian) (cont) Note: 2. Unused pins can be switched to port function, pull-up, or pull-down. Note: 2. Unused pins can be switched to port function, pull-up. 1013 Table A.10 Pin Status (PCMCIA/Big Endian) (cont) Note: 2. Unused pins can be switched to port function, pull-up, or pull-down. Note: 2. Unused pins can be switched to port function, pull-up. 1018, Table B.1 Memory-Mapped Control 1019, Registers (Address Map) 1021 Control Register SIRCR SITMR SIFPR PACR PBCR SDIR SDDR/SDDRH SDDRL IPRF IPRG HcRhPortStatus2 (USBHRPS2) LDPR00 LDICKR Module*1 Bus*2 Address*4 Size (Bits) 32 16 16 16 16 16 16/32 16 16 16 32 32 16 SIOF SIOF SIOF PORT PORT UDI UDI UDI PPCNT PPCNT USBH LCDC LCDC P2 P2 P2 P P I2 I2 I2 P2 P2 P2 P2 P2 H'040000EC H'040000FC H'040000FE H'04000100 H'04000102 H'04000200 H'04000208 H'0400020A H'04000220 H'04000222 H'04000458 H'04000800 H'04000C00 32 16 16 16 16 16 16/32 16 16 16 32 32 16 Access Size (Bits)*3 Control Register SIRCR PACR PBCR SDIR IPRF IPRG HcRhPortStatus2 (USBHRPS2) LDPR00 to LDPRFF LDICKR Module*1 SIOF PORT PORT H-UDI PPCNT PPCNT USBH LCDC LCDC Bus*2 P2 P P I2 P2 P2 P2 P2 P2 Address*4 H'040000EC H'04000100 H'04000102 H'04000200 H'04000220 H'04000222 H'04000458 H'04000800 to H'04000BFC H'04000C00 Size (Bits) 32 16 16 16 16 16 32 32 16 Access Size (Bits)*3 32 16 16 16 16 16 32 32 16 Rev. 5.00 Dec 12, 2005 page xxx of lxxii Page 1024 Previous Version Appendix C Product Lineup Model Name HD6417727F160B HD6417727BP160B HD6417727F100B HD6417727BP100B Package 240-pin plastic HQFP (FP-240B) 240-pin CSP (BP-240A) 240-pin plastic HQFP (FP-240B) 240-pin CSP (BP-240A) Model Name Revised Version Package 240-pin plastic HQFP (PRQP0240KC-B) 240-pin CSP (PLBG0240JA-A) 240-pin plastic HQFP (PRQP0240KC-B) 240-pin CSP (PLBG0240JA-A) HD6417727F160C HD6417727BP160C HD6417727F100C HD6417727BP100C 1025 Figure D.1 Package Dimensions (FP-240B) Figure D.2 Package Dimensions (BP-240A) Figure D.1 Package Dimensions (PRQP0240KC-B) Replaced Figure D.2 Package Dimensions (PLBG0240JA-A) Replaced 1026 1027 E.1 Determining the Version Number Based on the Markings on the Chip (1) HQPF-240 Package Version Previous to SH7727B SH7727B "B" indication (1) HQFP-240 Package Version Previous to SH7727B SH7727B "B" indication SH7727C "C" indication 100 0124 6417727 SH3-DSP 100 HITACHI 0124 BF80128 JAPAN 6417727 SH3-DSP 100 HITACHI B 0124 BF80128 JAPAN 6417727F SH3-DSP 100 HITACHI 0124 BF80128 JAPAN 6417727F SH3-DSP 100 HITACHI B 0124 BF80128 JAPAN 6417727F SH3-DSP C BF80128 Note: Once stocks bearing Hitachi markings are exhausted, chips bearing Renesas markings may begin to appear. (2) CSP-240 Package Version Previous to SH7727B 6417727BP 100 BF80128 0124 JAPAN SH7727B "B" indication 6417727BP 100 B BF80128 0124 JAPAN (2) CSP-240 Package Version Previous to SH7727B 6417727BP 100 BF80128 0124 JAPAN SH7727B 6417727BP 100 B BF80128 0124 JAPAN "B" indication SH7727C 6417727BP 100 C BF80128 0124 JAPAN "C" indication Rev. 5.00 Dec 12, 2005 page xxxi of lxxii Rev. 5.00 Dec 12, 2005 page xxxii of lxxii Contents Section 1 Overview and Pin Functions ......................................................................... 1.1 1.2 1.3 Features ............................................................................................................................. Block Diagram .................................................................................................................. Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1 1 8 9 9 11 Section 2 CPU ...................................................................................................................... 21 2.1 Registers............................................................................................................................ 2.1.1 General Purpose Registers ................................................................................... 2.1.2 Control Registers ................................................................................................. 2.1.3 System Registers.................................................................................................. 2.1.4 DSP Registers ...................................................................................................... Data Format ...................................................................................................................... 2.2.1 Data Format in Registers (Non-DSP Type) ......................................................... 2.2.2 DSP-Type Data Format........................................................................................ 2.2.3 Data Format in Memory....................................................................................... Features of CPU Core Instructions.................................................................................... Instruction Formats ........................................................................................................... 2.4.1 CPU Instruction Addressing Modes..................................................................... 2.4.2 DSP Data Addressing .......................................................................................... 2.4.3 CPU Instruction Formats ..................................................................................... 2.4.4 DSP Instruction Formats...................................................................................... Instruction Set ................................................................................................................... 2.5.1 CPU Instruction Set ............................................................................................. DSP Extended-Function Instructions ................................................................................ 2.6.1 Introduction.......................................................................................................... 2.6.2 Added CPU System Control Instructions............................................................. 2.6.3 Single and Double Data Transfer for DSP Data Instructions............................... 2.6.4 DSP Operation Instruction Set ............................................................................. 21 25 27 31 31 38 38 38 40 40 44 44 48 54 58 64 64 79 79 80 82 85 2.2 2.3 2.4 2.5 2.6 Section 3 Memory Management Unit (MMU) ........................................................... 97 3.1 Overview........................................................................................................................... 3.1.1 Features................................................................................................................ 3.1.2 Role of MMU....................................................................................................... 3.1.3 SH7727 MMU ..................................................................................................... 3.1.4 Register Configuration......................................................................................... Register Description.......................................................................................................... 97 97 97 99 103 103 3.2 Rev. 5.00 Dec 12, 2005 page xxxiii of lxxii 3.3 3.4 3.5 3.6 3.7 TLB Functions .................................................................................................................. 3.3.1 Configuration of the TLB .................................................................................... 3.3.2 TLB Indexing....................................................................................................... 3.3.3 TLB Address Comparison ................................................................................... 3.3.4 Page Management Information ............................................................................ MMU Functions................................................................................................................ 3.4.1 MMU Hardware Management ............................................................................. 3.4.2 MMU Software Management .............................................................................. 3.4.3 MMU Instruction (LDTLB)................................................................................. 3.4.4 Avoiding Synonym Problems .............................................................................. MMU Exceptions.............................................................................................................. 3.5.1 TLB Miss Exception ............................................................................................ 3.5.2 TLB Protection Violation Exception ................................................................... 3.5.3 TLB Invalid Exception......................................................................................... 3.5.4 Initial Page Write Exception ................................................................................ 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) ................................................................................................ 3.5.6 MMU Exception in Repeat Loop......................................................................... Memory-Mapped TLB...................................................................................................... 3.6.1 Address Array ...................................................................................................... 3.6.2 Data Array............................................................................................................ 3.6.3 Usage Examples................................................................................................... Usage Notes ...................................................................................................................... 105 105 107 108 110 111 111 111 112 113 116 116 117 118 119 121 123 124 125 125 127 128 Section 4 Exception Handling ......................................................................................... 131 4.1 Overview........................................................................................................................... 4.1.1 Features................................................................................................................ 4.1.2 Register Configuration......................................................................................... Exception Handling Function ........................................................................................... 4.2.1 Exception Handling Flow .................................................................................... 4.2.2 Exception Handling Vector Addresses ................................................................ 4.2.3 Acceptance of Exceptions.................................................................................... 4.2.4 Exception Codes .................................................................................................. 4.2.5 Exception Request Masks .................................................................................... 4.2.6 Returning from Exception Handling.................................................................... Register Description.......................................................................................................... Exception Handling Operation.......................................................................................... 4.4.1 Reset..................................................................................................................... 4.4.2 Interrupts.............................................................................................................. 4.4.3 General Exceptions .............................................................................................. Individual Exception Operations....................................................................................... 131 131 131 131 131 132 134 136 137 138 138 139 139 139 140 140 4.2 4.3 4.4 4.5 Rev. 5.00 Dec 12, 2005 page xxxiv of lxxii 4.6 4.5.1 Resets ................................................................................................................... 4.5.2 General Exceptions .............................................................................................. 4.5.3 Interrupts.............................................................................................................. Usage Notes ...................................................................................................................... 140 141 146 147 Section 5 Cache.................................................................................................................... 149 5.1 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Cache Structure.................................................................................................... 5.1.3 Register Configuration......................................................................................... Register Description.......................................................................................................... 5.2.1 Cache Control Register (CCR) ............................................................................ 5.2.2 Cache Control Register 2 (CCR2)........................................................................ Cache Operation................................................................................................................ 5.3.1 Searching the Cache............................................................................................. 5.3.2 Read Access ......................................................................................................... 5.3.3 Prefetch Operations.............................................................................................. 5.3.4 Write Access ........................................................................................................ 5.3.5 Write-Back Buffer ............................................................................................... 5.3.6 Coherency of Cache and External Memory ......................................................... Memory-Mapped Cache.................................................................................................... 5.4.1 Address Array ...................................................................................................... 5.4.2 Data Array............................................................................................................ Usage Examples................................................................................................................ 5.5.1 Invalidating Specific Entries ................................................................................ 5.5.2 Reading the Data of a Specific Entry................................................................... 149 149 149 151 151 151 152 154 154 156 156 156 157 157 157 157 158 160 160 160 5.2 5.3 5.4 5.5 Section 6 X/Y Memory...................................................................................................... 161 6.1 6.2 6.3 6.4 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ X/Y Memory Access from the CPU ................................................................................. X/Y Memory Access from the DSP.................................................................................. X/Y Memory Access from the DMAC ............................................................................. 161 161 162 164 164 Section 7 Interrupt Controller (INTC)........................................................................... 165 7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Pin Configuration................................................................................................. 7.1.4 Register Configuration......................................................................................... Interrupt Sources ............................................................................................................... 165 165 166 167 167 169 7.2 Rev. 5.00 Dec 12, 2005 page xxxv of lxxii 7.3 7.4 7.5 7.2.1 NMI Interrupts ..................................................................................................... 7.2.2 IRQ Interrupt........................................................................................................ 7.2.3 IRL Interrupts....................................................................................................... 7.2.4 PINT Interrupt...................................................................................................... 7.2.5 On-Chip Supporting Module Interrupts ............................................................... 7.2.6 Interrupt Exception Handling and Priority........................................................... INTC Registers ................................................................................................................. 7.3.1 Interrupt Priority Registers A to G (IPRA to IPRG) ............................................ 7.3.2 Interrupt Control Register 0 (ICR0)..................................................................... 7.3.3 Interrupt Control Register 1 (ICR1)..................................................................... 7.3.4 Interrupt Control Register 2 (ICR2)..................................................................... 7.3.5 Interrupt Control Register 3 (ICR3)..................................................................... 7.3.6 PINT Interrupt Enable Register (PINTER).......................................................... 7.3.7 Interrupt Request Register 0 (IRR0) .................................................................... 7.3.8 Interrupt Request Register 1 (IRR1) .................................................................... 7.3.9 Interrupt Request Register 2 (IRR2) .................................................................... 7.3.10 Interrupt Request Register 3 (IRR3) .................................................................... 7.3.11 Interrupt Request Register 4 (IRR4) .................................................................... INTC Operation ................................................................................................................ 7.4.1 Interrupt Sequence ............................................................................................... 7.4.2 Multiple Interrupts ............................................................................................... Interrupt Response Time ................................................................................................... 169 169 170 172 172 173 179 179 180 181 184 185 187 187 190 191 192 195 197 197 199 199 Section 8 User Break Controller ..................................................................................... 203 8.1 Overview........................................................................................................................... 8.1.1 Features................................................................................................................ 8.1.2 Block Diagram ..................................................................................................... 8.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 8.2.1 Break Address Register A (BARA) ..................................................................... 8.2.2 Break Address Mask Register A (BAMRA)........................................................ 8.2.3 Break Bus Cycle Register A (BBRA) .................................................................. 8.2.4 Break Address Register B (BARB)...................................................................... 8.2.5 Break Address Mask Register B (BAMRB) ........................................................ 8.2.6 Break Data Register B (BDRB) ........................................................................... 8.2.7 Break Data Mask Register B (BDMRB).............................................................. 8.2.8 Break Bus Cycle Register B (BBRB) .................................................................. 8.2.9 Break Control Register (BRCR) .......................................................................... 8.2.10 Execution Times Break Register (BETR)............................................................ 8.2.11 Branch Source Register (BRSR).......................................................................... 8.2.12 Branch Destination Register (BRDR) .................................................................. 203 203 204 205 206 206 206 207 209 210 211 212 213 215 218 219 220 8.2 Rev. 5.00 Dec 12, 2005 page xxxvi of lxxii 8.3 8.2.13 Break ASID Register A (BASRA)....................................................................... 8.2.14 Break ASID Register B (BASRB) ....................................................................... Operation Description ....................................................................................................... 8.3.1 Flow of the User Break Operation ....................................................................... 8.3.2 Break on Instruction Fetch Cycle......................................................................... 8.3.3 Break by Data Access Cycle ................................................................................ 8.3.4 Break on X/Y-Memory Bus Cycle....................................................................... 8.3.5 Sequential Break .................................................................................................. 8.3.6 Value of Saved Program Counter ........................................................................ 8.3.7 PC Trace .............................................................................................................. 8.3.8 Usage Examples................................................................................................... 8.3.9 Usage Notes ......................................................................................................... 221 221 222 222 222 223 224 224 224 225 227 231 Section 9 Power-Down Modes and Software Reset.................................................. 233 9.1 Overview........................................................................................................................... 9.1.1 Power-Down Modes ............................................................................................ 9.1.2 Pin Configuration................................................................................................. 9.1.3 Register Configuration......................................................................................... Register Description.......................................................................................................... 9.2.1 Standby Control Register (STBCR)..................................................................... 9.2.2 Standby Control Register 2 (STBCR2)................................................................ 9.2.3 Standby Control Register 3 (STBCR3)................................................................ 9.2.4 Module Software Reset Register (SRSTR).......................................................... Sleep Mode ....................................................................................................................... 9.3.1 Transition to Sleep Mode..................................................................................... 9.3.2 Canceling Sleep Mode ......................................................................................... Standby Mode ................................................................................................................... 9.4.1 Transition to Standby Mode................................................................................. 9.4.2 Canceling Standby Mode ..................................................................................... 9.4.3 Clock Pause Function .......................................................................................... Module Standby Function ................................................................................................. 9.5.1 Transition to Module Standby Function............................................................... 9.5.2 Clearing the Module Standby Function ............................................................... Timing of STATUS Pin Changes...................................................................................... 9.6.1 Timing for Resets................................................................................................. 9.6.2 Timing for Canceling Standbys ........................................................................... 9.6.3 Timing for Canceling Sleep Mode....................................................................... Hardware Standby Mode .................................................................................................. 9.7.1 Transition to Hardware Standby Mode ................................................................ 9.7.2 Clearing the Hardware Standby Mode................................................................. 9.7.3 Timing of Hardware Standby Mode .................................................................... 233 233 235 235 236 236 237 239 241 243 243 243 243 243 245 246 247 247 249 249 249 250 252 254 254 254 255 9.2 9.3 9.4 9.5 9.6 9.7 Rev. 5.00 Dec 12, 2005 page xxxvii of lxxii Section 10 On-Chip Oscillation Circuits ...................................................................... 257 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.2 Overview of the CPG........................................................................................................ 10.2.1 CPG Block Diagram ............................................................................................ 10.2.2 CPG Pin Configuration ........................................................................................ 10.2.3 CPG Register Configuration ................................................................................ 10.3 Clock Operating Modes .................................................................................................... 10.4 Register Descriptions ........................................................................................................ 10.4.1 Frequency Control Register (FRQCR)................................................................. 10.4.2 CKIO2 Control Register (CKIO2CR).................................................................. 10.5 Changing the Frequency ................................................................................................... 10.5.1 Changing the Multiplication Rate ........................................................................ 10.5.2 Changing the Division Ratio................................................................................ 10.6 Overview of the WDT....................................................................................................... 10.6.1 Block Diagram of the WDT................................................................................. 10.6.2 Register Configurations ....................................................................................... 10.7 WDT Registers.................................................................................................................. 10.7.1 Watchdog Timer Counter (WTCNT)................................................................... 10.7.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 10.7.3 Notes on Register Access..................................................................................... 10.8 Using the WDT ................................................................................................................. 10.8.1 Canceling Standby Mode ..................................................................................... 10.8.2 Changing the Frequency ...................................................................................... 10.8.3 Using Watchdog Timer Mode.............................................................................. 10.8.4 Using Interval Timer Mode.................................................................................. 10.9 Notes on Board Design ..................................................................................................... 257 257 259 259 261 261 262 267 267 269 270 270 270 271 271 272 272 272 273 275 275 275 276 276 277 277 Section 11 Extend Clock Pulse Generator for USB (EXCPG) .............................. 279 11.1 Overview........................................................................................................................... 11.1.1 EXCPG ................................................................................................................ 11.2 Functions........................................................................................................................... 11.2.1 Block Diagram ..................................................................................................... 11.2.2 Pin Configuration................................................................................................. 11.2.3 Register Configuration......................................................................................... 11.3 Register Descriptions ........................................................................................................ 11.3.1 EXCPG Control Register (EXCPGCR) ............................................................... 11.4 Usage Notes ...................................................................................................................... 279 279 279 279 280 280 280 280 281 Rev. 5.00 Dec 12, 2005 page xxxviii of lxxii Section 12 Bus State Controller (BSC) ......................................................................... 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.1.5 Area Overview ..................................................................................................... 12.1.6 PC Card Support .................................................................................................. 12.2 BSC Registers ................................................................................................................... 12.2.1 Bus Control Register 1 (BCR1) ........................................................................... 12.2.2 Bus Control Register 2 (BCR2) ........................................................................... 12.2.3 Wait State Control Register 1 (WCR1)................................................................ 12.2.4 Wait State Control Register 2 (WCR2)................................................................ 12.2.5 Individual Memory Control Register (MCR)....................................................... 12.2.6 PCMCIA Control Register (PCR)........................................................................ 12.2.7 Synchronous DRAM Mode Register (SDMR) .................................................... 12.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 12.2.9 Refresh Timer Counter (RTCNT)........................................................................ 12.2.10 Refresh Time Constant Register (RTCOR) ......................................................... 12.2.11 Refresh Count Register (RFCR) .......................................................................... 12.2.12 Cautions on Accessing Refresh Control Related Registers.................................. 12.3 BSC Operation .................................................................................................................. 12.3.1 Endian/Access Size and Data Alignment............................................................. 12.3.2 Description of Areas ............................................................................................ 12.3.3 Basic Interface ..................................................................................................... 12.3.4 Synchronous DRAM Interface............................................................................. 12.3.5 Burst ROM Interface............................................................................................ 12.3.6 PCMCIA Interface ............................................................................................... 12.3.7 Waits between Access Cycles.............................................................................. 12.3.8 Bus Arbitration..................................................................................................... 12.3.9 Bus Pull-Up.......................................................................................................... 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Register Configuration......................................................................................... 13.1.3 Bus Control Register 1 (BCR1) ........................................................................... 13.1.4 Bus Control Register 2 (BCR2) ........................................................................... 13.1.5 Wait State Control Register 1 (WCR1)................................................................ 13.1.6 Wait State Control Register 2 (WCR2)................................................................ 13.1.7 Individual Memory Control Register (MCR)....................................................... 283 283 283 285 286 287 288 292 293 293 297 298 299 303 306 310 311 313 314 314 315 316 316 322 325 331 347 350 362 363 364 Section 13 Li Bus State Controller (LBSC)................................................................. 367 367 367 367 368 370 371 372 373 Rev. 5.00 Dec 12, 2005 page xxxix of lxxii 13.2 LBSC Operation................................................................................................................ 13.2.1 Bus Sharing Architecture ..................................................................................... 13.2.2 Usable System Memory ....................................................................................... 13.2.3 Bus Arbitration..................................................................................................... 13.2.4 LCDC Li Bus Access........................................................................................... 13.2.5 USBH Li Bus Access........................................................................................... 13.2.6 Setting of DMA Transfer with Bus Arbitration of Other Module........................ 376 376 376 376 376 377 377 Section 14 Direct Memory Access Controller (DMAC).......................................... 379 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram ..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3) .................................... 14.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)............................ 14.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) .................. 14.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3)............................. 14.2.5 DMA Channel Request Assign Register (CHRAR )............................................ 14.2.6 DMA Operation Register (DMAOR)................................................................... 14.3 Operation........................................................................................................................... 14.3.1 DMA Transfer Flow............................................................................................. 14.3.2 DMA Transfer Requests ...................................................................................... 14.3.3 Channel Priority ................................................................................................... 14.3.4 DMA Transfer Types ........................................................................................... 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 14.3.6 Source Address Reload Function ......................................................................... 14.3.7 DMA Transfer Ending ......................................................................................... 14.4 Compare-Match Timer (CMT) ......................................................................................... 14.4.1 Overview.............................................................................................................. 14.4.2 Register Descriptions ........................................................................................... 14.4.3 Operation ............................................................................................................. 14.4.4 Compare-Match ................................................................................................... 14.5 Examples for Use .............................................................................................................. 14.5.1 Example of DMA Transfer between A/D Converter and External Memory (Address Reload on) ............................................................................................ 14.5.2 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address on) ........................................................................................... 14.6 Usage Notes ...................................................................................................................... 379 379 381 382 382 384 384 385 386 387 394 396 398 398 400 402 405 418 427 429 431 431 432 435 436 438 438 439 441 Rev. 5.00 Dec 12, 2005 page xl of lxxii Section 15 Timer (TMU)................................................................................................... 443 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram ..................................................................................................... 15.1.3 Register Configuration......................................................................................... 15.2 TMU Registers.................................................................................................................. 15.2.1 Timer Start Register (TSTR)................................................................................ 15.2.2 Timer Control Register (TCR) ............................................................................. 15.2.3 Timer Constant Register (TCOR) ........................................................................ 15.2.4 Timer Counters (TCNT) ...................................................................................... 15.3 TMU Operation................................................................................................................. 15.3.1 Overview.............................................................................................................. 15.3.2 Basic Functions.................................................................................................... 15.4 Interrupts ........................................................................................................................... 15.4.1 Status Flag Set Timing......................................................................................... 15.4.2 Status Flag Clear Timing ..................................................................................... 15.4.3 Interrupt Sources and Priorities............................................................................ 15.5 Usage Notes ...................................................................................................................... 15.5.1 Writing to Registers ............................................................................................. 15.5.2 Reading Registers ................................................................................................ 443 443 444 445 446 446 447 448 449 451 451 451 453 453 454 454 455 455 455 Section 16 Realtime Clock (RTC).................................................................................. 457 16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram ..................................................................................................... 16.1.3 Pin Configuration................................................................................................. 16.1.4 RTC Register Configuration ................................................................................ 16.2 Register Descriptions ........................................................................................................ 16.2.1 64-Hz Counter (R64CNT) ................................................................................... 16.2.2 Second Counter (RSECCNT) .............................................................................. 16.2.3 Minute Counter (RMINCNT) .............................................................................. 16.2.4 Hour Counter (RHRCNT).................................................................................... 16.2.5 Day of the Week Counter (RWKCNT)................................................................ 16.2.6 Date Counter (RDAYCNT) ................................................................................. 16.2.7 Month Counter (RMONCNT) ............................................................................. 16.2.8 Year Counter (RYRCNT) .................................................................................... 16.2.9 Second Alarm Register (RSECAR) ..................................................................... 16.2.10 Minute Alarm Register (RMINAR) ..................................................................... 16.2.11 Hour Alarm Register (RHRAR)........................................................................... 16.2.12 Day of the Week Alarm Register (RWKAR)....................................................... 16.2.13 Date Alarm Register (RDAYAR) ........................................................................ 457 457 458 459 460 461 461 461 462 462 463 464 464 465 465 466 466 467 467 Rev. 5.00 Dec 12, 2005 page xli of lxxii 16.2.14 Month Alarm Register (RMONAR) .................................................................... 16.2.15 RTC Control Register 1 (RCR1).......................................................................... 16.2.16 RTC Control Register 2 (RCR2).......................................................................... 16.3 RTC Operation.................................................................................................................. 16.3.1 Initial Settings of Registers after Power-On ........................................................ 16.3.2 Setting the Time................................................................................................... 16.3.3 Reading the Time................................................................................................. 16.3.4 Alarm Function .................................................................................................... 16.3.5 Crystal Oscillator Circuit ..................................................................................... 16.4 Usage Notes ...................................................................................................................... 16.4.1 Writing Registers During RTC Count Operation................................................. 16.4.2 RTC Periodic Interrupts ....................................................................................... 16.4.3 Using the ADJ Bit in the Real Time Clock (RTC) .............................................. 468 469 470 473 473 473 475 476 477 478 478 478 479 Section 17 Serial Communication Interface (SCI) .................................................... 481 17.1 Overview........................................................................................................................... 17.1.1 Features................................................................................................................ 17.1.2 Block Diagram ..................................................................................................... 17.1.3 Pin Configuration................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.2 Register Descriptions ........................................................................................................ 17.2.1 Receive Shift Register (SCRSR).......................................................................... 17.2.2 Receive Data Register (SCRDR) ......................................................................... 17.2.3 Transmit Shift Register (SCTSR) ........................................................................ 17.2.4 Transmit Data Register (SCTDR)........................................................................ 17.2.5 Serial Mode Register (SCSMR)........................................................................... 17.2.6 Serial Control Register (SCSCR)......................................................................... 17.2.7 Serial Status Register (SCSSR)............................................................................ 17.2.8 Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR) ................. 17.2.9 Bit Rate Register (SCBRR).................................................................................. 17.3 Operation........................................................................................................................... 17.3.1 Overview.............................................................................................................. 17.3.2 Operation in Asynchronous Mode ....................................................................... 17.3.3 Multiprocessor Communication........................................................................... 17.3.4 Clock Synchronous Operation ............................................................................. 17.4 SCI Interrupt Sources........................................................................................................ 17.5 Usage Notes ...................................................................................................................... 481 481 482 485 486 487 487 487 488 488 489 491 495 499 500 509 509 511 521 529 538 539 Section 18 Smart Card Interface ..................................................................................... 543 18.1 Overview........................................................................................................................... 543 18.1.1 Features................................................................................................................ 543 Rev. 5.00 Dec 12, 2005 page xlii of lxxii 18.1.2 Block Diagram ..................................................................................................... 18.1.3 Pin Configuration................................................................................................. 18.1.4 Register Configuration......................................................................................... 18.2 Register Descriptions ........................................................................................................ 18.2.1 Smart Card Mode Register (SCSCMR) ............................................................... 18.2.2 Serial Status Register (SCSSR)............................................................................ 18.3 Operation........................................................................................................................... 18.3.1 Overview.............................................................................................................. 18.3.2 Pin Connections ................................................................................................... 18.3.3 Data Format ......................................................................................................... 18.3.4 Register Settings .................................................................................................. 18.3.5 Clock.................................................................................................................... 18.3.6 Data Transmission and Reception........................................................................ 18.4 Usage Notes ...................................................................................................................... 18.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode .................... 18.4.2 Retransmission (Receive and Transmit Modes)................................................... 544 545 545 546 546 547 548 548 549 549 551 552 555 561 561 563 Section 19 Serial Communication Interface with FIFO (SCIF)............................. 565 19.1 Overview........................................................................................................................... 19.1.1 Features................................................................................................................ 19.1.2 Block Diagram ..................................................................................................... 19.1.3 Pin Configuration................................................................................................. 19.1.4 Register Configuration......................................................................................... 19.2 Register Descriptions ........................................................................................................ 19.2.1 Receive Shift Register 2 (SCRSR2)..................................................................... 19.2.2 Receive FIFO Data Register 2 (SCFRDR2) ........................................................ 19.2.3 Transmit Shift Register 2 (SCTSR2) ................................................................... 19.2.4 Transmit FIFO Data Register 2 (SCFTDR2) ....................................................... 19.2.5 Serial Mode Register 2 (SCSMR2)...................................................................... 19.2.6 Serial Control Register 2 (SCSCR2).................................................................... 19.2.7 Serial Status Register 2 (SCSSR2)....................................................................... 19.2.8 Bit Rate Register 2 (SCBRR2)............................................................................. 19.2.9 FIFO Control Register 2 (SCFCR2) .................................................................... 19.2.10 FIFO Data Count Set Register 2 (SCFDR2) ........................................................ 19.3 Operation........................................................................................................................... 19.3.1 Overview.............................................................................................................. 19.3.2 Serial Operation ................................................................................................... 19.4 SCIF Interrupts.................................................................................................................. 19.5 Usage Notes ...................................................................................................................... 565 565 566 568 569 570 570 570 571 571 572 574 576 580 586 588 589 589 590 600 601 Rev. 5.00 Dec 12, 2005 page xliii of lxxii Section 20 Serial IO (SIOF) ............................................................................................. 20.1 Overview........................................................................................................................... 20.1.1 Features................................................................................................................ 20.1.2 Block Diagram ..................................................................................................... 20.1.3 Terminal............................................................................................................... 20.1.4 Register Configuration......................................................................................... 20.2 Register Description.......................................................................................................... 20.2.1 Mode Register (SIMDR)...................................................................................... 20.2.2 Clock Select Register (SISCR) ............................................................................ 20.2.3 Transmit Data Assign Register (SITDAR) .......................................................... 20.2.4 Receive Data Assign Register (SIRDAR)............................................................ 20.2.5 Control Command Assign Register (SICDAR) ................................................... 20.2.6 Serial Control Register (SICTR).......................................................................... 20.2.7 FIFO Control Register (SIFCTR) ........................................................................ 20.2.8 Status Register (SISTR) ....................................................................................... 20.2.9 Interrupt Enable Register (SIIER)........................................................................ 20.2.10 Transmit Data Register (SITDR) ......................................................................... 20.2.11 Receive Data Register (SIRDR)........................................................................... 20.2.12 Transmit Control Data Register (SITCR) ............................................................ 20.2.13 Receive Control Data Register (SIRCR).............................................................. 20.3 Operation........................................................................................................................... 20.3.1 Serial Clock.......................................................................................................... 20.3.2 Serial Timing ....................................................................................................... 20.3.3 Transmit Data Format .......................................................................................... 20.3.4 Register Assignment for Transfer Data................................................................ 20.3.5 Control Data Interface.......................................................................................... 20.3.6 FIFO..................................................................................................................... 20.3.7 Procedures for Transmit or Receive..................................................................... 20.3.8 Interrupt ............................................................................................................... 20.3.9 Transmit or Receive Timing ................................................................................ 20.4 Usage Notes ...................................................................................................................... 20.4.1 Notes on Using the SIOF with Versions Previous to the SH7727B..................... 21.1 Overview........................................................................................................................... 21.1.1 Features................................................................................................................ 21.1.2 Block Diagram ..................................................................................................... 21.1.3 Pin Configuration................................................................................................. 21.1.4 Register Configuration......................................................................................... 21.2 Register Description.......................................................................................................... Rev. 5.00 Dec 12, 2005 page xliv of lxxii 605 605 605 606 607 607 608 608 610 612 613 614 616 618 620 624 626 627 628 629 630 630 631 632 634 637 639 641 646 648 652 654 Section 21 Analog Front End Interface (AFEIF) ....................................................... 657 657 657 658 659 659 660 21.2.1 AFEIF Control Register 1 and 2 (ACTR1, ACTR2) ........................................... 21.2.2 Make Ratio Count Register (MRCR)................................................................... 21.2.3 Minimum Pause Count Register (MPCR)............................................................ 21.2.4 AFEIF Status Register 1 and 2 (ASTR1, ASTR2)............................................... 21.2.5 Dial Pulse Number Queue (DPNQ) ..................................................................... 21.2.6 Ringing Pulse Counter (RCNT) ........................................................................... 21.2.7 AFE Control Data Register (ACDR) ................................................................... 21.2.8 AFE Status Data Register (ASDR) ...................................................................... 21.2.9 Transmit Data FIFO Port (TDFP) ........................................................................ 21.2.10 Receive Data FIFO Port (RDFP) ......................................................................... 21.3 Operation........................................................................................................................... 21.3.1 Interrupt Timing................................................................................................... 21.3.2 AFE Interface....................................................................................................... 21.3.3 DAA Interface...................................................................................................... 21.3.4 Wake up Ringing Interrupt .................................................................................. 660 663 663 664 669 670 670 670 671 671 671 671 673 675 677 Section 22 USB Pin Multiplex Controller.................................................................... 679 22.1 Feature............................................................................................................................... 22.1.1 Block Diagram ..................................................................................................... 22.1.2 Pin Configuration................................................................................................. 22.1.3 Register Configuration......................................................................................... 22.2 Register Description.......................................................................................................... 22.2.1 Extra Pin Function Controller (EXPFC) .............................................................. 22.3 Examples of External Circuit ............................................................................................ 22.3.1 Example of the Connection between USB Function Controller and Transceiver 22.3.2 Example of the Connection between USB Host Controller and Transceiver....... 22.3.3 Usage Notes ......................................................................................................... 679 680 681 682 683 683 684 684 689 690 Section 23 USB Function Controller ............................................................................. 691 23.1 23.2 23.3 23.4 23.5 Features ............................................................................................................................. Block Diagram .................................................................................................................. Pin Configuration.............................................................................................................. Register Configuration ...................................................................................................... Register Descriptions ........................................................................................................ 23.5.1 USBEP0i Data Register (USBEPDR0I) .............................................................. 23.5.2 USBEP0o Data Register (USBEPDR0O) ............................................................ 23.5.3 USBEP0s Data Register (USBEPDR0S) ............................................................. 23.5.4 USBEP1 Data Register (USBEPDR1)................................................................. 23.5.5 USBEP2 Data Register (USBEPDR2)................................................................. 23.5.6 USBEP3 Data Register (USBEPDR3)................................................................. 23.5.7 USB Interrupt Flag Register 0 (USBIFR0) .......................................................... 691 692 692 693 694 694 694 694 695 695 695 695 Rev. 5.00 Dec 12, 2005 page xlv of lxxii 23.6 23.7 23.8 23.9 23.5.8 USB Interrupt Flag Register 1 (USBIFR1) .......................................................... 23.5.9 USB Trigger Register (USBTRG) ....................................................................... 23.5.10 USBFIFO Clear Register (USBFCLR) ................................................................ 23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) ....................................... 23.5.12 USB Data Status Register (USBDASTS) ............................................................ 23.5.13 USB Endpoint Stall Register (USBEPSTL) ........................................................ 23.5.14 USB Interrupt Enable Register 0 (USBIER0)...................................................... 23.5.15 USB Interrupt Enable Register 1 (USBIER1)...................................................... 23.5.16 USBEP1 Receive Data Size Register (USBEPSZ1) ............................................ 23.5.17 USB Interrupt Select Register 0 (USBISR0) ....................................................... 23.5.18 USB Interrupt Select Register 1 (USBISR1) ....................................................... 23.5.19 USBDMA Setting Register (USBDMAR)........................................................... Operation........................................................................................................................... 23.6.1 Cable Connection................................................................................................. 23.6.2 Cable Disconnection ............................................................................................ 23.6.3 Control Transfer................................................................................................... 23.6.4 EP1 Bulk-Out Transfer (Dual FIFOs).................................................................. 23.6.5 EP2 Bulk-In Transfer (Dual FIFOs) .................................................................... 23.6.6 EP3 Interrupt-In Transfer..................................................................................... Processing of USB Standard Commands and Class/Vendor Commands.......................... 23.7.1 Processing of Commands Transmitted by Control Transfer ................................ Stall Operations................................................................................................................. 23.8.1 Overview.............................................................................................................. 23.8.2 Forcible Stall by Application ............................................................................... 23.8.3 Automatic Stall by USB Function Module .......................................................... Usage Notes ...................................................................................................................... 23.9.1 Receiving Setup Data........................................................................................... 23.9.2 Clearing the FIFO ................................................................................................ 23.9.3 Overreading and Overwriting the Data Registers ................................................ 23.9.4 Assigning Interrupt Sources to EP0 ..................................................................... 23.9.5 Clearing the FIFO when DMA Transfer Is Enabled ............................................ 23.9.6 Notes on TR Interrupt .......................................................................................... 23.9.7 Peripheral Clock (P) Operation Frequency ........................................................ 697 698 699 699 700 700 701 701 701 702 702 703 704 704 705 706 713 714 716 717 717 718 718 718 720 722 722 722 722 723 723 723 724 Section 24 USB HOST Module ...................................................................................... 725 24.1 General Description .......................................................................................................... 24.1.1 Features................................................................................................................ 24.1.2 Pin Configuration................................................................................................. 24.1.3 Register Configuration......................................................................................... 24.2 Register Description.......................................................................................................... 24.2.1 HcRevision........................................................................................................... Rev. 5.00 Dec 12, 2005 page xlvi of lxxii 725 725 726 727 728 728 24.3 24.4 24.5 24.6 24.7 24.2.2 HcControl............................................................................................................. 24.2.3 HcCommandStatus .............................................................................................. 24.2.4 HcInterruptStatus ................................................................................................. 24.2.5 HcInterruptEnable................................................................................................ 24.2.6 HcInterruptDisable............................................................................................... 24.2.7 HcHCCA.............................................................................................................. 24.2.8 HcPeriodCurrentED............................................................................................. 24.2.9 HcControlHeadED............................................................................................... 24.2.10 HcControlCurrentED ........................................................................................... 24.2.11 HcBulkHeadED ................................................................................................... 24.2.12 HcBulkCurrentED................................................................................................ 24.2.13 HcDoneHead........................................................................................................ 24.2.14 HcFmInterval ....................................................................................................... 24.2.15 HcFmRemaining .................................................................................................. 24.2.16 HcFmNumber ...................................................................................................... 24.2.17 HcPeriodicStart.................................................................................................... 24.2.18 HcLSThreshold .................................................................................................... 24.2.19 HcRhDescriptorA ................................................................................................ 24.2.20 HcRhDescriptorB................................................................................................. 24.2.21 HcRhStatus .......................................................................................................... 24.2.22 HcRhPortStatus[1:2] ............................................................................................ Data Storage Format which Required by USB Host Controller........................................ 24.3.1 Storage Format of the Transferred Data............................................................... 24.3.2 Storage Format of the Descriptor......................................................................... Data Alignment Restriction of USB Host Controller........................................................ 24.4.1 Restriction on the Line Boundary of the Synchronous DRAM ........................... 24.4.2 Restriction on the Memory Access Address ........................................................ Restrictions on the Data Transfer of USB Controller ....................................................... 24.5.1 Restriction of the Data Size in IN Transfer.......................................................... 24.5.2 Restrictions on the Hub Connection on NAK/STALL Reception ....................... 24.5.3 Restrictions when a Low-Speed Device is Disconnected .................................... Restrictions on the Software Reset and USB Reset .......................................................... Notes on Using USB Host with Versions Previous to the SH7727C................................ 729 732 735 737 739 740 740 741 741 741 742 742 743 744 745 746 746 747 749 750 751 757 757 758 758 758 759 759 759 759 760 760 760 Section 25 LCD Controller ............................................................................................... 763 25.1 Overview........................................................................................................................... 25.1.1 Features................................................................................................................ 25.1.2 Block Diagram ..................................................................................................... 25.1.3 Pin Configuration................................................................................................. 25.1.4 Register Configuration......................................................................................... 25.2 Register Descriptions ........................................................................................................ 763 763 764 765 765 767 Rev. 5.00 Dec 12, 2005 page xlvii of lxxii 25.2.1 LCDC Input Clock Register (LDICKR) .............................................................. 25.2.2 LCDC Module Type Register (LDMTR) ............................................................ 25.2.3 LCDC Data Format Register (LDDFR) ............................................................... 25.2.4 LCDC Scan Mode Register (LDSMR) ................................................................ 25.2.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) .......... 25.2.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) .......... 25.2.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) .......... 25.2.8 LCDC Palette Control Register (LDPALCR) ...................................................... 25.2.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ...................................... 25.2.10 LCDC Horizontal Character Number Register (LDHCNR) ................................ 25.2.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ........................................ 25.2.12 LCDC Vertical Display Line Number Register (LDVDLNR)............................. 25.2.13 LCDC Vertical Total Line Number Register (LDVTLNR) ................................. 25.2.14 LCDC Vertical Sync Signal Register (LDVSYNR) ............................................ 25.2.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ...... 25.2.16 LCDC Interrupt Control Register (LDINTR) ...................................................... 25.2.17 LCDC Power Management Mode Register (LDPMMR)..................................... 25.2.18 LCDC Power-Supply Sequence Period Register (LDPSPR) ............................... 25.2.19 LCDC Control Register (LDCNTR).................................................................... 25.3 Operation........................................................................................................................... 25.3.1 LCD Module Sizes which can be Displayed in this LCDC ................................. 25.3.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (SDRAM) .............................................................................................. 25.3.3 Color Palette Specification................................................................................... 25.3.4 Data Format ......................................................................................................... 25.3.5 Timing Controller Register .................................................................................. 25.3.6 Power Management Registers.............................................................................. 25.3.7 Operation for Hardware Rotation......................................................................... 25.4 Clock and LCD Data Signal Examples ............................................................................. 25.5 Usage Notes ...................................................................................................................... 767 768 771 773 774 775 776 777 778 779 780 781 782 783 784 784 786 788 789 790 790 791 797 799 802 802 807 809 820 Section 26 Pin Function Controller (PFC) ................................................................... 821 26.1 Overview........................................................................................................................... 821 26.2 Register Configuration ...................................................................................................... 826 26.3 Register Descriptions ........................................................................................................ 827 26.3.1 Port A Control Register (PACR).......................................................................... 827 26.3.2 Port B Control Register (PBCR) .......................................................................... 828 26.3.3 Port C Control Register (PCCR) .......................................................................... 829 26.3.4 Port D Control Register (PDCR).......................................................................... 830 26.3.5 Port E Control Register (PECR) .......................................................................... 831 26.3.6 Port F Control Register (PFCR)........................................................................... 832 Rev. 5.00 Dec 12, 2005 page xlviii of lxxii 26.3.7 Port G Control Register (PGCR).......................................................................... 26.3.8 Port H Control Register (PHCR).......................................................................... 26.3.9 Port J Control Register (PJCR) ............................................................................ 26.3.10 Port K Control Register (PKCR).......................................................................... 26.3.11 Port L Control Register (PLCR) .......................................................................... 26.3.12 Port M Control Register (PMCR) ........................................................................ 26.3.13 SC Port Control Register (SCPCR)...................................................................... 833 835 836 837 838 839 840 Section 27 I/O Ports ............................................................................................................ 845 27.1 Overview........................................................................................................................... 845 27.2 Register Configuration ...................................................................................................... 846 27.3 Ports A to C, E, J, K.......................................................................................................... 847 27.3.1 Ports A to C, E, J, K Data Rgister (PADR, PBDR, PCDR, PEDR, PJDR, PKDR) ................................................... 847 27.4 Port D................................................................................................................................ 848 27.4.1 Port D Data Register (PDDR) .............................................................................. 848 27.5 Ports F, M ......................................................................................................................... 850 27.5.1 Ports F, M Data Register (PFDR, PMDR) ........................................................... 850 27.6 Port G................................................................................................................................ 851 27.6.1 Port G Data Register (PGDR) .............................................................................. 851 27.7 Port H................................................................................................................................ 852 27.7.1 Port H Data Register (PHDR) .............................................................................. 852 27.8 Port L ................................................................................................................................ 854 27.8.1 Port L Data Register (PLDR)............................................................................... 854 27.9 SC Port.............................................................................................................................. 855 27.9.1 Port SC Data Register (SCPDR) .......................................................................... 855 Section 28 A/D Converter................................................................................................. 857 28.1 Overview........................................................................................................................... 28.1.1 Features................................................................................................................ 28.1.2 Block Diagram ..................................................................................................... 28.1.3 Input Pins ............................................................................................................. 28.1.4 Register Configuration......................................................................................... 28.2 Register Descriptions ........................................................................................................ 28.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 28.2.2 A/D Control/Status Register (ADCSR) ............................................................... 28.2.3 A/D Control Register (ADCR) ............................................................................ 28.3 Bus Master Interface ......................................................................................................... 28.4 Operation........................................................................................................................... 28.4.1 Single Mode (MULTI = 0) .................................................................................. 28.4.2 Multi Mode (MULTI = 1, SCN = 0).................................................................... 857 857 858 859 860 861 861 862 864 865 867 867 869 Rev. 5.00 Dec 12, 2005 page xlix of lxxii 28.4.3 Scan Mode (MULTI = 1, SCN = 1) ..................................................................... 28.4.4 Input Sampling and A/D Conversion Time.......................................................... 28.4.5 External Trigger Input Timing ............................................................................. 28.5 Interrupts ........................................................................................................................... 28.6 Definitions of A/D Conversion Accuracy ......................................................................... 28.7 Usage Notes ...................................................................................................................... 28.7.1 Setting Analog Input Voltage .............................................................................. 28.7.2 Processing of Analog Input Pins .......................................................................... 28.7.3 Access Size and Read Data.................................................................................. 871 873 874 875 875 876 876 876 877 Section 29 D/A Converter................................................................................................. 879 29.1 Overview........................................................................................................................... 29.1.1 Features................................................................................................................ 29.1.2 Block Diagram ..................................................................................................... 29.1.3 I/O Pins ................................................................................................................ 29.1.4 Register Configuration......................................................................................... 29.2 Register Descriptions ........................................................................................................ 29.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 29.2.2 D/A Control Register (DACR) ............................................................................ 29.3 Operation........................................................................................................................... 879 879 879 880 880 881 881 881 883 Section 30 PC Card Controller (PCC)........................................................................... 885 30.1 Overview........................................................................................................................... 30.1.1 Features................................................................................................................ 30.1.2 Block Diagram ..................................................................................................... 30.1.3 Register Configuration......................................................................................... 30.1.4 PCMCIA Support................................................................................................. 30.2 Register Descriptions ........................................................................................................ 30.2.1 Area 6 Interface Status Register (PCC0ISR) ....................................................... 30.2.2 Area 6 General Control Register (PCC0GCR) .................................................... 30.2.3 Area 6 Card Status Change Register (PCC0CSCR)............................................. 30.2.4 Area 6 Card Status Change Interrupt Enable Register (PCC0CSCIER) .............. 30.3 Operation........................................................................................................................... 30.3.1 PC card Connection Specification (Interface Diagram, Pin Correspondence)..... 30.3.2 PC Card Interface Timing .................................................................................... 30.3.3 Usage Notes ......................................................................................................... 885 885 886 887 888 891 891 894 896 900 903 903 907 912 Section 31 User-Debugging Interface (H-UDI).......................................................... 915 31.1 Overview........................................................................................................................... 915 31.2 User Debugging Interface (H-UDI) .................................................................................. 915 31.2.1 Pin Description..................................................................................................... 915 Rev. 5.00 Dec 12, 2005 page l of lxxii 31.2.2 Block Diagram ..................................................................................................... 31.3 Register Descriptions ........................................................................................................ 31.3.1 Bypass Register (SDBPR) ................................................................................... 31.3.2 Instruction Register (SDIR) ................................................................................. 31.3.3 Boundary-Scan Register (SDBSR) ...................................................................... 31.4 H-UDI Operations............................................................................................................. 31.4.1 TAP Controller .................................................................................................... 31.4.2 Reset Configuration ............................................................................................. 31.4.3 H-UDI Reset ........................................................................................................ 31.4.4 H-UDI Interrupt ................................................................................................... 31.4.5 Bypass.................................................................................................................. 31.4.6 Using H-UDI to Recover from Sleep Mode........................................................ 31.5 Usage Notes ...................................................................................................................... 31.6 Advanced User Debugger (AUD) ..................................................................................... 916 916 917 917 918 925 925 926 927 927 927 927 928 928 Section 32 Electrical Characteristics.............................................................................. 929 32.1 Absolute Maximum Ratings ............................................................................................. 32.2 DC Characteristics ............................................................................................................ 32.3 AC Characteristics ............................................................................................................ 32.3.1 Clock Timing ....................................................................................................... 32.3.2 Control Signal Timing ......................................................................................... 32.3.3 AC Bus Timing .................................................................................................... 32.3.4 Basic Timing........................................................................................................ 32.3.5 Burst ROM Timing .............................................................................................. 32.3.6 Synchronous DRAM Timing ............................................................................... 32.3.7 PCMCIA Timing ................................................................................................. 32.3.8 Peripheral Module Signal Timing........................................................................ 32.3.9 H-UDI-Related Pin Timing.................................................................................. 32.3.10 LCDC Timing ...................................................................................................... 32.3.11 SIOF Module Signal Timing................................................................................ 32.3.12 USB Module Signal Timing ................................................................................ 32.3.13 AFEIF Module Signal Timing ............................................................................. 32.3.14 AC Characteristics Measurement Conditions ...................................................... 32.3.15 Delay Time Variation Due to Load Capacitance ................................................. 32.4 A/D Converter Characteristics .......................................................................................... 32.5 D/A Converter Characteristics .......................................................................................... 929 931 934 937 946 949 951 954 957 968 975 978 980 982 985 987 989 990 991 991 Appendix A Pin Functions................................................................................................ 993 A.1 A.2 A.3 Pin Functions .................................................................................................................... 993 Treatment of Unused Pins................................................................................................. 999 Pin Status when Accessing Address Spaces.................................................................... 1004 Rev. 5.00 Dec 12, 2005 page li of lxxii Appendix B Control Registers....................................................................................... 1018 B.1 Register Address Map ..................................................................................................... 1018 Appendix C Product Lineup........................................................................................... 1028 Appendix D Package Dimensions ................................................................................ 1029 Appendix E Using Versions Previous to the SH7727C ......................................... 1031 E.1 Determining the Version Number Based on the Markings on the Chip.......................... 1031 Appendix F Using Port G Control Register (PGCR) with Versions Previous to the SH7727B.......................................................................................... 1032 Rev. 5.00 Dec 12, 2005 page lii of lxxii Figures Section 1 Overview and Pin Functions Figure 1.1 Block Diagram ....................................................................................................... 8 Figure 1.2 Pin Arrangement (PRQP0240KC-B) ..................................................................... 9 Figure 1.3 Pin Arrangement (PLBG0240JA-A) ...................................................................... 10 Section 2 CPU Figure 2.1 Register Configuration in Each Processing Mode (1) ............................................ Figure 2.2 Register Configuration in Each Processing Mode (2) ............................................ Figure 2.3 General Purpose Register (Not in DSP Mode) ....................................................... Figure 2.4 General Purpose Register (DSP Mode) .................................................................. Figure 2.5 Control Registers (1) .............................................................................................. Figure 2.5 Control Registers (2) .............................................................................................. Figure 2.6 System Registers .................................................................................................... Figure 2.7 DSP Registers......................................................................................................... Figure 2.8 Connections of DSP Registers and Buses .............................................................. Figure 2.9 Longword Operand ................................................................................................ Figure 2.10 Data Format............................................................................................................ Figure 2.11 Byte, Word, and Longword Alignment .................................................................. Figure 2.12 X and Y Data Transfer Addressing ........................................................................ Figure 2.13 Single Data Transfer Addressing............................................................................ Figure 2.14 Modulo Addressing ................................................................................................ Figure 2.15 DSP Instruction Formats ........................................................................................ Figure 2.16 Sample Parallel Instruction Program...................................................................... Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions .................... Section 3 Memory Management Unit (MMU) Figure 3.1 MMU Functions ..................................................................................................... Figure 3.2 Logical Address Space Mapping............................................................................ Figure 3.3 MMU Register Contents ........................................................................................ Figure 3.4 Overall Configuration of the TLB .......................................................................... Figure 3.5 Logical Address and TLB Structure....................................................................... Figure 3.6 TLB Indexing (IX = 1) ........................................................................................... Figure 3.7 TLB Indexing (IX = 0) ........................................................................................... Figure 3.8 Objects of Address Comparison............................................................................. Figure 3.9 Operation of LDTLB Instruction............................................................................ Figure 3.10 Synonym Problem .................................................................................................. Figure 3.11 MMU Exception Generation Flowchart ................................................................. Figure 3.12 MMU Exception Signals in Instruction Fetch ........................................................ 23 24 25 26 29 30 31 35 37 38 39 40 49 50 52 58 87 95 99 101 104 105 106 107 108 109 113 115 120 121 Rev. 5.00 Dec 12, 2005 page liii of lxxii Figure 3.13 MMU Exception Signals in Data Access ............................................................... 122 Figure 3.14 MMU Exception in Repeat Loop ........................................................................... 123 Figure 3.15 Specifying Address and Data for Memory-Mapped TLB Access .......................... 126 Section 4 Exception Handling Figure 4.1 Vector Table........................................................................................................... 132 Figure 4.2 Example of Acceptance Order of General Exceptions ........................................... 135 Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers........... 139 Section 5 Cache Figure 5.1 Cache Structure ...................................................................................................... Figure 5.2 CCR Register Configuration .................................................................................. Figure 5.3 CCR2 Register Configuration ................................................................................ Figure 5.4 Cache Search Scheme ............................................................................................ Figure 5.5 Write-Back Buffer Configuration........................................................................... Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access........................ 150 152 153 155 157 159 Section 6 X/Y Memory Figure 6.1 X/Y Memory Logical Address Mapping................................................................ 163 Figure 6.2 X/Y Memory Physical Address Mapping .............................................................. 164 Section 7 Interrupt Controller (INTC) Figure 7.1 INTC Block Diagram ............................................................................................. Figure 7.2 Example of IRL Interrupt Connection.................................................................... Figure 7.3 Interrupt Operation Flowchart................................................................................ Figure 7.4 Example of Pipeline Operations when IRL Interrupt is Accepted ......................... 166 171 198 202 Section 8 User Break Controller Figure 8.1 Block Diagram of User Break Controller............................................................... 204 Section 9 Power-Down Modes and Software Reset Figure 9.1 Canceling Standby Mode with STBCR.STBY....................................................... Figure 9.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ........................... Figure 9.3 Manual Reset STATUS Output.............................................................................. Figure 9.4 Standby to Interrupt STATUS Output.................................................................... Figure 9.5 Standby to Power-On Reset STATUS Output........................................................ Figure 9.6 Standby to Manual Reset STATUS Output............................................................ Figure 9.7 Sleep to Interrupt STATUS Output ........................................................................ Figure 9.8 Sleep to Power-On Reset STATUS Output............................................................ Figure 9.9 Sleep to Manual Reset STATUS Output................................................................ Figure 9.10 Hardware Standby Mode Timing (CA = Low in Normal Operation) .................... Rev. 5.00 Dec 12, 2005 page liv of lxxii 246 249 250 250 251 251 252 252 253 255 Figure 9.11 Hardware Standby Mode Timing (CA = Low during WDT Operation while Standby Mode is Cleared) ............................................................................ 256 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 On-Chip Oscillation Circuits Block Diagram of Clock Pulse Generator .............................................................. Block Diagram of the WDT ................................................................................... Writing to WTCNT and WTCSR........................................................................... Points for Attention when Using Crystal Resonator............................................... Points for Attention when Using PLL Oscillator Circuit ....................................... 259 271 275 277 278 Section 11 Extend Clock Pulse Generator for USB (EXCPG) Figure 11.1 Block Diagram of EXCPG ..................................................................................... 279 Section 12 Bus State Controller (BSC) Figure 12.1 Corresponding to Logical Address Space and Physical Address Space................. Figure 12.2 Corresponding to Logical Address Space and Physical Address Space................. Figure 12.3 Physical Space Allocation ...................................................................................... Figure 12.4 Writing to RFCR, RTCSR, RTCNT, and RTCOR................................................. Figure 12.5 Basic Timing of Basic Interface ............................................................................. Figure 12.6 Example of 32-Bit Data-Width Static RAM Connection ....................................... Figure 12.7 Example of 16-Bit Data-Width Static RAM Connection ....................................... Figure 12.8 Example of 8-Bit Data-Width Static RAM Connection ......................................... Figure 12.9 Basic Interface Wait Timing (Software Wait Only)............................................... Figure 12.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1)....................................................................................................... Figure 12.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width).......... Figure 12.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)............................. Figure 12.13 Basic Timing for Synchronous DRAM Burst Read ............................................... Figure 12.14 Synchronous DRAM Burst Read Wait Specification Timing ................................ Figure 12.15 Basic Timing for Synchronous DRAM Single Read.............................................. Figure 12.16 Basic Timing for Synchronous DRAM Burst Write .............................................. Figure 12.17 Basic Timing for Synchronous DRAM Single Write............................................. Figure 12.18 Auto-Refresh Operation ......................................................................................... Figure 12.19 Synchronous DRAM Auto-Refresh Timing........................................................... Figure 12.20 Synchronous DRAM Self-Refresh Timing ............................................................ Figure 12.21 Synchronous DRAM Mode Write Timing ............................................................. Figure 12.22 Burst ROM Wait Access Timing ........................................................................... Figure 12.23 Burst ROM Basic Access Timing .......................................................................... Figure 12.24 Example of PCMCIA Interface (If Internal PC Card Controller is not used.)........ Figure 12.25 Basic Timing for PCMCIA Memory Card Interface .............................................. Figure 12.26 Wait Timing for PCMCIA Memory Card Interface ............................................... 285 289 291 315 326 327 328 328 329 330 332 333 336 337 338 339 341 342 343 344 346 348 349 351 353 354 Rev. 5.00 Dec 12, 2005 page lv of lxxii Figure 12.27 Basic Timing for PCMCIA Memory Card Interface Burst Access ........................ Figure 12.28 Wait Timing for PCMCIA Memory Card Interface Burst Access ......................... Figure 12.29 PCMCIA Space Assignment .................................................................................. Figure 12.30 Basic Timing for PCMCIA I/O Card Interface ...................................................... Figure 12.31 Wait Timing for PCMCIA I/O Card Interface ....................................................... Figure 12.32 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. Figure 12.33 Waits between Access Cycles ................................................................................ Figure 12.34 Pins A25 to A0 Pull-Up Timing............................................................................. Figure 12.35 Pins D31 to D0 Pull-Up Timing (Read Cycle)....................................................... Figure 12.36 Pins D31 to D0 Pull-Up Timing (Write Cycle) ...................................................... 355 356 357 359 360 361 363 364 364 365 Section 13 Li Bus State Controller (LBSC) Figure 13.1 Block Diagram of Li Bus Architecture................................................................... 377 Direct Memory Access Controller (DMAC) DMAC Block Diagram .......................................................................................... DMAC Transfer Flowchart .................................................................................... Operation in Round-Robin Mode........................................................................... Channel Priority Order in Round-Robin Mode ...................................................... Operation in Direct Address Mode......................................................................... Example of DMA Transfer Timing in the Direct Address Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)... Figure 14.7 Example of DMA Transfer Timing in the Direct Address Mode (16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) ................................................................................................. Figure 14.8 Example of DMA Transfer Timing in the Direct Address Mode (16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary Memory) ................................................................................................. Figure 14.9 Operation in Indirect Address Mode (When the External Memory Space is Set to 16-bit Width) ............................................................................................ Figure 14.10 Example of Transfer Timing in Indirect Address Mode (Transfer between External Memories, External Memory with 16-bit Width) ...... Figure 14.11 Data Flow in Single Address Mode........................................................................ Figure 14.12 Example of DMA Transfer Timing in Single Address Mode ................................ Figure 14.13 Example of DMA Transfer Timing in Single Address Mode (External Memory Space (Ordinary Memory) External Device with DACK) .. Figure 14.14 Transfer Example in Cycle-Steal Mode ................................................................. Figure 14.15 Example of Transfer in Burst Mode....................................................................... Figure 14.16 Bus State in Multiple Channel Operation............................................................... Figure 14.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) ....................................... Figure 14.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) ....................................... Rev. 5.00 Dec 12, 2005 page lvi of lxxii Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 381 399 403 404 406 407 408 408 410 411 412 413 414 415 415 417 420 421 Figure 14.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles)................................................................................................................. Figure 14.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) ... Figure 14.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) ........................................ Figure 14.22 Burst Mode, Level Input ........................................................................................ Figure 14.23 Burst Mode, Edge Input ......................................................................................... Figure 14.24 Source Address Reload Function Diagram............................................................. Figure 14.25 Timing Chart of Source Address Reload Function................................................. Figure 14.26 CMT Block Diagram.............................................................................................. Figure 14.27 Counter Operation .................................................................................................. Figure 14.28 Count Timing ......................................................................................................... Figure 14.29 Timing of CMF Setting .......................................................................................... Figure 14.30 Timing of CMF Clear by the CPU ......................................................................... Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Timer (TMU) TMU Block Diagram.............................................................................................. Setting the Count Operation ................................................................................... Auto-Reload Counter Operation............................................................................. Count Timing when Internal Clock is Operating ................................................... Count Timing when On-Chip RTC Clock is Operating ......................................... UNF Set Timing ..................................................................................................... Status Flag Clear Timing........................................................................................ 422 423 424 425 426 427 428 431 435 436 437 437 444 451 452 452 453 453 454 Section 16 Realtime Clock (RTC) Figure 16.1 RTC Block Diagram............................................................................................... Figure 16.2(a) Setting the Time ................................................................................................. Figure 16.2(b) Setting the Time................................................................................................. Figure 16.3 Reading the Time ................................................................................................... Figure 16.4 Using the Alarm Function ...................................................................................... Figure 16.5 Example of Crystal Oscillator Circuit Connection................................................. Figure 16.6 Periodic Interrupt Function Setting ........................................................................ Serial Communication Interface (SCI) SCI Block Diagram ................................................................................................ SCPT[1]/SCK0 Pin ................................................................................................ SCPT[0]/TxD0 Pin................................................................................................. SCPT[0]/RxD0 Pin................................................................................................. Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)................................................. Figure 17.6 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)............................................................................................ Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 458 474 474 475 476 477 478 482 483 484 485 511 513 Rev. 5.00 Dec 12, 2005 page lvii of lxxii Figure 17.7 Sample SCI Initialization Flowchart ...................................................................... Figure 17.8 Sample Serial Transmission Flowchart .................................................................. Figure 17.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... Figure 17.10 Sample Serial Reception Data Flowchart (1) ......................................................... Figure 17.10 Sample Serial Reception Data Flowchart (2) ......................................................... Figure 17.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... Figure 17.12 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ........................................... Figure 17.13 Sample Multiprocessor Serial Transmission Flowchart ......................................... Figure 17.14 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................... Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (1)......................................... Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (2)......................................... Figure 17.16 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................... Figure 17.17 Data Format in Clock Synchronous Communication ............................................. Figure 17.18 Sample SCI Initialization Flowchart ...................................................................... Figure 17.19 Sample Serial Transmission Flowchart .................................................................. Figure 17.20 Sample SCI Transmission Operation in Clocked Synchronous Mode ................... Figure 17.21 Sample Serial Reception Flowchart (1).................................................................. Figure 17.21 Sample Serial Reception Flowchart (2).................................................................. Figure 17.22 Example of SCI Operation in Reception ................................................................ Figure 17.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ....... Figure 17.24 Receive Data Sampling Timing in Asynchronous Mode ....................................... Section 18 Smart Card Interface Figure 18.1 Smart Card Interface Block Diagram ..................................................................... Figure 18.2 Pin Connection Diagram for the Smart Card Interface........................................... Figure 18.3 Data Format for Smart Card Interface.................................................................... Figure 18.4 Waveform of Start Character.................................................................................. Figure 18.5 Initialization Flowchart (Example)......................................................................... Figure 18.6 Transmission Flowchart (Example) ....................................................................... Figure 18.7 Reception Flowchart (Example)............................................................................. Figure 18.8 Receive Data Sampling Timing in Smart Card Mode ............................................ Figure 18.9 Retransmission in SCI Receive Mode .................................................................... Figure 18.10 Retransmission in SCI Transmit Mode .................................................................. 514 515 517 518 519 521 522 523 525 526 527 528 529 531 532 533 534 535 536 537 540 544 549 550 552 556 558 560 562 563 564 Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.1 SCIF Block Diagram .............................................................................................. 566 Rev. 5.00 Dec 12, 2005 page lviii of lxxii Figure 19.2 SCPT[4]/TxD2 Pin................................................................................................. Figure 19.3 SCPT[4]/RxD2 Pin................................................................................................. Figure 19.4 Sample SCIF Initialization Flowchart .................................................................... Figure 19.5 Sample Serial Transmission Flowchart .................................................................. Figure 19.6 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) Figure 19.7 Example of Operation Using Modem Control (CTS)............................................. Figure 19.8 Sample Serial Reception Flowchart (1).................................................................. Figure 19.9 Sample Serial Reception Flowchart (2).................................................................. Figure 19.10 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... Figure 19.11 Example of Operation Using Modem Control (RTS)............................................. Figure 19.12 Receive Data Sampling Timing in Asynchronous Mode ....................................... Section 20 Serial IO (SIOF) Figure 20.1 SIOF Block Diagram.............................................................................................. Figure 20.2 Serial Clock Supply System ................................................................................... Figure 20.3 SIOF Serial Data Synchronized Timing................................................................. Figure 20.4 SIOF Transmit or Receive Timing ......................................................................... Figure 20.5 Transmit or Receive Data Bit Alignment ............................................................... Figure 20.6 Control Data Bit Alignment ................................................................................... Figure 20.7 Control Data Interface (Slot Position) .................................................................... Figure 20.8 Control Data Interface (Secondary FS) .................................................................. Figure 20.9 Example of Transmit Operation in Master ............................................................. Figure 20.10 Example of Receive Operation in Master............................................................... Figure 20.11 Example of Transmit Operation in Slave ............................................................... Figure 20.12 Example of Receive Operation in Slave................................................................. Figure 20.13 Transmit or Receive Timing (8 bits monaural--1) ................................................ Figure 20.14 Transmit or Receive Timing (8 bits monaural--2) ................................................ Figure 20.15 Transmit or Receive Timing (16 bits monaural--1) .............................................. Figure 20.16 Transmit or Receive Timing (16 bits stereo--1).................................................... Figure 20.17 Transmit or Receive Timing (16 bits stereo--2).................................................... Figure 20.18 Transmit or Receive Timing (16 bits stereo--3).................................................... Figure 20.19 Transmit or Receive Timing (16 bits monaural--2) .............................................. Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Analog Front End Interface (AFEIF) Block Diagram of AFE Interface ........................................................................... FIFO Interrupt Timing............................................................................................ Ringing Interrupt Occurrence Timing .................................................................... Interrupt Generator ................................................................................................. AFE Serial Interface............................................................................................... AFE Control Sequence........................................................................................... 567 568 592 593 595 595 596 597 599 599 602 606 630 631 632 634 636 637 638 641 642 643 644 648 648 649 649 650 650 651 658 672 672 673 673 674 Rev. 5.00 Dec 12, 2005 page lix of lxxii Figure 21.7 DAA Block Diagram.............................................................................................. 675 Figure 21.8 Ringing Detect Sequence ....................................................................................... 676 Section 22 USB Pin Multiplex Controller Figure 22.1 Block Diagram of USB PIN Multiplexer ............................................................... Figure 22.2 Example 1 of Transceiver Connection for USB function Controller (On-chip transceiver is used).................................................................................. Figure 22.3 Example 2 of Transceiver Connection for USB function Controller (On-chip transceiver is used).................................................................................. Figure 22.4 Example 3 of Transceiver Connection for USB function Controller (On-chip transceiver is not used)............................................................................ Figure 22.5 Example 4 of Transceiver Connection for USB function Controller (On-chip transceiver is not used)............................................................................ Figure 22.6 Example 1 of Transceiver Connection for USB Host Controller (On-chip transceiver is used).................................................................................. Figure 22.7 Example 2 of Transceiver Connection for USB Host Controller (On-chip transceiver is not used)............................................................................ Section 23 USB Function Controller Figure 23.1 Block Diagram of UBC.......................................................................................... Figure 23.2 Cable Connection Operation .................................................................................. Figure 23.3 Cable Disconnection Operation.............................................................................. Figure 23.4 Transfer Stage for Control Transfer ....................................................................... Figure 23.5 Setup Stage Operation ............................................................................................ Figure 23.6 Data Stage Operation (Control-In) ......................................................................... Figure 23.7 Data Stage Operation (Control-Out)....................................................................... Figure 23.8 Status Stage Operation (Control-In) ....................................................................... Figure 23.9 Status Stage Operation (Control-Out) .................................................................... Figure 23.10 EP1 Bulk-Out Transfer Operation.......................................................................... Figure 23.11 EP2 Bulk-In Transfer Operation ............................................................................ Figure 23.12 EP2 Interrupt-In Transfer Operation ...................................................................... Figure 23.13 Forcible Stall by Application.................................................................................. Figure 23.14 Automatic Stall by USB Function Module............................................................. Figure 23.15 TR Interrupt Flag Set Timing ................................................................................. Section 25 Figure 25.1 Figure 25.2 Figure 25.3 Figure 25.4 Figure 25.5 LCD Controller Block Diagram ....................................................................................................... Valid Display and Retrace Period .......................................................................... Color-Palette Data Format...................................................................................... Power-Supply Control Sequence and States of the LCD Module .......................... Power-Supply Control Sequence and States of the LCD Module .......................... 680 684 685 686 687 689 690 692 704 705 706 707 708 710 711 712 713 714 716 719 721 723 764 786 798 803 803 Rev. 5.00 Dec 12, 2005 page lx of lxxii Figure 25.6 Power-Supply Control Sequence and States of the LCD Module .......................... Figure 25.7 Power-Supply Control Sequence and States of the LCD Module .......................... Figure 25.8 Clock and LCD Data Signal Example.................................................................... Figure 25.9 Clock and LCD Data Signal Example.................................................................... Figure 25.10 Clock and LCD Data Signal Example.................................................................... Figure 25.11 Clock and LCD Data Signal Example.................................................................... Figure 25.12 Clock and LCD Data Signal Example.................................................................... Figure 25.13 Clock and LCD Data Signal Example.................................................................... Figure 25.14 Clock and LCD Data Signal Example.................................................................... Figure 25.15 Clock and LCD Data Signal Example.................................................................... Figure 25.16 Clock and LCD Data Signal Example.................................................................... Figure 25.17 Clock and LCD Data Signal Example.................................................................... Figure 25.18 Clock and LCD Data Signal Example.................................................................... Figure 25.19 Clock and LCD Data Signal Example.................................................................... Figure 25.20 Clock and LCD Data Signal Example.................................................................... Figure 25.21 Clock and LCD Data Signal Example.................................................................... Figure 25.22 Clock and LCD Data Signal Example.................................................................... 804 804 809 810 810 811 811 812 812 813 813 814 815 816 817 818 819 Section 26 Pin Function Controller (PFC) Figure 26.1 Overview of the Pin Selection Function................................................................. 821 A/D Converter A/D Converter Block Diagram............................................................................... A/D Data Register Access Operation (Reading H'AA40) ...................................... Example of A/D Converter Operation (Single Mode, Channel 2 Selected) ........... Example of A/D Converter Operation (Multi Mode, Channels AN4 to AN6 Selected) .................................................... Figure 28.5 Example of A/D Converter Operation (Scan Mode, Channels AN4 to AN6 Selected) ...................................................... Figure 28.6 A/D Conversion Timing......................................................................................... Figure 28.7 External Trigger Input Timing ............................................................................... Figure 28.8 Definitions of A/D Conversion Accuracy .............................................................. Figure 28.9 Example of Analog Input Protection Circuit .......................................................... Figure 28.10 Analog Input Pin Equivalent Circuit ...................................................................... Section 28 Figure 28.1 Figure 28.2 Figure 28.3 Figure 28.4 858 866 868 870 872 873 874 876 877 877 Section 29 D/A Converter Figure 29.1 D/A Converter Block Diagram............................................................................... 879 Figure 29.2 Example of D/A Converter Operation.................................................................... 883 Section 30 PC Card Controller (PCC) Figure 30.1 PC Card Controller Block Diagram........................................................................ 886 Rev. 5.00 Dec 12, 2005 page lxi of lxxii Figure 30.2 Figure 30.3 Figure 30.4 Figure 30.5 Figure 30.6 Figure 30.7 Figure 30.8 Figure 30.9 Section 31 Figure 31.1 Figure 31.2 Figure 31.3 Continuous 32-MB Area Mode .............................................................................. Continuous 16-MB Area Mode (Area 6)................................................................ SH7727 Interface.................................................................................................... PCMCIA Memory Card Interface Basic Timing.................................................... PCMCIA Memory Card Interface Wait Timing..................................................... PCMCIA I/O Card Interface Basic Timing ............................................................ PCMCIA I/O Card Interface Wait Timing ............................................................. Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 889 890 903 907 908 909 910 911 User-Debugging Interface (H-UDI) H-UDI Block Diagram ........................................................................................... 916 TAP Controller State Transitions ........................................................................... 925 H-UDI Reset........................................................................................................... 927 Section 32 Electrical Characteristics Figure 32.1 Power-On Sequence ............................................................................................... Figure 32.2 Power Supply Voltage and Operating Frequency .................................................. Figure 32.3 EXTAL Clock Input Timing .................................................................................. Figure 32.4 CKIO Clock Input Timing ..................................................................................... Figure 32.5 CKIO Clock Output Timing................................................................................... Figure 32.6 Power-on Oscillation Settling Time ....................................................................... Figure 32.7 Oscillation Settling Time at Standby Return (Return by Reset)............................. Figure 32.8 Oscillation Settling Time at Standby Return (Return by NMI).............................. Figure 32.9 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0).............. Figure 32.10 PLL Synchronization Settling Time by Reset or NMI Interrupt ............................ Figure 32.11 PLL Synchronization Settling Time by IRQ/IRL and PINT0/1 Interrupt .............. Figure 32.12 PLL Sync Stabilization Time at Frequency Multiplier Factor Change .................. Figure 32.13 Reset Input Timing................................................................................................. Figure 32.14 Interrupt signal Input Timing ................................................................................. Figure 32.15 Bus Release Timing................................................................................................ Figure 32.16 Pin Drive Timing at Standby.................................................................................. Figure 32.17 Basic Bus Cycle (No Wait) .................................................................................... Figure 32.18 Basic Bus Cycle (One Wait)................................................................................... Figure 32.19 Basic Bus Cycle (External Wait, WAITSEL = 1) .................................................. Figure 32.20 Burst ROM Bus Cycle (No Wait) .......................................................................... Figure 32.21 Burst ROM Bus Cycle (Two Waits) ...................................................................... Figure 32.22 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ........................................ Figure 32.23 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) .... Figure 32.24 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) .... Figure 32.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1) ................................................................... Rev. 5.00 Dec 12, 2005 page lxii of lxxii 930 935 941 941 942 942 943 943 944 944 945 945 947 947 948 948 951 952 953 954 955 956 957 958 959 Figure 32.26 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0) ................................................................... Figure 32.27 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0).............. Figure 32.28 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1).............. Figure 32.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0) ............................................................................. Figure 32.30 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0) ............................................................................. Figure 32.31 Synchronous DRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1).......................... Figure 32.32 Synchronous DRAM Self-Refresh Cycle (TPC = 0).............................................. Figure 32.33 Synchronous DRAM Mode Register Write Cycle ................................................. Figure 32.34 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................... Figure 32.35 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) ............................ Figure 32.36 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait)........... Figure 32.37 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1) .... Figure 32.38 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)........................................ Figure 32.39 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) ............................ Figure 32.40 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing, WAITSEL = 1) ................................. Figure 32.41 Oscillation Settling Time at RTC Crystal Oscillator Power-on.............................. Figure 32.42 SCK Input Clock Timing ....................................................................................... Figure 32.43 SCI I/O Timing in Clock Synchronous Mode ........................................................ Figure 32.44 I/O Port Timing ...................................................................................................... Figure 32.45 DREQ Input Timing............................................................................................... Figure 32.46 DRAK Output Timing............................................................................................ Figure 32.47 TCK Input Timing.................................................................................................. Figure 32.48 TRST Input Timing (Reset Hold)........................................................................... Figure 32.49 H-UDI Data Transfer Timing................................................................................. Figure 32.50 ASEMD0 Input Timing.......................................................................................... Figure 32.51 LCDC AC Specification......................................................................................... Figure 32.52 SIOMCLK Input Timing........................................................................................ Figure 32.53 SIOF Transmit/Receive Timing (Master Mode 1: Fall Sampling Time) ............... Figure 32.54 SIOF Transmit/Receive Timing (Master Mode 1: Rise Sampling Time)............... Figure 32.55 SIOF Transmit/Receive Timing (Master Mode 2: Fall Sampling Time) ............... Figure 32.56 SIOF Transmit/Receive Timing (Master Mode 2: Rise Sampling Time)............... Figure 32.57 SIOF Transmit/Receive Timing (Slave Mode 1 and Slave Mode 2)...................... Figure 32.58 USB Clock Timing................................................................................................. Figure 32.59 AFEIF Module AC Timing .................................................................................... 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 976 976 976 977 977 977 978 979 979 979 981 982 983 983 984 984 985 985 988 Rev. 5.00 Dec 12, 2005 page lxiii of lxxii Figure 32.60 Output Load Circuit................................................................................................ 989 Figure 32.61 Load Capacitance vs. Delay Time.......................................................................... 990 Appendix D Package Dimensions Figure D.1 Package Dimensions (PRQP0240KC-B).............................................................. 1029 Figure D.2 Package Dimensions (PLBG0240JA-A) .............................................................. 1030 Rev. 5.00 Dec 12, 2005 page lxiv of lxxii Tables Section 1 Overview and Pin Functions Table 1.1 SH7727 Features .................................................................................................... 2 Table 1.2 SH7727 Pin Function ............................................................................................. 11 Section 2 CPU Table 2.1 Initial Register Values ............................................................................................ 24 Table 2.2 Detail Behavior Under Each SH3-DSP Mode........................................................ 33 Table 2.3 Destination Register of DSP Instructions............................................................... 34 Table 2.4 Source Register of DSP Operations ....................................................................... 35 Table 2.5 DSR Register Bits .................................................................................................. 36 Table 2.6 Word Data Sign Extension ..................................................................................... 41 Table 2.7 Delayed Branch Instructions .................................................................................. 41 Table 2.8 T Bit ....................................................................................................................... 42 Table 2.9 Immediate Data Referencing.................................................................................. 42 Table 2.10 Absolute Address Referencing ............................................................................... 43 Table 2.11 Displacement Referencing...................................................................................... 43 Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions ........................ 44 Table 2.13 Overview of Data Transfer Instructions ................................................................. 48 Table 2.14 CPU Instruction Formats........................................................................................ 55 Table 2.15 Double Data Transfer Instruction Formats ............................................................. 59 Table 2.16 Single Data Transfer Instruction Formats .............................................................. 60 Table 2.17 A-Field Parallel Data Transfer Instructions............................................................ 61 Table 2.18 B-Field ALU Operation Instructions and Multiply Instructions............................. 62 Table 2.19 CPU Instruction Types ........................................................................................... 65 Table 2.20 Data Transfer Instructions ...................................................................................... 69 Table 2.21 Arithmetic Operation Instructions .......................................................................... 71 Table 2.22 Logic Operation Instructions.................................................................................. 73 Table 2.23 Shift Instructions .................................................................................................... 74 Table 2.24 Branch Instructions................................................................................................. 75 Table 2.25 System Control Instructions ................................................................................... 76 Table 2.26 Added CPU System Control Instructions............................................................... 81 Table 2.27 Double Data Transfer Instructions ......................................................................... 83 Table 2.28 Single Data Transfer Instructions........................................................................... 84 Table 2.29 Correspondence between DSP Data Transfer Operands and Registers.................. 85 Table 2.30 DSP Operation Instruction Formats ....................................................................... 86 Table 2.31 Correspondence between DSP Instruction Operands and Registers....................... 87 Table 2.32 DSP Operation Instructions.................................................................................... 88 Table 2.33 DC Bit Update Definitions ..................................................................................... 94 Rev. 5.00 Dec 12, 2005 page lxv of lxxii Table 2.34 Examples of NOPX and NOPY Instruction Codes ................................................ 96 Section 3 Memory Management Unit (MMU) Table 3.1 Register Configuration ........................................................................................... 103 Table 3.2 Access States Designated by D, C, and PR Bits..................................................... 110 Section 4 Exception Handling Table 4.1 Register Configuration ........................................................................................... 131 Table 4.2 Exception Event Vectors ........................................................................................ 133 Table 4.3 Exception Codes..................................................................................................... 136 Table 4.4 Types of Reset........................................................................................................ 141 Section 5 Cache Table 5.1 Cache Specifications .............................................................................................. 149 Table 5.2 LRU and Way Replacement................................................................................... 151 Table 5.3 Register Configuration ........................................................................................... 151 Table 5.4 LRU and Way Replacement (when W2LOCK=1)................................................. 153 Table 5.5 LRU and Way Replacement (when W3LOCK=1)................................................. 153 Table 5.6 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) .................... 154 Section 6 X/Y Memory Table 6.1 X/Y Memory Specifications................................................................................... 161 Section 7 Interrupt Controller (INTC) Table 7.1 Pin Configuration ................................................................................................... Table 7.2 Register Configuration ........................................................................................... Table 7.3 IRL3 to IRL0 Pins and Interrupt Levels................................................................. Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)........................... Table 7.5 Interrupt Exception Handling Sources and Priority (IRL Mode) ........................... Table 7.6 Interrupt Level and INTEVT Code ........................................................................ Table 7.7 Interrupt Request Sources and IPRA to IPRG........................................................ Table 7.8 Interrupt Response Time ........................................................................................ 167 168 171 174 176 178 179 200 Section 8 User Break Controller Table 8.1 Register Configuration ........................................................................................... 205 Table 8.2 Data Access Cycle Addresses and Operand Size Comparison Conditions ............ 223 Section 9 Power-Down Modes and Software Reset Table 9.1 Power-Down Modes............................................................................................... 234 Table 9.2 Pin Configuration ................................................................................................... 235 Table 9.3 Register Configuration ........................................................................................... 235 Rev. 5.00 Dec 12, 2005 page lxvi of lxxii Table 9.4 Register States in Standby Mode............................................................................ 244 Section 10 On-Chip Oscillation Circuits Table 10.1 Clock Pulse Generator Pins and Functions............................................................. Table 10.2 Register Configuration ........................................................................................... Table 10.3 Clock Operating Modes.......................................................................................... Table 10.4 Available Combination of Clock Mode and FRQCR Values................................. Table 10.5 Register Configuration ........................................................................................... 261 261 262 264 272 Section 11 Extend Clock Pulse Generator for USB (EXCPG) Table 11.1 Pin Configuration ................................................................................................... 280 Table 11.2 Register Configuration ........................................................................................... 280 Section 12 Bus State Controller (BSC) Table 12.1 Pin Configuration ................................................................................................... Table 12.2 Register Configuration ........................................................................................... Table 12.3 Physical Address Space Map ................................................................................. Table 12.4 Correspondence between External Pins (MD4 and MD3) and Memory bus width in area0 ............................................................................. Table 12.5 SH7727 and PCMCIA Pins .................................................................................... Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment .......................... Table 12.7 16-Bit External Device/Big Endian Access and Data Alignment .......................... Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment ............................ Table 12.9 32-Bit External Device/Little Endian Access and Data Alignment........................ Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment........................ Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment.......................... Table 12.12 Relationship between Synchronous DRAM type, bus width and AMX ................ Table 12.13 Relationship between LSI Address Pins and Synchronous DRAM Address Pins . 286 288 290 291 292 316 317 318 319 320 321 334 335 Section 13 Li Bus State Controller (LBSC) Table 13.1 Register Configuration ........................................................................................... 367 Section 14 Direct Memory Access Controller (DMAC) Table 14.1 Pin Configuration ................................................................................................... Table 14.2 DMAC Registers .................................................................................................... Table 14.3 Selecting External Request Modes with the RS Bits.............................................. Table 14.4 Selection of On-Chip Module Request Modes Using RS3 to RS0 Bits ................. Table 14.5 DMA Transfers ...................................................................................................... Table 14.6 Relationship of Request Modes and Bus Modes .................................................... Table 14.7 Register Configuration ........................................................................................... 382 382 400 401 405 416 432 Rev. 5.00 Dec 12, 2005 page lxvii of lxxii Table 14.8 Transfer Conditions and Register Settings for Transfer between On-Chip A/D Converter and External Memory ............................................................................ 438 Table 14.9 DMAC Sate after the Fourth Transfer Ends ........................................................... 439 Table 14.10 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter .............................................................................. 440 Section 15 Timer (TMU) Table 15.1 TMU Register Configuration ................................................................................. 445 Table 15.2 TMU Interrupt Sources .......................................................................................... 454 Section 16 Realtime Clock (RTC) Table 16.1 RTC Pin Configuration .......................................................................................... Table 16.2 RTC Registers ........................................................................................................ Table 16.3 Day-of-Week Codes (RWKCNT) .......................................................................... Table 16.4 Day-of-Week Codes (RWKAR)............................................................................. Table 16.5 Recommended Oscillator Circuit Constants (Recommended Values) ................... Section 17 Serial Communication Interface (SCI) Table 17.1 SCI Pins 485 Table 17.2 Registers 486 Table 17.3 SCSMR Settings..................................................................................................... Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1)................................... Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (2)................................... Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (3)................................... Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (4)................................... Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (5)................................... Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (6)................................... Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (7)................................... Table 17.5 Bit Rates and SCBRR Settings in Clock Synchronous Mode ................................ Table 17.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................ Table 17.7 Maximum Bit Rates during External Clock Input (Asynchronous Mode) ............. Table 17.8 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)..... Table 17.9 Serial Mode Register Settings and SCI Communication Formats.......................... Table 17.10 SCSMR and SCSCR Settings and SCI Clock Source Selection............................. Table 17.11 Serial Communication Formats (Asynchronous Mode) ......................................... Table 17.12 Receive Error Conditions and SCI Operation ........................................................ Table 17.13 SCI Interrupt Sources ............................................................................................. Table 17.14 SCSSR Status Flags and Transfer of Receive Data................................................ 459 460 463 467 477 501 502 502 503 503 504 504 505 506 507 508 508 510 510 512 520 538 539 Rev. 5.00 Dec 12, 2005 page lxviii of lxxii Section 18 Smart Card Interface Table 18.1 SCI Pins 545 Table 18.2 Registers 545 Table 18.3 Register Settings for the Smart Card Interface ....................................................... Table 18.4 Relationship of n to CKS1 and CKS0 .................................................................... Table 18.5 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0).................................. Table 18.6 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0).................................. Table 18.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)....................... Table 18.8 Register Set Values and SCK Pin........................................................................... Table 18.9 Smart Card Mode Operating State and Interrupt Sources ...................................... 551 553 553 553 554 554 561 Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.1 SCIF Pins................................................................................................................ 568 Table 19.2 Registers 569 Table 19.3 SCSMR2 Settings................................................................................................... 581 Table 19.4 Bit Rates and SCBRR2 Settings............................................................................. 581 Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................ 585 Table 19.6 SCSMR2 Settings and SCIF Transmit/Receive ..................................................... 589 Table 19.7 Settings for SCSMR2 and SCSCR2 and Selection of Clock Source of SCIF ........ 590 Table 19.8 Serial Transmit/Receive Formats ........................................................................... 590 Table 19.9 SCIF Interrupt Sources........................................................................................... 600 Section 20 Table 20.1 Table 20.2 Table 20.3 Table 20.4 Table 20.5 Table 20.6 Table 20.7 Table 20.8 Table 20.9 Table 20.10 Table 20.11 Table 20.12 Table 20.13 Serial IO (SIOF) SIOF Pin List.......................................................................................................... SIOF Register Configuration.................................................................................. Examples of SIOF Clock Frequency ...................................................................... Serial Transmit Mode............................................................................................. Frame Length ......................................................................................................... Transmit Data Sound Mode ................................................................................... Receive Data Sound Mode ..................................................................................... Control Data Channel Number Establishment ....................................................... Transmit Request Submit Condition ...................................................................... Receive Request Submit Condition........................................................................ Transmit or Receive Reset...................................................................................... SIOF Interrupt Factors............................................................................................ Setting Conditions for the Transmit or Receive Interrupt Flag .............................. 607 607 630 632 633 635 635 636 639 640 645 646 647 Section 21 Analog Front End Interface (AFEIF) Table 21.1 Pins for AFE Interface............................................................................................ 659 Rev. 5.00 Dec 12, 2005 page lxix of lxxii Table 21.2 Table 21.3 AFEIF Registers..................................................................................................... 659 Telephone Number and Data.................................................................................. 669 Section 22 USB Pin Multiplex Controller Table 22.1 Pin Configuration (Digital Transceiver Signal)...................................................... Table 22.2 Pin Configuration (Analog Transceiver Signal) ..................................................... Table 22.3 Pin Configuration (Power Control signal).............................................................. Table 22.4 Register Configuration ........................................................................................... 681 681 682 682 Section 23 USB Function Controller Table 23.1 Pin Configuration and Functions............................................................................ 692 Table 23.2 USB Function Module Registers............................................................................ 693 Table 23.3 Command Decoding on Application Side .............................................................. 717 Section 24 USB HOST Module Table 24.1 Pin Configuration ................................................................................................... 726 Table 24.2 Register Configuration ........................................................................................... 727 Section 25 LCD Controller Table 25.1 Pin Configuration ................................................................................................... Table 25.2 Register Configuration ........................................................................................... Table 25.3 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (32-bit Bus SDRAM) ...................................................... Table 25.4 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (16-bit Bus SDRAM) ...................................................... Table 25.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates ........ Table 25.6 LCDC Operating Modes ........................................................................................ Table 25.7 LCD Module Power-Supply States ........................................................................ 765 765 792 795 805 806 806 Section 26 Pin Function Controller (PFC) Table 26.1 List of Multiplexed Pins ......................................................................................... 821 Table 26.2 Pin Function Controller Registers .......................................................................... 826 Section 27 I/O Ports Table 27.1 Pin Function Controller Registers .......................................................................... Table 27.2 Read/Write Operation of the Ports A to C, E, J, K Data Register .......................... Table 27.3 Read/Write Operation of the Port D Data Register (PDDR) ................................. Table 27.4 Read/Write Operation of the Ports F, M Data Register (PFDR, PMDR) ............... Table 27.5 Read/Write Operation of the Port G Data Register (PGDR) .................................. Table 27.6 Read/Write Operation of the Port H Data Register (PHDR) ................................. Table 27.7 Read/Write Operation of the Port L Data Register (PLDR) ................................... Rev. 5.00 Dec 12, 2005 page lxx of lxxii 846 847 849 850 851 853 854 Table 27.8 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 856 Section 28 A/D Converter Table 28.1 A/D Converter Pins.................................................................................................. 859 Table 28.2 A/D Converter Registers ........................................................................................ 860 Table 28.3 Analog Input Channels and A/D Data Registers .................................................... 861 Table 28.4 A/D Conversion Time (Single Mode) .................................................................... 874 Table 28.5 Analog Input Pin Ratings ....................................................................................... 878 Table 28.6 Relationship between Access Size and Read Data ................................................. 878 Section 29 D/A Converter Table 29.1 D/A Converter Pins ................................................................................................ 880 Table 29.2 D/A Converter Registers ........................................................................................ 880 Section 30 PC Card Controller (PCC) Table 30.1 PC Card Controller Registers ................................................................................. 887 Table 30.2 Features of the PCMCIA Interface......................................................................... 888 Table 30.3 PCMCIA Support Interface.................................................................................... 904 Section 31 User-Debugging Interface (H-UDI) Table 31.1 H-UDI Registers..................................................................................................... Table 31.2 H-UDI Commands ................................................................................................. Table 31.3 Correspondence between SH7727 Pins and Boundary-Scan Register ................... Table 31.4 Reset Configuration................................................................................................ Section 32 Table 32.1 Table 32.2 Table 32.2 Table 32.3 Table 32.4 Table 32.4 Table 32.5 Table 32.6 Table 32.7 Table 32.8 Table 32.9 Table 32.10 Table 32.11 Table 32.12 Table 32.13 Electrical Characteristics Absolute Maximum Ratings................................................................................... DC Characteristics (1) ............................................................................................ DC Characteristics (2) ............................................................................................ Permitted Output Current Values ........................................................................... Maximum Operating Frequencies (1) .................................................................... Maximum Operating Frequencies (2) .................................................................... Clock Timing (1) .................................................................................................... Clock Timing (2) .................................................................................................... Clock Timing (3) .................................................................................................... Clock Timing (4) .................................................................................................... Control Signal Timing............................................................................................ Bus Timing............................................................................................................. Peripheral Module Signal Timing .......................................................................... H-UDI-Related Pin Timing .................................................................................... LCDC Timing ........................................................................................................ 917 918 919 926 929 931 933 934 936 936 937 938 939 940 946 949 975 978 980 Rev. 5.00 Dec 12, 2005 page lxxi of lxxii Table 32.14 Table 32.15 Table 32.16 Table 32.17 Table 32.18 Table 32.19 Table 32.20 SIOF Module Signal Timing .................................................................................. USB Module Signal Timing................................................................................... USB Electrical Characteristics (Full-Speed) .......................................................... USB Electrical Characteristics (Low-Speed) ......................................................... AFEIF Module Signal Timing................................................................................ A/D Converter Characteristics ............................................................................... D/A Converter Characteristics ............................................................................... 982 985 986 986 987 991 991 Appendix A Pin Functions Table A.1 Pin Functions.......................................................................................................... 993 Table A.2 Treatment of Unused Pins ...................................................................................... 999 Table A.3 Pin Status (Normal Memory/Little Endian) ......................................................... 1004 Table A.4 Pin Status (Normal Memory/Big Endian) ............................................................ 1006 Table A.5 Pin Status (Burst ROM/Little Endian).................................................................. 1008 Table A.6 Pin Status (Burst ROM/Big Endian) .................................................................... 1010 Table A.7 Pin Status (Synchronous DRAM/Little Endian)................................................... 1012 Table A.8 Pin Status (Synchronous DRAM/Big Endian) ..................................................... 1013 Table A.9 Pin Status (PCMCIA/Little Endian) ..................................................................... 1014 Table A.10 Pin Status (PCMCIA/Big Endian)........................................................................ 1016 Appendix B Control Registers Table B.1 Memory-Mapped Control Registers (Address Map) ............................................ 1018 Rev. 5.00 Dec 12, 2005 page lxxii of lxxii Section 1 Overview and Pin Functions Section 1 Overview and Pin Functions 1.1 Features The SH7727 is a single-chip RISC microprocessor that integrates a 32-bit RISC-type SuperH RISC engine architecture CPU with digital signal processing (DSP) extension as its core that has a cache memory, an on-chip X/Y memory, and a memory management unit (MMU) as well as peripheral functions required for system configuration. The SH7727 includes data protection, virtual memory, and other functions provided by incorporating an MMU into a SuperH Series microprocessor (SH-1 or SH-2). The SH7727 chip has the on-chip X/Y memory with large capacitance, on-chip DSP module, and emulator support. The provision of on-chip DSP functions enables applications that previously required the use of two chips--a microprocessor and a DSP--to be implemented with a single chip. High-speed data transfers with a direct memory access controller (DMAC) and an external memory access support function enables direct connection to each memory. The SH7727 microprocessor also supports an infrared communication function, a stereo audio recording and playback function, a USB host controller, a function controller, an LCD controller, a PCMCIA interface, an A/D converter, and a D/A converter. The USB host controller and LCD controller have bus master functions, so that data supplied from an external memory (area 3) can be freely processed. Because the USB host controller, in particular, conforms to Open HCI standards, it is extremely easy to transfer data from the PC of a device driver or other devices. Also, low-power operation suitable for battery operation is possible because the LCD controller continues to display even in sleep mode. An internal USB transceiver is also provided, eliminating the need for attachments. A powerful built-in power management function keeps power consumption low, even during highspeed operation. In particular, power consumption can be significantly reduced by halting the X/Y memory. Because the LSI operates at a maximum speed eight times of the speed at which the system operates, it is ideal for electronic devices, which require both high speed and low power consumption. The features of this LSI are listed in table 1.1. The specifications of this LSI are listed in table 1.2. Rev. 5.00 Dec 12, 2005 page 1 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Table 1.1 Item CPU SH7727 Features Features * * * * Original Renesas SuperH architecture Object code level compatible with SH-1, SH-2 and SH-3 32-bit internal data bus General-register Sixteen 32-bit general registers (eight 32-bit shadow registers) Eight 32-bit control registers Four 32-bit system registers * RISC-type instruction set Instruction length: 16-bit fixed length to improve code efficiency Load-store architecture Delayed branch instructions Instruction set based on C language * * * * Instruction execution time: one instruction/cycle for basic instructions Logical address space: 4 Gbytes Space identifier ASID: 8 bits, 256 logical address space Five-stage pipeline Rev. 5.00 Dec 12, 2005 page 2 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Item DSP Features * * * * * Mixture of 16-bit and 32-bit instructions 32-/40-bit internal data bus Multiplier, ALU, barrel shifter and DSP register 16 bits x 16 bits 32-bit one cycle multiplier Large DSP data register Six 32-bit data registers Two 40-bit data registers * Extended Harvard Architecture for DSP data bus Two data buses One instruction bus * * * * * * Clock pulse generator (CPG) * * Max. four parallel operations: ALU, multiply and two load or store Two addressing units to generate addresses for two memory access DSP data addressing modes: increment, indexing (with or without modulo addressing) Zero overhead repeat loop control Conditional execution instructions User-DSP mode and privileged-DSP mode Clock mode: An input clock can be selected from the external input (EXTAL or CKIO) or crystal oscillator. Three types of clocks generated: CPU clock: 1-16 times the input clock Bus clock: 1-4 times the input clock Peripheral clock: 1/4-4 times the input clock * Power-down modes: Sleep mode Standby mode Module standby mode (X/Y memory standby enabled) * One-channel watchdog timer Rev. 5.00 Dec 12, 2005 page 3 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Item Memory management unit (MMU) Features * * * * * * Cache memory * * * * * X/Y memory * 4 Gbytes of address space, 256 address spaces (ASID 8 bits) Page unit sharing Supports multiple page sizes: 1 kbytes or 4 kbytes 128-entry, 4-way set associative TLB Supports software selection of replacement method and randomreplacement algorithms Contents of TLB can directly be accessed according to the address mapping 16-kbyte cache, mixed instruction/data 256 entries, 4-way set associative, 16-byte block length Write-back, write-through, least recently used (LRU) replacement algorithm 1-stage write-back buffer Maximum 2 ways of the cache can be locked User-selectable mapping mechanism Fixed mapping for mission-critical realtime applications Automatic mapping through TLB for easy to use * 3 independent read/write ports 8-/16-/32-bit access from the CPU Maximum two 16-bit accesses from the DSP 8-/16-/32-bit access from the DMAC * Interrupt controller (INTC) User break controller (UBC) * * * * * 8-kbyte RAM for X and Y memory individually 7 external interrupt pins (NMI, IRQ5-IRQ0) On-chip peripheral interrupts: set priority levels for each module 2 break channels Addresses, data values, type of access, and data size can all be set as break conditions Supports a sequential break function Rev. 5.00 Dec 12, 2005 page 4 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Item Bus state controller (BSC) Features * Physical address space divided into six areas (area 0, areas 2 to 6), each of up to 64 Mbytes, with the following features settable for each area: Bus size (8, 16, or 32 bits) Number of wait cycles (hardware wait function also waited) Direct connection of SRAM, synchronous DRAM, and burst ROM possible by designating memory to be connected to each area Supports PCMCIA interface (2 channels) Chip select signals (CS0, CS2-CS6) for relevant area * Synchronous DRAM refresh function Programmable refresh interval Supports CAS-before-RAS refresh and self-refresh modes Supports power-down DRAM * * Li bus state * controller (LBSC) * * User debug * Interface (H-UDI) * * Timer (TMU) * * * Realtime clock (RTC) * * Synchronous DRAM burst access function Big endian or little endian can be specified Bus State Controller for LCDC or USB Host Supports synchronous DRAM Synchronous DRAM access function (area 3) E10A emulator support Pin arrangement conforming to JTAG specification Realtime branch trace 3-channel auto-reload-type 32-bit timer Choice of six counter input clocks Maximum resolution: 2 MHz Built-in clock, calendar functions, and alarm functions On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle interrupt) of 1/256 second Asynchronous mode or clock synchronous mode can be selected Full-duplex communication Supports smart card interface Serial communication interface (SCI) * * * Rev. 5.00 Dec 12, 2005 page 5 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Item Features Synchronous 16 step, 8/16/32 bit word FIFO for transmission/reception Supports 8-bit/16-bit mono/stereo sound playback or recording DMA can be transferred Supports frame sync signal 16-byte FIFO for transmission/reception DMA can be transferred On-chip modem control function 4 channels Burst mode and cycle-steal mode External request operating mode 1-channel 16-bit compare match timer Supports control signals for one slot Interchangeable with SH7709 when not in use (2 slots) Conforms to OHCI Rev. 1.0 USB Rev. 1.1 compatible Up to 127 endpoints Supports INT/BULK/CONTROL/ISO modes Bus master controller (can access area 3 synchronous DRAM) 2 ports with analog transceiver (1of 2 is common with USB function) External clock input function USB Rev. 1.1 compatible Up to 4 endpoints Supports INT/BULK/CONTROL modes (ISO mode not supported) 1 port with analog transceiver (common with Host), 12 Mbps only External clock input function * * * Serial communication interface (SCIF) * * * Serial I/O (SIOF) * Direct memory * access controller * (DMAC) * * PC card controller * * USB Host * controller (USBH) * * * * * * USB Function * controller (USBF) * * * * Rev. 5.00 Dec 12, 2005 page 6 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Item LCD controller (LCDC) Features * * * * * * * * * AFE I/F * * * * I/O port A/D converter (ADC) * * * * D/A converter (DAC) * * * Product lineup SH7727 160 MHz products From 16 x 1 to 1024 x 1024 pixels can be supported 4/8/15/16 bpp (bit per pixel) color modes 1/2/4/6 bpp (bit per pixel) gray scale 8-bit Frame rate controller TFT/DSTN/STN Signal polarity setting function Hardware panel rotation Power control function Selectable clock source (LCLK, bus clock (B), or peripheral clock (P)) ST7550 direct interface Telephone line control 128-word FIFO for transfer 128-word FIFO for receive Thirteen 8-bit I/O ports 10 bits 4 LSB, 6 channels Conversion time: 15 s Input range: 0-Vcc (max. 3.6 V) 8 bits 4 LSB, 2 channels Conversion time: 10 s Output range: 0-Vcc (max. 3.6 V) As of June 1, 2005 Operating Frequency Model Name HD6417727F160C Package 240-pin plastic HQFP (PRQP0240KC-B) Power Supply Voltage I/O Internal 3.0 V to 1.70 V to 160 MHz 3.6 V 2.05 V HD6417727BP160C 240-pin CSP (PLBG0240JA-A) 100 MHz products 2.6 V to 1.60 V to 100 MHz 3.6 V 2.05 V HD6417727F100C 240-pin plastic HQFP (PRQP0240KC-B) HD6417727BP100C 240-pin CSP (PLBG0240JA-A) Rev. 5.00 Dec 12, 2005 page 7 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions 1.2 Block Diagram Internal SRAM (XY RAM) instruction/data for CPU/DSP 16 kbytes SuperH CPU core DSP core Memory management unit (MMU) Cache memory 16 kbytes CPU bus (L bus) Cache access controller (CCN) User break controller (UBC) Direct memory access controller (DMAC) Bridge Interrupt controller (INTC) User debug interface (H-UDI) Clock pulse generator (CPG) Bus state controller (BSC) Real time clock (RTC) Internal bus (I bus) Internal bus 2 (I2 bus) Serial communication interface (SCIF) Serial/ smart card (SCI) Timer (TMU) A/D converter (ADC) D/A converter (DAC) Peripheral bus (P bus) Peripheral bus controller Peripheral bus 1 (P1 bus) Peripheral bus 2 (P2 bus) Arbitration 512-byte SRAM Analog front end interface (AFEIF) 128-byte SRAM Audio CODEC interface (SIOF) PC card controller (PCC) USB function controller (USBF) 288-byte SRAM Li bus state controller (LBSC) LI bus 2.4-kbyte line buffer SRAM LCD display controller (LCDC) 512-byte pallet SRAM USB host controller (USBH) Figure 1.1 Block Diagram Rev. 5.00 Dec 12, 2005 page 8 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions 1.3 1.3.1 Pin Description Pin Arrangement EXTAL XTAL Vcc Vss PCC0WAIT/PTH[6]/AUDCK Vcc-PLL2 CAP2 Vss-PLL2 Vss-PLL1 CAP1 Vcc-PLL1 MD0 PCC0VS2/PTF[0]/Reserved PCC0VS1/PTF[1]/Reserved PCCREG/PTF[2]/Reserved PTF[3]/PINT[11]/Reserved PTF[4]/ PINT[12]/TCK PTF[5]/PINT[13]/TDI PTF[6]/PINT[14]/TMS VccQ PTF[7]/PINT[15]/TRST VssQ PCC0CD1/PTG[0]/AUDATA[0] Vcc PCC0CD2/PTG[1]/AUDATA[1] Vss PCC0BVD1/PTG[2]/AUDATA[2] PCC0BVD2/PTG[3]/AUDATA[3] PTG[4] PTG[5]/ASEBRKAK ASEMD0 IOIS16/PTG[7] ADTRG/PTH[5] RESETM WAIT PCC0DRV/DACK0 PCC0RESET/DRAK0 PTE[0]/TDO PTE[3]/FLM PTE[6]/M_DISP PTD[7]/DON Vcc PTD[5]/CL1 Vss Reserved/PTJ[5] Reserved/PTJ[4] VccQ Reserved/PTJ[3] VssQ Reserved/CAS/PTJ[2] Reserved/PTJ[1] RAS3/PTJ[0] CKE/PTK[5] PTE[1]/USB2_pwr_en PTE[2]/USB1_pwr_en RTS2/USB1d_TXENL USB2_ovr_cr nt USB1_ovr_cr nt/USBF_VBUS Reserved/USB1d_SUSPEND PTM[4]/PINT[4]/ AFE_RDET 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 Vcc-RTC XTAL2 EXTAL2 Vss-RTC MD1 MD2 NMI IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] VEPWC VCPWC MD5 BREQ BACK VssQ CKIO2 VccQ D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] D25/PTB[1] D24/PTB[0] VssQ D23/PTA[7] VccQ D22/PTA[6] D21/PTA[5] D20/PTA[4] Vss D19/PTA[3] Vcc D18/PTA[2] D17/PTA[1] D16/PTA[0] D15 VssQ D14 VccQ D13 D12 D11 D10 D9 D8 D7 D6 VssQ D5 VccQ D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 LCD15/PTM[3]/PINT[10] LCD14/PTM[2]/PINT[9] LCD13/PTM[1]/PINT[8] LCD12/PTM[0] STATUS0/PTJ[6] STATUS1/PTJ[7] CL2/PTH[7] VssQ CKIO VccQ TxD0/SCPT[0] SCK0/SCPT[1] TxD_SIO/SCPT[2] SIOMCLK/SCPT[3] TxD2/SCPT[4] SCK_SIO/SCPT[5] SIOFSYNC/SCPT[6] RxD0/SCPT[0] RxD_SIO/SCPT[2] Vss RxD2/SCPT[4] Vcc SCPT[7]/CTS2/IRQ5 LCD11/PTC[7]/PINT[3] LCD10/PTC[6]/PINT[2] LCD9/PTC[5]/PINT[1] VssQ LCD8/PTC[4]/PINT[0] VccQ LCD7/PTD[3] LCD6/PTD[2] LCD5/PTC[3] LCD4/PTC[2] LCD3/PTC[1] LCD2/PTC[0] LCD1/PTD[1] LCD0/PTD[0] DREQ0/PTD[4] LCLK/UCLK/PTD[6] RESETP CA MD3 MD4 Scan_testen AVcc_USB USB1_P(analog) USB1_M(analog) AVss_USB USB2_P(analog) USB2_M(analog) AVcc-USB AVss AN[2]/PTL[2] AN[3]/PTL[3] AN[4]/PTL[4] AN[5]/PTL[5] AVcc AN[6]/PTL[6]/DA[1] AN[7]/PTL[7]/DA[0] AVss 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Vcc = 1.9 V, Vss = GND for CPU core VccQ = 3.3 V, VssQ = GND for I/O buffer Digital and PLL GND must be separated and isolated from the other signals The order of pin name and default pin name has no relation. Please refer to pin table. SH-7727 PRQP0240KC-B (Top View) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTM[5]/PINT[5]/AFE_TXOUT/USB1d_TXSE0 PTM[6]/PINT[6]/AFE_RXIN/USB1d_SPEED PTM[7]/PINT[7]/AFE_FS/USB1d_RCV VccQ AFE_SCLK/USB1d_TXDPLS VssQ AFE_RLYCNT/USB1d_DMNS/PTK[1] AFE_HC1/USB1d_DPLS/PTK[0] CE2B/PTE[5] CE2A/PTE[4] CS6/CE1B CS5/CE1A/PTK[3] CS4/PTK[2] CS3 CS2 CS0 PTE[7]/PCC0RDY/AUDSYNC RD/WR VccQ WE3/DQMUU/ICIOWR/PTK[7] VssQ WE2/DQMUL/ICIORD/PTK[6] WE1/DQMLU/WE WE0/DQMLL RD BS/PTK[4] A25 Vcc A24 Vss A23 A22 VccQ A21 VssQ A20 A19 A18 A17 A16 A15 A14 A13 VccQ A12 VssQ A11 A10 A9 A8 A7 A6 A5 A4 VccQ A3 VssQ A2 A1 A0 Figure 1.2 Pin Arrangement (PRQP0240KC-B) Rev. 5.00 Dec 12, 2005 page 9 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions 1 A B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D6 16 D5 D1 VssQ A7 A9 17 D4 D3 D7 A5 A8 18 D2 D0 VssQ A1 VccQ 19 A0 A2 A3 A4 A6 A10 Vcc- EXT MD1 RTC AL2 VEP NMI IRQ1 BACK D31 WC D27 VssQ D19 D26 D22 Vss D16 VccQ D10 D17 D14 VCP AN6 AVss Vss- XTAL2 MD2 VssQ D30 WC RTC AVcc_ AN5 AVcc IRQ0 IRQ3 MD5 CKIO2 D29 USB AN3 AN7 AN2 IRQ2 IRQ4 BREQ VccQ D28 D11 VccQ D8 D9 D24 VccQ D21 D25 D23 D20 D18 VssQ D12 Vcc D15 D13 AVss AN4 USB USB 2_M 2_P AVss_ USB USB AVcc_ USB 1_M 1_P USB Scan_ MD4 MD3 testen CA A12 VssQ A11 A15 A19 A14 A18 A13 VccQ A17 A16 RES LCLK DRE LCD0 Q0 ETP LCD1 LCD2 LCD4 LCD3 VccQ LCD5 LCD6 LCD7 LCD10 LCD9 LCD8 VssQ RxD2 Vcc SCPT7 LCD11 RxD_ SIOF RxD0 Vss SIO SYNC TxD_ SIOM TxD2 SCK_ SIO CLK SIO STA CKIO TxD0 SCK0 TUS1 SH7727 PLBG0240JA-A (Top View) A21 VccQ VssQ A20 A23 A25 Vss Vcc A24 BS A22 RD WE0 WE1 WE2 VssQ WE3 VccQ RD/WR PTE7 CS0 CS5 CS2 CS3 CS4 CS6 VssQ CE2B AFE_ AFE_ CL2 LCD14 VssQ VccQ MD0 PTF3 VccQ Vcc PCC0 ASEM RESE PCC0 PTD7 PTJ5 VssQ PTJ1 PTM6 RLYCNT HC1 BVD1 D0 TM RESET STA LCD12 CAP1 Vss- Vcc- PCC PTF6 PCC0 PCC0 PTG5 ADT PTE0 Vcc PTJ4 CAS CKE CE2A VccQ AFE_ SCLK PLL2 PLL1 REG TUS0 CD1 BVD2 RG LCD13 EXTAL Vss XTAL USB1d_ USB2 Vcc- PCC0 PTF5 VssQ Vss PTG4 WAIT PTE3 PTD5 VccQ PTE2 PTM5 PTM7 SUSPEND ovr_crnt PLL2 VS1 Vss- PCC0 LCD15 Vcc PCC0 CAP2 PTF4 PTF7 PCC0 IOIS16 PCC0 PTE6 Vss PTJ3 RAS3 PTE1 RTS2 USB1 PTM4 PLL1 VS2 WAIT CD2 DRV ovr_crnt Figure 1.3 Pin Arrangement (PLBG0240JA-A) Rev. 5.00 Dec 12, 2005 page 10 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions 1.3.2 Table 1.2 Pin Functions SH7727 Pin Function I/O *1 -- O I -- I I I I/I/I I/I/I I/I/I I/I/I I/I O O I I O -- O -- IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO Function RTC power supply (1.9 V) On-chip RTC crystal oscillator pin On-chip RTC crystal oscillator pin RTC power supply (0 V) Clock mode setting Clock mode setting Nonmaskable interrupt request External interrupt / external interrupt / input port H External interrupt / external interrupt / input port H External interrupt / external interrupt / input port H External interrupt / external interrupt / input port H External interrupt request / input port H LCD panel VEE control LCD panel VCC control Endian setting Bus request Bus acknowledge Input/output power supply (0 V) System clock output Input/output power supply (3.3 V) Data bus / I/O port B Data bus / I/O port B Data bus / I/O port B Data bus / I/O port B Data bus / I/O port B Data bus / I/O port B Data bus / I/O port B Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A1 B4 A2 B3 A3 B5 A4 C4 A5 D4 C5 D5 A6 B6 C6 D6 A7 B7 C7 D7 A8 B8 C8 D8 A9 B9 D9 Vcc-RTC XTAL2 EXTAL2 Vss-RTC*1 MD1 MD2 NMI IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] VEPWC VCPWC MD5 BREQ BACK VssQ CKIO2 VccQ D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] D25/PTB[1] Rev. 5.00 Dec 12, 2005 page 11 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 C9 A10 D10 C10 B10 C11 D11 B11 A11 D12 C12 B12 A12 D13 C13 B13 A13 D14 C14 B14 A14 D15 C15 C17 A15 C16 A16 B15 A17 B17 A18 B16 B18 D24/PTB[0] VssQ D23/PTA[7] VccQ D22/PTA[6] D21/PTA[5] D20/PTA[4] Vss D19/PTA[3] Vcc D18/PTA[2] D17/PTA[1] D16/PTA[0] D15 VssQ D14 VccQ D13 D12 D11 D10 D9 D8 D7 D6 VssQ D5 VccQ D4 D3 D2 D1 D0 I/O IO/IO -- IO/IO -- IO/IO IO/IO IO/IO -- IO/IO -- IO/IO IO/IO IO/IO IO -- IO -- IO IO IO IO IO IO IO IO -- IO -- IO IO IO IO IO Function Data bus / I/O port B Input/output power supply (0 V) Data bus / I/O port A Input/output power supply (3.3 V) Data bus / I/O port A Data bus / I/O port A Data bus / I/O port A Power supply (0 V) Data bus / I/O port A Power supply (1.9 V) Data bus / I/O port A Data bus / I/O port A Data bus / I/O port A Data bus Input/output power supply (0 V) Data bus Input/output power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Input/output power supply (0 V) Data bus Input/output power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus Rev. 5.00 Dec 12, 2005 page 12 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 A19 D18 B19 C18 C19 E18 D19 D17 E19 D16 E17 E16 F19 F18 F17 F16 G19 G18 G17 G16 H19 H18 H17 H16 J19 J18 J16 J17 K19 K16 K17 K18 L17 A0 A1 A2 VssQ A3 VccQ A4 A5 A6 A7 A8 A9 A10 A11 VssQ A12 VccQ A13 A14 A15 A16 A17 A18 A19 A20 VssQ A21 VccQ A22 A23 Vss A24 Vcc I/O O O O -- O -- O O O O O O O O -- O -- O O O O O O O O -- O -- O O -- O -- Function Address bus Address bus Address bus Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus Address bus Power supply (0 V) Address bus Power supply (1.9 V) Rev. 5.00 Dec 12, 2005 page 13 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 94 95 96 97 98 99 L16 L18 L19 M16 M17 M18 A25 BS/PTK[4] RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTK[6] VssQ WE3/DQMUU/ ICIOWR/PTK[7] VccQ RD/WR PTE[7]/PCC0RDY/ AUDSYNC CS0 CS2 CS3 CS4/PTK[2] CS5/CE1A/PTK[3] CS6/CE1B CE2A/PTE[4] CE2B/PTE[5] AFE_HC1/ USB1d_DPLS/ PTK[0] AFE_RLYCNT/ USB1d _DMNS/ PTK[1] VssQ AFE_SCLK/ USB1d _TXDPLS VccQ I/O O O/IO O O/O O/O/O O/O/ O/IO -- O/O/ O/IO -- O IO/I/O O O O O/IO O/O/IO O/O O/IO O/IO O/I/IO Function Address bus Bus cycle start signal / I/O port K Read strobe D7-D0 select signal / DQM (SDRAM) D15-D8 select signal / DQM (SDRAM) / PCMCIA WE D23-D16 select signal / DQM (SDRAM) / PCMCIA I/O read / I/O port K Input/output power supply (0 V) D31-D24 select signal / DQM (SDRAM) / PCMCIA I/O write / I/O port K Input/output power supply (3.3 V) Read/write I/O port E / PCMCIA0 ready / AUD synchronization Chip select 0 Chip select 2 Chip select 3 Chip select 4 / I/O port K Chip select 5 / CE1 (area 5 PCMCIA) / I/O port K Chip select 6 / CE1 (area 6 PCMCIA) Area 5 PCMCIA card enable / I/O port E Area 6 PCMCIA card enable / I/O port E AFE hardware control signal / D+ signal input / I/O port K AFE relay control signal / D- signal input / I/O port K Input/output power supply (0 V) AFE clock / D+ transmit output Input/output power supply (3.3 V) 100 101 M19 N16 102 103 104 105 106 107 108 109 110 111 112 113 N17 N18 N19 P16 P17 P18 P19 R16 R17 U17 R19 T17 114 T19 O/I/IO 115 116 117 R18 U19 U18 -- I/O -- Rev. 5.00 Dec 12, 2005 page 14 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 118 V19 PTM[7]/PINT[7]/ AFE_FS/ USB1d_RCV PTM[6]/PINT[6]/ AFE_RXIN/ USB1d_SPEED PTM[5]/PINT[5]/ AFE_TXOUT/ USB1d_TXSE0 PTM[4]/PINT[4]/ AFE_RDET Reserved/ USB1d_SUSPEND USB1_ovr_crnt/ USBF_VBUS USB2_ovr_crnt RTS2/ USB1d_TXENL PTE[2]/ USB1_pwr_en PTE[1]/ USB2_pwr_en CKE/PTK[5] RAS3/PTJ[0] Reserved/PTJ[1] Reserved/CAS/ PTJ[2] VssQ Reserved/PTJ[3] VccQ Reserved/PTJ[4] Reserved/PTJ[5] Vss PTD[5]/CL1 Vcc PTD[7]/DON PTE[6]/M_DISP I/O I/I/I/I Function Input port M / port interrupt / AFE frame synchronization / receive data input Input port M / port interrupt / AFE receive data / transceiver speed control Input port M / port interrupt / AFE transmit data / SE0 output Input port M / port interrupt / AFE ringing detection Reserved/Transceiver suspend state output USB host 1 overcurrent detection / USB function VBUS USB host 2 overcurrent detection SCIF RTS pin / USB output enable pin I/O port E / USB1 voltage control I/O port E / USB2 voltage control CK enable (SDRAM) / I/O port K RAS for SDRAM / I/O port J Reserved / I/O port J Reserved / CAS for SDRAM / I/O port J Input/output power supply (0 V) Reserved / I/O port J Input/output power supply (3.3 V) Reserved / I/O port J Reserved / I/O port J Power supply (0 V) I/O port D / LCD line clock Power supply (1.9 V) I/O port D / LCD DISPLAY on I/O port E / LCD alternating signal / DISP signal 119 T18 I/I/I/O 120 V18 I/I/O/O 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 W19 V16 W18 V17 W17 V15 W16 U16 W15 T16 U15 T15 W14 V14 U14 T14 W13 V13 U13 T13 W12 I/I/I O/O I/I I O/O IO/O IO/O O/IO O/IO O/IO O/O/IO -- O/IO -- O/IO O/IO -- IO/O -- IO/O IO/O Rev. 5.00 Dec 12, 2005 page 15 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 V12 U12 T12 W11 V11 T11 U11 W10 T10 U10 V10 U9 T9 V9 W9 T8 U8 V8 W8 T7 U7 V7 W7 T6 U6 PTE[3]/FLM PTE[0]/TDO PCC0RESET/ DRAK0 PCC0DRV/DACK0 WAIT RESETM ADTRG/PTH[5] IOIS16/PTG[7] ASEMD0 PTG[5]/ASEBRKAK PTG[4] I/O IO/O IO/O O/O O/O I I I/I I/I I I/O I Function I/O port E / LCD frame line marker I/O port E / test data output PCC reset / DMA request receive PCC buffer control / DMA acknowledge 0 Hardware wait request Manual reset request Analog trigger / input port H IOIS16 (PCMCIA) / input port G ASE mode Input port G / ASE break acknowledge Input port G PCC BVD2 pin / input port G / AUD data PCC BVD1 pin / input port G / AUD data Power supply (0 V) PCMCIA0 CD2 pin / input port G / AUD data Power supply (1.9 V) PCC CD1 pin / input port G / AUD data Input/output power supply (0 V) Input port F / port interrupt / test reset Input/output power supply (3.3 V) Input port F / port interrupt / test mode switch Input port F / port interrupt / test data input Input port F / port interrupt / test clock Input port F / port interrupt / Reserved PCC REG pin / input port F/ Reserved PCC0BVD2/PTG[3]/ I/I/O AUDATA[3] PCC0BVD1/PTG[2]/ I/I/O AUDATA[2] Vss PCC0CD2/PTG[1]/ AUDATA[1] Vcc PCC0CD1/PTG[0]/ AUDATA[0] VssQ PTF[7]/PINT[15]/ TRST VccQ PTF[6]/PINT[14]/ TMS PTF[5]/PINT[13]/ TDI PTF[4]/PINT[12]/ TCK PTF[3]/PINT[11]/ Reserved PCCREG/PTF[2]/ Reserved -- I/I/O -- I/I/O -- I/I/I -- I/I/I I/I/I I/I/I I/I/O O/I/O Rev. 5.00 Dec 12, 2005 page 16 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 V6 W6 T5 U5 U3 W5 U4 W4 V5 W3 V3 W2 V4 V2 W1 T2 V1 U2 U1 R2 T1 T3 R1 T4 R3 R4 P1 P2 P3 PCC0VS1/PTF[1]/ Reserved PCC0VS2/PTF[0]/ Reserved MD0 Vcc-PLL1*2 CAP1 Vss-PLL1*2 Vss-PLL2*2 CAP2 Vcc-PLL2 *2 PCC0WAIT/PTH[6]/ AUDCK Vss Vcc XTAL EXTAL LCD15/PTM[3]/ PINT[10] LCD14/PTM[2]/ PINT[9] LCD13/PTM[1]/ PINT[8] LCD12/PTM[0] STATUS0/PTJ[6] STATUS1/PTJ[7] CL2/PTH[7] VssQ CKIO VccQ TxD0/SCPT[0] SCK0/SCPT[1] TxD_SIO/SCPT[2] SIOMCLK/SCPT[3] TxD2/SCPT[4] I/O I/I/O I/I/IO I -- -- -- -- -- -- I/I/I -- -- O I O/I/I O/I/I O/I/I O/I O/IO O/IO O/IO -- IO -- O/O IO/IO O/O I/IO O/O Function PCC VS1 pin / input port F/ Reserved PCC VS2 pin / input port F/ Reserved Clock mode setting PLL1 power supply (1.9 V) PLL1 external capacitance pin PLL1 power supply (0 V) PLL2 power supply (0 V) PLL2 external capacitance pin PLL2 power supply (1.9V) PCC hardware wait request / input port H / AUD clock Power supply (0 V) Power supply (1.9 V) Clock oscillator External clock / crystal oscillator LCD data output / input port M / port interrupt LCD data output / input port M / port interrupt LCD data output / input port M / port interrupt LCD data output / input port M Processor status / I/O port J Processor status / I/O port J LCD clock output / I/O port H Input/output power supply (0 V) System clock input/output Input/output power supply (3.3 V) Transmit data 0 / SCI output port Serial clock 0 / SCI I/O port SIOF transmit data / SCI output port SIOF clock input / SCI I/O port Transmit data 2 / SCI output port Rev. 5.00 Dec 12, 2005 page 17 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 P4 N1 N2 N3 N4 M1 M2 M3 M4 L1 L2 L4 L3 K1 K4 K3 K2 J3 J4 J2 J1 H4 H3 H2 H1 G4 G3 G2 G1 F4 SCK_SIO/SCPT[5] I/O IO/IO Function SIOF communication clock / SCI I/O port SIOF frame synch. / SCI I/O port Receive data 0 / SCI input port SIOF receive data / SCI input port Power supply (0 V) Receive data 2 / SCI input port Power supply (1.9 V) SCI input port / SCIF clear to send / external interrupt request LCD data out / I/O port C / port interrupt LCD data out / I/O port C / port interrupt LCD data out / I/O port C / port interrupt Input/output power supply (0 V) LCD data out / I/O port C / port interrupt Input/output power supply (3.3 V) LCD data out / I/O port D LCD data out / I/O port D LCD data out / I/O port C LCD data out / I/O port C LCD data out / I/O port C LCD data out / I/O port C LCD data out / I/O port D LCD data out / I/O port D DMA request / input port D LCD clock / USB clock / input port D Power-on reset request Hardware standby request Area 0 bus width setting Area 0 bus width setting Test pin (fixed to 3.3 V) USB analog power supply (3.3 V) SIOFSYNC/SCPT[6] IO/IO RxD0/SCPT[0] RxD_SIO/SCPT[2] Vss RxD2/SCPT[4] Vcc I/I I/I -- I/I -- SCPT[7]/CTS2/IRQ5 I/I/I LCD11/PTC[7]/ PINT[3] LCD10/PTC[6]/ PINT[2] LCD9/PTC[5]/ PINT[1] VssQ LCD8/PTC[4]/ PINT[0] VccQ LCD7/PTD[3] LCD6/PTD[2] LCD5/PTC[3] LCD4/PTC[2] LCD3/PTC[1] LCD2/PTC[0] LCD1/PTD[1] LCD0/PTD[0] DREQ0/PTD[4] LCLK/UCLK/PTD[6] RESETP CA MD3 MD4 Scan_testen AVcc_USB O/IO/I O/IO/I O/IO/I -- O/IO/I -- O/IO O/IO O/IO O/IO O/IO O/IO O/IO O/IO I/I I/I/I I I I I I -- Rev. 5.00 Dec 12, 2005 page 18 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Pin No. Pin No. (PRQP0240KC-B) (PLBG0240JA-A) Name 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 F3 F2 F1 E4 E3 C3 E1 D3 D1 E2 C1 C2 B1 D2 B2 USB1_P(analog) USB1_M(analog) AVss_USB USB2_P(analog) USB2_M(analog) AVcc_USB AVss AN[2]/PTL[2] AN[3]/PTL[3] AN[4]/PTL[4] AN[5]/PTL[5] AVcc AN[6]/PTL[6]/DA[1] AN[7]/PTL[7]/DA[0] AVss I/O IO IO -- IO IO -- -- I/I I/I I/I I/I -- I/I/O I/I/O -- Function USB1 data I/O (plus) USB1 data I/O (minus) USB analog power supply (0 V) USB2 data I/O (plus) USB2 data I/O (minus) USB analog power supply (3.3 V) Analog power supply (0 V) A/D converter input / input port L A/D converter input / input port L A/D converter input / input port L A/D converter input / input port L Analog power supply (3.3 V) A/D converter input / input port L / D/A converter output A/D converter input / input port L / D/A converter output Analog power supply (0 V) Notes: All Vcc/Vss should be connected to the all system power supply (so that power is supplied at all times). 1. Always supply power to the Vcc-RTC, even if RTC is not being used. 2. Always supply power to the Vcc-PLL, even if the internal PLL is not being used. 3. Drive high when using the user system alone, and not using an emulator or the H-UDI. When this pin is low or open, RESETP may be masked. Rev. 5.00 Dec 12, 2005 page 19 of 1034 REJ09B0254-0500 Section 1 Overview and Pin Functions Rev. 5.00 Dec 12, 2005 page 20 of 1034 REJ09B0254-0500 Section 2 CPU Section 2 CPU 2.1 Registers The SH7727 has the same registers as in SH-3. In addition, the SH7727 also support the same DSP-related registers seen in SH-DSP. The basic software-accessible registers are divided into four distinct groups: * General-purpose registers * Control registers * System registers * DSP registers With the exception of a number of DSP registers, all of these registers are 32-bit width. The general-purpose registers are accessible from the user mode, with R0 to R7 banked to provide each processor mode access to a separate set of the R0 to R7 registers (i.e. R0 to R7_BANK0, and R0 to R7_BANK1). In the privileged mode, the register bank (RB) bit in the status register (SR) defines which set of banked registers (R0 to R7_BANK0 or R0 to R7_BANK1) is accessed as general-purpose registers, and which are accessed only by the LDC/STC instructions. The control registers can be accessed by the LDC/STC instructions. The GBR, RS, RE, and MOD registers can also be accessed in user mode. Control registers are: * SR: Status register * SSR: Saved status register * SPC: Saved program counter * GBR: Global base register * VBR: Vector base register * RS: Repeat start register (DSP mode only) * RE: Repeat end register (DSP mode only) * MOD: Modulo register (DSP mode only) The system registers are accessed by the LDS/STS instructions (the PC cannot be accessed by software, but is included here because its contents are saved in, and restored from, SPC). The system registers are: * MACH: Multiply and accumulate high register * MACL: Multiply and accumulate low register * PR: Procedure register Rev. 5.00 Dec 12, 2005 page 21 of 1034 REJ09B0254-0500 Section 2 CPU * PC: Program counter This section explains the usage of these registers in different modes. Figures 2.1 and 2.2 show the register configuration in each processing mode. Switching between user mode and privileged mode is carried out by means of the processing operation mode bit (MD) in the status register. The DSP mode is switched by means of the DSP bit in the status register. Rev. 5.00 Dec 12, 2005 page 22 of 1034 REJ09B0254-0500 Section 2 CPU 31 R0_BANK0*1 *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 0 31 R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 0 GBR MACH MACL PR PC (a) User mode register configuration (b) Privileged mode register configuration (RB = 1) (c) Privileged mode register configuration (RB = 0) Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode. 2. Bank register 3. Bank register Accessed as a general register when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Bank register Accessed as a general register when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.1 Register Configuration in Each Processing Mode (1) Rev. 5.00 Dec 12, 2005 page 23 of 1034 REJ09B0254-0500 Section 2 CPU 32 31 A0G A1G A0 A1 M0 M1 X0 X1 Y0 Y1 DSR MS ME MOD 0 (d) DSP mode register configuration (DSP = 1) Figure 2.2 Register Configuration in Each Processing Mode (2) Register values after a reset are shown in table 2.1. Table 2.1 Type General registers Control registers Initial Register Values Registers R0 to R15 SR Initial Value* Undefined MD bit = 1, RB bit = 1, BL bit = 1, I3 to I0 = 1111 (H'F), reserved bits = 0, others undefined Undefined H'00000000 Undefined Undefined Undefined H'A0000000 Undefined H'00000000 GBR, SSR, SPC VBR RS, RE MOD System registers DSP registers MACH, MACL, PR PC A0, A0G, A1, A1G, M0, M1, X0, X1, Y0, Y1 DSR Note: * Initialized by a power-on or manual reset. Rev. 5.00 Dec 12, 2005 page 24 of 1034 REJ09B0254-0500 Section 2 CPU 2.1.1 General Purpose Registers There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. With SuperH microcomputer type instructions, R0 is used as an index register. With a number of instructions, R0 is the only register that can be used. R15 is used as the stack pointer (SP). In exception handling, R15 is used to reference the stack when saving and restoring the status register (SR) and program counter (PC). With DSP type instructions, eight of the sixteen general registers are used for addressing of X and Y data memory and data memory (single data) that uses the L-bus. To access X memory, R4 and R5 are used as X address register [Ax] and R8 is used as X index register [Ix]. To access Y memory, R6 and R7 are used as Y address register [Ay] and R9 is used as Y index register [Iy]. To access single data that uses the L-bus, R2, R3, R4, and R5 are used as single data address register [As] and R8 is used as single data index register [Is]. Figure 2.3 shows the general purpose registers, which are identical to SH-3's, when DSP extension is disabled. 31 R0*1 *2 R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 R8 R9 R10 R11 R12 R13 R14 R15 0 General Registers (when not in DSP mode) Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source register or destination register. 2. R0 to R7 are banked registers. In user mode, BANK0 is used. In privileged mode, SR.RB specifies BANK. SR.RB = 0; BANK0 is used SR.RB = 1; BANK1 is used Figure 2.3 General Purpose Register (Not in DSP Mode) Rev. 5.00 Dec 12, 2005 page 25 of 1034 REJ09B0254-0500 Section 2 CPU On the other hand, R2 to R9 registers are also used for the DSP data address calculations, see figure 2.4, when DSP extension is enabled. Another symbol that represents the purpose of the registers in DSP type instruction is [ ]. 31 R0 R1 R2 [As] R3 [As] R4 [As, Ax] R5 [As, Ax] R6 [Ay] R7 [Ay] R8 [Ix, Is] R9 [Iy] R10 R11 R12 R13 R14 R15 Single data transfer operation R2 to R5 [As]: Address register set for memory. R8 [Is]: Index register for address register set As. X or Y data transfer operation R4, R5 [Ax]: Address register set for X data memory. R8 [x]: Index register for address register set Ax. R6, R7 [Ay]: R9 [Iy]: Address register set for Y data memory. Index register for address register set Ay. 0 General Registers (DSP mode enabled) Figure 2.4 General Purpose Register (DSP Mode) DSP type instructions can access X and Y data memory simultaneously. To specify addresses for X and Y data memory, two address pointer sets are prepared. These are: R8[Ix], R4, R5[Ax] for X memory access, and R9[Iy], R6, R7[Ay] for Y memory access. The names (symbol) R2 to R9 are used in the Assembler, but users can use other register names that represent the purpose of the register in the DSP instruction explicitly. In the assembly program, user can use an alias for the register. The coding in assembler is as follows. Ix: .REG (R8) Rev. 5.00 Dec 12, 2005 page 26 of 1034 REJ09B0254-0500 Section 2 CPU The name Ix is the alias for R8. Other aliases are as follows. Ax0: Ax1: Ix: Ay0: Ay1: Iy: As0: As1: As2: As3: Is: .REG .REG .REG .REG .REG .REG .REG .REG .REG .REG .REG (R4) (R5) (R8) (R6) (R7) (R9) (R4) ; This is optional. If you need another alias for single data transfer. (R5) ; This is optional. If you need another alias for single data transfer. (R2) (R3) (R8) ; This is optional. If you need another alias for single data transfer. 2.1.2 Control Registers SH7727 has eight control registers: SR, SSR, SPC, GBR, VBR, RS, RE, and MOD (figure 2.5). SSR, SPC, GBR and VBR are the same as the SH-3 registers. The DSP mode is activated only when SR.DSP = 1. Repeat start register RS, repeat end register RE, and repeat counter RC (12-bit part of the SR) and repeat control bits RF0 and RF1 are new registers and control bits which are used for repeat control. Modulo register MOD and modulo control bits DMX and DMY in the SR are also new register and control bits. In the SR, there are six additional control bits: RC[11:0], RF0, RF1, DMX, DMY and DSP. Bits DMX, DMY, RC[11:0], and RF[1:0] can be modified in supervisor mode, DSP supervisor mode, and DSP user mode. The DMX and DMY are used for modulo addressing control. If the DMX is 1 then the modulo addressing mode is effective for the X memory address pointer, Ax (R4 or R5). If the DMY is 1 then it is effective for the Y memory address pointer, Ay (R6 or R7). However, both X and Y address pointer cannot be operated under the modulo addressing mode even though both DMX and DMY bits are set. The case of DMX = DMY = 1 is reserved for future expansion. When both DMX and DMY are set simultaneously, the hardware will preliminary treat only address pointer as the modulo addressing mode. Modulo addressing is available for X and Y data transfer operation (MOVX and MOVY), but not for single data transfer operation (MOVS). The RF1 and RF0 hold information of the number of repeat steps and they are set when a SETRC instruction is executed. When RF[1:0] shows 00, the current repeat module consists of one-step instruction. When RF[1:0] = 01, it means two-step instructions. When RF[1:0] = 11, it means Rev. 5.00 Dec 12, 2005 page 27 of 1034 REJ09B0254-0500 Section 2 CPU three-step instruction. When RF[1:0] = 10, it means the current repeat module consists of four or more instructions. Although RC[11:0] and RF[1:0] can be changed by a store/load to SR, use of the dedicated manipulation instruction SETRC is recommended. The SR also has a 12-bit repeat counter RC which is used for efficient loop control. Repeat start register (RS) and repeat end register (RE) are also introduced for the loop control. They keep the start and end addresses of a loop (the contents of the registers, RS and RE are slightly different from the actual loop start and end address). Modulo register, MOD is introduced to realize modulo addressing for circular data buffering. MOD keeps the modulo start address (MS) and the modulo end address (ME). In order to access RS, RE and MOD, load/store (control register) instructions for them are introduced. An example for RS is as follows: LDC Rm,RS; LDC.L @Rm+,RS; STC RS,Rn; STC.L RS,@-Rn; Rm RS (Rm) RS, Rm+4 Rm RS Rn Rn-4 Rn, RS (Rn) Address set instructions for the RS and RE are also prepared. LDRS @(disp,PC); disp x 2 + PC RS LDRE @(disp,PC); disp x 2 + PC RE Rev. 5.00 Dec 12, 2005 page 28 of 1034 REJ09B0254-0500 Section 2 CPU 31 28 27 RC 16 15 13 12 0-0 11 10 9 8 7 I3 6 5 4 3 2 1 0 T 0 MD RB BL DSP DMY DMX M Q I2 I1 I0 RF1 RF0 S SR (Status register) MD bit: Processor operation mode MD = 1: Privileged mode MD = 0: User mode Register bank bit; used to define the general registers in privileged mode. RB = 1: R0_BANK1 to R7_BANK1 are used as general registers. R0_BANK0 to R7_BANK0 accessed by LDC/STC instructions. RB = 0: R0_BANK0 to R7_BANK0 are used as general registers. R0_BANK1 to R7_BANK1 accessed by LDC/STC instructions. Block bit; used to mask exception in privileged mode. BL = 1: Interrupts are masked (not accepted) BL = 0: Interrupts are accepted RB bit: BL bit: RC [11:0]: 12-bit repeat counter DSP bit: DSP operation mode DSP = 1: DSP instructions (LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+, DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD, STC RS/RE/MOD,Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx) are enabled. DSP = 0: All DSP instructions are treated as illegal instructions; only SH3 instructions are supported. Modulo addressing enable for Y side Modulo addressing enable for X side Used by DIV0U/S and DIV1 instructions. 4-bit field indicating the interrupt request mask level. Used for repeat control Used by the MAC instructions and DSP data. The MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT and DT instructions use the T bit to indicate true (logic one) or false (logic zero). The ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L and ROTCR/L instructions also use the T bit to indicate a carry, borrow, overflow, or underflow. DMY bit: DMX bit: Q, M bit: I [3:0]: RF [1:0]: S bit: T bit: Reserved bits: Always read as 0, and should always be written with 0 (bit 31, bits 15 to 13). Figure 2.5 Control Registers (1) Rev. 5.00 Dec 12, 2005 page 29 of 1034 REJ09B0254-0500 Section 2 CPU 31 SSR 31 SPC 31 GBR 31 VBR 31 RS 31 RE 31 MOD ME 16 15 MS 0 Saved status register (SSR) 0 Saved program counter (SPC) 0 Global base register 0 Vector base register 0 Repeat start register 0 Repeat end register 0 Modulo register ME: Modulo end address, MS: Modulo start address Saved status register (SSR) Stores current SR value at time of exception to indicate processor status when returning to instruction stream from exception handler. Saved program counter (SPC) Stores current PC value at time of exception to indicate return address on completion of exception handling. Global base register (GBR) Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for data transfer and logical operations on the on-chip peripheral module register area. Vector base register (VBR) Stores base address of exception vector area. Repeat start register (RS) Used in DSP mode only. Indicates start address of repeat loop. Repeat end register (RE) Used in DSP mode only. Indicates address of repeat loop end. Modulo register (MOD) Used in DSP mode only. MOD[31:16]: ME: Modulo end address, MOD[15:0]: MS: Modulo start address. In X/Y operand address generation, the CPU compares the address with ME, and if it is the same, loads MS in either the X or Y operand address register (depending on bits DMX and DMY in the SR register). Figure 2.5 Control Registers (2) Rev. 5.00 Dec 12, 2005 page 30 of 1034 REJ09B0254-0500 Section 2 CPU 2.1.3 System Registers The SH7727 has four system registers, MACL, MACH, PR and PC (figure 2.6). 31 MACH MACL 31 PR 31 PC 0 Multiply and accumulate high and low registers (MACH/L) Store the results of multiplicationand accumulation operations. 0 Procedure register (PR) Stores the subroutine procedure return address. 0 Program counter (PC) Indicates the starting address that is four addresses ahead. Figure 2.6 System Registers DSR, A0, X0, X1, Y0 and Y1 registers are also treated as system registers. So, data transfer instructions between general registers and system registers are supported for them. 2.1.4 DSP Registers The SH7727 has eight data registers and one control register (figure 2.7). The data registers are 32-bit width with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G and A1G), giving them a total width of 40 bits. Three types of operations access the DSP data registers. First one is the DSP data. When a DSP fixed-point data operation uses A0 or A1 for source register, it uses the guard bits (bits 39 to 32). When it uses A0 or A1 for destination register, bits 39 to 32 in the guard bit are valid. When a DSP fixed-point data operation uses the DSP registers other than A0 and A1 for source register, it sign-extends the source value to bits 39 to 32. When it uses them for destination register, the bits 39 to 32 of the result is discard. Second one is X and Y data transfer operation, "MOVX.W MOVY.W". This operation accesses the X and Y memories through 16-bit X and Y data buses (figure 2.8). Registers to be loaded or stored by this operation are always upper 16 bits (bits 31 to 16). X0 and X1 can be destination of the X memory load and Y0 and Y1 can be destination of Y memory load, but other register cannot be destination register of this operation. Rev. 5.00 Dec 12, 2005 page 31 of 1034 REJ09B0254-0500 Section 2 CPU When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored to the X or Y memory by this operation, but other registers cannot be stored. There are some rules to access SR by STC/LDC instruction. 1. When DSP is disabled, same as SH-3 behavior 2. When SDP supervisor mode, same as supervisor mode 3. In User DSP mode, SR can be read by STC instruction 4. In User DSP mode, LDC to SR is allowed but no DSP related bits are protected from write. Table 2.2 shows detail behavior under each SH3-DSP mode. Rev. 5.00 Dec 12, 2005 page 32 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.2 Detail Behavior Under Each SH3-DSP Mode Supervisor Mode DSP Supervisor Mode MD = 1 & DSP = 1 S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK DSP User Mode MD = 0 & DSP = 1 S: OK, L: NG S: OK, L: NG S: OK, L: NG S: OK, L: OK S: OK, L: NG S: OK, L: OK S: OK, L: OK S: OK, L: NG S: OK, L: NG S: OK, L: NG S: OK, L: OK S: OK, L: NG S: OK, L: NG SETRC instruction SETRC instruction Access to DSP Related Bits by Dedicated Instruction User Mode MD = 0 & DSP = 0 S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction S, L: illegal instruction Fields MD RB BL RC [11:0] DSP DMX DMY Q M I [3:0] RF [1:0] S T MD = 1 & DSP = 0 S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK Initial Value after Reset 1 1 1 0b000000000000 0 0 0 X X 1111 X X X (S) STC: Store SR to Rn, SR Rn (L) LDC: Load Rn to SR, Rn SR OK: Allowed to STC/LSC operation Illegal instruction: Treated as illegal instruction, exception should be occurred NG: Keep previous value, nothing changed Third one is single-data transfer instruction, "MOVS.W" and "MOVS.L". This instruction accesses any memory location through LDB (figure 2.8). All DSP registers connect to the LDB and be able to be source and destination register of the data transfer. It has word and longword access modes. In the word mode, registers to be loaded or stored by this instruction are upper 16 bits (bits 31 to 16) for the DSP registers except A0G and A1G. When data is loaded into a register Rev. 5.00 Dec 12, 2005 page 33 of 1034 REJ09B0254-0500 Section 2 CPU other than A0G and A1G in the word mode, lower half of the register is cleared. When it is A0 or A1, the data is sign-extended to bits 39 to 32 and lower half of it is cleared. When A0G or A1G is a destination register in the word mode, data is loaded into 8-bit register, but A0 or A1 is not cleared. In the longword mode, when a destination register is A0 or A1, it is sign-extended to bits 39 to 32. Tables 2.3 and 2.4 show the data type of registers used in the DSP instructions. Some instructions cannot use some registers shown in the tables because of instruction code limitation. For example, PMULS can use A1 for source registers, but cannot use A0. These tables ignore details of the register selectability. Table 2.3 Destination Register of DSP Instructions Guard Bits Registers A0, A1 DSP Instructions Fixed-point, PSHA, PMULS Integer, PDMSB Logical, PSHL Data transfer A0G, A1G X0, X1 Y0, Y1 M0, M1 Data transfer DSP MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PSHA, PMULS Integer, logical, PDMSB, PSHL Data transfer MOVX/Y.W, MOVS.W MOVS.L 39 32 31 Register Bits 16 15 0 Sign-extended 40-bit result Sign-extended 24-bit result Cleared 16-bit result Sign-extended 16-bit data Sign-extended 32-bit data Data Data No update No update 32-bit result 16-bit result 16-bit result 32-bit data Cleared Cleared Cleared Cleared Cleared Rev. 5.00 Dec 12, 2005 page 34 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.4 Source Register of DSP Operations Guard Bits Register Bits 16 15 0 40-bit data 24-bit data 16-bit data 16-bit data 32-bit data Data Data Sign* Sign* 32-bit data 16-bit data 16-bit data 16-bit data 32-bit data Registers A0, A1 DSP Instructions Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVX/Y.W, MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVS.W MOVS.L 39 32 31 A0G, A1G X0, X1 Y0, Y1 M0, M1 Data transfer DSP Note: * Sign-extend the data and feed to the ALU 39 32 31 A0 A1 M0 M1 X0 X1 Y0 Y1 (a) DSP Data Registers 0 A0G A1G 31 876543210 GT Z N V CS [2:0] DC (b) DSP Status Register (DSR) Reset status DSR: All zeros Others: Undefined Figure 2.7 DSP Registers Rev. 5.00 Dec 12, 2005 page 35 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.5 Bit 31-8 7 DSR Register Bits Name (Abbreviation) Reserved bits Signed greater than bit (GT) Function 0: Always read out; always use 0 as a write value Indicates that the operation result is positive (excepting 0), or that operand 1 is greater than operand 2 1: Operation result is positive, or operand 1 is greater Indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 1: Operation result is zero (0), or equivalence Indicates that the operation result is negative, or that operand 1 is smaller than operand 2 1: Operation result is negative, or operand 1 is smaller 6 Zero bit (Z) 5 Negative bit (N) 4 3-1 Overflow bit (V) Indicates that the operation result has overflowed 1: Operation result has overflowed Status selection bits (CS) Designate the mode for selecting the operation result status set in the DC bit Do not set either 110 or 111 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed above mode 0 DSP status bit (DC) Sets the status of the operation result in the mode designated by the CS bits 0: Designated mode status not realized (unrealized) 1: Designated mode status realized Rev. 5.00 Dec 12, 2005 page 36 of 1034 REJ09B0254-0500 Section 2 CPU 16 bit 16 bit 8 bit MOVX.W MOVY.W MOVS.W, MOVS.L 31 39 32 A0G A1G DSR 7 0 32 bit 16 A0 A1 M0 M1 X0 X1 Y0 Y1 LDB XDB YDB MOVS.W, MOVS.L 0 Figure 2.8 Connections of DSP Registers and Buses The DSP unit has DSP status register (DSR). The DSR has conditions of the DSP data operation result (zero, negative, and so on) and a DC bit which is similar to the T bit in the CPU. The DC bit indicates the one of the conditional flags. A conditional DSP data processing instruction controls its execution based on the DC bit. This control affects only the operations in the DSP unit; it controls the update of DSP registers only. It cannot control operations in CPU, such as address register updating and load/store operations. The control bit CS[2:0] specifies the condition to be reflect to the DC bit. The unconditional DSP type data operations, except PMULS, MOVX, MOVY and MOVS, update the conditional flags and DC bit, but no CPU instructions, including MAC instructions, update the DC bit. The conditional DSP type instructions do not update the DSR either. DSR is assigned as a system register and load/store instructions are prepared as follows: STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; When DSR is read by the STS instructions, the upper bits (bit 31 to bit 8) are all 0. Rev. 5.00 Dec 12, 2005 page 37 of 1034 REJ09B0254-0500 Section 2 CPU 2.2 2.2.1 Data Format Data Format in Registers (Non-DSP Type) Register operands are always longwords (32 bits) (figure 2.9). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 Longword 0 Figure 2.9 Longword Operand 2.2.2 DSP-Type Data Format The SH7727 has several different data formats that depend on operations. This section explains the data formats for DSP type instructions. Figure 2.10 shows three DSP-type data formats with different binary point positions. A CPU-type data format with the binary point to the right of bit 0 is also shown for reference. The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSPtype integer format has the binary point between bit 16 and bit 15. The DSP-type logical format does not have a binary point. The valid data lengths of the data formats depend on the operations and the DSP registers. Rev. 5.00 Dec 12, 2005 page 38 of 1034 REJ09B0254-0500 Section 2 CPU DSP type fixed point 39 With guard bits S 31 30 Without guard bits 39 Multiplier input S 31 30 S 16 15 0 -1 to +1 - 2-15 0 -1 to +1 - 2-31 31 30 0 -28 to +28 - 2-31 DSP type integer 39 With guard bits S 31 Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) S 31 22 S 31 21 16 15 S 0 -16 to +16 16 15 0 -32 to +32 16 15 0 -215 to +215 - 1 32 31 16 15 0 -223 to +223 - 1 39 DSP type logical 31 16 15 0 CPU type integer Longword 31 S 0 -231 to +231 - 1 S: Sign bit : Binary point : Does not affect the operations Figure 2.10 Data Format Shift amount for arithmetic shift (PSHA) instruction has 7 bits filed that could represent -64 to +63, however -32 to +32 is the valid number for the operation. Also the shift amount for logical shift operation has 6-bits field, however -16 to +16 is the valid number for the instruction. Rev. 5.00 Dec 12, 2005 page 39 of 1034 REJ09B0254-0500 Section 2 CPU 2.2.3 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if the word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed. In such cases, the data accessed cannot be guaranteed (figure 2.11). Address A + 1 Address A 31 Address A Address A + 4 Address A + 8 Byte 0 23 Byte 1 Address A + 3 Address A + 11 Address A + 9 Address A + 8 7 0 Byte 0 Address A + 8 Address A + 4 Address A Address A + 2 15 Byte 2 7 0 Byte 3 31 Address A + 10 23 Byte 2 15 Byte 3 Byte 1 Word 0 Longword Word 1 Word 1 Longword Word 0 Big-endian mode Little-endian mode Figure 2.11 Byte, Word, and Longword Alignment As the data format, either big endian or little endian byte order can be selected, according to the MD5 pin at reset. When MD5 is low at reset, the processor operates in big endian. When MD5 is high at reset, the processor operates in little endian. 2.3 Features of CPU Core Instructions The CPU core instructions are RISC-type instructions with the following features: Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code efficiency. One Instruction per State: Pipelining is used, and basic instructions can be executed in one state. At 160-MHz operation, one state is 6.25 ns. Data Size: The basic data size for operations is longword. Byte, word, or longword can be selected as the memory access size. Memory byte or word data is sign-extended and operated on as longword data. Immediate data is sign-extended to longword size for arithmetic operations or zero-extended to longword size for logical operations. Rev. 5.00 Dec 12, 2005 page 40 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.6 Word Data Sign Extension Description Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. Example of Other CPU ADD.W #H'1234,R0 SH7727 CPU MOV.W ADD ........ .DATA.W H'1234 @(disp,PC),R1 R1,R0 Note: Immediate data is referenced by @(disp,PC). Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly on memory. Delayed Branching: Unconditional branch instructions, etc., are executed as delayed branches. With a delayed branch instruction, the branch is made after execution of the instruction (called the slot instruction) immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. With a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution for register updating, etc., excluding the branch operation, is performed in delayed branch instruction delay slot instruction order. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.7 Delayed Branch Instructions Description ADD is executed before branch to TRGET. Example of Other CPU ADD.W R1,R0 BRA TRGET SH7727 CPU BRA ADD TRGET R1,R0 Multiply/Multiply-and-Accumulate Operations: A 16 x 16 32 multiply operation is executed in 1 to 3 states, and a 16 x 16 + 64 64 multiply-and-accumulate operation in 2 to 3 states. A 32 x 32 64 multiply operation and a 32 x 32 + 64 64 multiply-and-accumulate operation are each executed in 2 to 5 states. T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. Rev. 5.00 Dec 12, 2005 page 41 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.8 T Bit Description If R0 R1, the T bit is set. A branch is made to TRGET0 if R0 R1, or to TRGET1 if R0 < R1. The T bit is not set by ADD. If R0 = 0, the T bit is set. A branch is made if R0 = 0. Example of Other CPU CMP.W R1,R0 BGE BLT BEQ TRGET0 TRGET1 TRGET SH7727 CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET SUB.W #1,R0 Immediate Data: Byte immediate data is placed inside the instruction code. Word and longword immediate data is not placed inside the instruction code, but in a table in memory. The table in memory is referenced with an immediate data transfer instruction (MOV) using PC-relative addressing mode with displacement. Table 2.9 Type 8-bit immediate 16-bit immediate Immediate Data Referencing SH7727 CPU MOV MOV.W #H'12,R0 @(disp,PC),R0 ........ .DATA.W H'1234 Example of Other CPU MOV.B MOV.W #H'12,R0 #H'1234,R0 32-bit immediate MOV.L @(disp,PC),R0 ........ MOV.L #H'12345678,R0 .DATA.L H'12345678 Note: Immediate data is referenced by @(disp,PC). Rev. 5.00 Dec 12, 2005 page 42 of 1034 REJ09B0254-0500 Section 2 CPU Absolute Addresses: When data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using register indirect addressing mode. Table 2.10 Absolute Address Referencing Type Absolute address SH7727 CPU MOV.L MOV.B @(disp,PC),R1 @R1,R0 ........ .DATA.L H'12345678 Example of Other CPU MOV.B @H'12345678,R0 16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode. Table 2.11 Displacement Referencing Type 16-bit displacement SH7727 CPU MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 Example of Other CPU MOV.W @(H'1234,R1),R2 ........ .DATA.W H'1234 Rev. 5.00 Dec 12, 2005 page 43 of 1034 REJ09B0254-0500 Section 2 CPU 2.4 2.4.1 Instruction Formats CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions Addressing Mode Register direct Register indirect Register indirect with postincrement Instruction Format Rn @Rn Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Calculation Formula -- Rn @Rn+ Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn + 1/2/4 1/2/4 + Rn Rn After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) Register indirect with predecrement @-Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4 Rev. 5.00 Dec 12, 2005 page 44 of 1034 REJ09B0254-0500 Section 2 CPU Addressing Mode Instruction Format Calculation Formula Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 Effective Address Calculation Method Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Register @(disp:4, Rn) indirect with displacement Indexed register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn + R0 Rn + R0 Rn + R0 GBR indirect @(disp:8, with GBR) displacement Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 Rev. 5.00 Dec 12, 2005 page 45 of 1034 REJ09B0254-0500 Section 2 CPU Addressing Mode Instruction Format Calculation Formula GBR + R0 Effective Address Calculation Method Effective address is sum of register GBR and R0 contents. GBR + R0 GBR + R0 Indexed GBR @(R0, GBR) indirect PC-relative @(disp:8, PC) Effective address is PC with 8-bit displacement with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC & H'FFFFFFFC + disp (zero-extended) x 2/4 *: With longword operand * PC + disp x 2 or PC&H'FFFFFFFC + disp x 4 Word: PC + disp x 2 Longword: PC&H'FFFFFFFC + disp x 4 Rev. 5.00 Dec 12, 2005 page 46 of 1034 REJ09B0254-0500 Section 2 CPU Addressing Mode PC-relative Instruction Format disp:8 Calculation Formula PC + disp x 2 Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) x 2 + PC + disp x 2 disp:12 Effective address is PC with 12-bit displacement PC + disp x 2 disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) x 2 + PC + disp x 2 Rn Effective address is sum of PC and Rn. PC + Rn PC + Rn PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. -- -- -- Rev. 5.00 Dec 12, 2005 page 47 of 1034 REJ09B0254-0500 Section 2 CPU 2.4.2 DSP Data Addressing Two different memory accesses are made with DSP instructions. The two kinds of instructions are X and Y data transfer instructions (MOVX.W, MOVY.W) and single data transfer instructions (MOVS.W, MOVSL). The data addressing is different for these two kinds of instruction. An overview of the data transfer instructions is given in table 2.13. Table 2.13 Overview of Data Transfer Instructions X/Y Data Transfer Processing (MOVX.W, MOVY.W) Address register Index register Addressing Ax: R4, R5, Ay: R6, R7 Ix: R8, Iy: R9 Nop/Inc (+2)/index addition: post-increment -- Modulo addressing Data bus Data length Bus contention Memory Source register Destination register Possible XDB, YDB 16 bits (word) No X/Y data memory Dx, Dy: A0, A1 Dx: X0/X1, Dy: Y0/Y1 Single Data Transfer Processing (MOVS.W, MOVS.L) As: R2, R3, R4, R5 Is: R8 Nop/Inc (+2, +4)/index addition: post-increment Dec (-2, -4): pre-decrement Not possible LDB 16/32 bits (word/longword) Yes Entire memory space Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G X/Y Data Addressing: With DSP instructions, the X and Y data memory can be accessed simultaneously using the MOVX.W and MOVY.W instructions. Two address pointers are provided for DSP instructions to enable simultaneous access to X and Y data memory. Only pointer addressing can be used with DSP instructions; immediate addressing is not available. Address registers are divided into two, with register R4 or R5 functioning as the X memory address register (Ax), and register R6 or R7 as the Y memory address register (Ay). The following three kinds of addressing can be used with X and Y data transfer instructions. 1. Non-update address register addressing: The Ax and Ay registers are address pointers. They are not updated. Rev. 5.00 Dec 12, 2005 page 48 of 1034 REJ09B0254-0500 Section 2 CPU 2. Addition index register addressing: The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy register is added to each (post-increment). 3. Increment address register addressing: The Ax and Ay registers are address pointers. After a data transfer, they are each incremented by 2 (post- increment). There is an index register for each address pointer. The R8 register is the index register (Ix) for the X memory address register (Ax), and the R9 register is the index register (Iy) for the Y memory address register (Ay). The X and Y data transfer instructions perform word-length processing, and use 16-bit access to the X/Y data memory. A value of 2 is therefore added to the address register in the increment processing. To perform decrementing, -2 is set in the index register and addition index register addressing is specified. In X/Y data addressing, only bits 1 to 15 of the address pointer are valid. When using X/Y data addressing, 0 must always be written to bit 0 of the address pointer and index register. X/Y data transfer addressing is shown in figure 2.12. When accessing X and Y memory using the X and Y buses, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of @AY+ or @Ay + Iy is stored in the lower word of Ay, while the upper word retains its original value. R8[Ix] +2 (INC) +0 (no update) R4[Ax] R5[Ax] R9[Iy] +2 (INC) +0 (no update) R6[Ay] R7[Ay] ALU AU Note: Three address processing methods: 1. Increment 2. Index register addition (Ix/Iy) 3. No increment AU: Adder provided for DSP addressing Post-updating is used in all cases. The address pointer can be decremented by setting -2/-4 in the index register. Figure 2.12 X and Y Data Transfer Addressing Rev. 5.00 Dec 12, 2005 page 49 of 1034 REJ09B0254-0500 Section 2 CPU Single Data Addressing: DSP instructions include two single data transfer instructions (MOVS.W, MOVS.L) that load data into, or store data from, a DSP register. With these instructions, one of registers R2 to R5 is used as the single data transfer address register (As). The following four kinds of addressing can be used with single data transfer instructions. 1. Non-update address register addressing: The As register is an address pointer. It is not updated. 2. Addition index register addressing: The As register is an address pointer. After a data transfer, the value of the Is register is added to the As register (post-increment). 3. Increment address register addressing: The As register is an address pointer. After a data transfer, the As register is incremented by 2 or 4 (post-increment). 4. Decrement address register addressing: The As register is an address pointer. Before a data transfer, -2 or -4 is added to the As register (i.e. 2 or 4 is subtracted) (pre-decrement). The R8 register is the index register (Is) for the address pointer (As). Single data transfer addressing is shown in figure 2.13. 31 R2[As] 31 R8[Is] -2/-4 (DEC) +2/+4 (INC) +0 (no update) ALU 0 R3[As] R4[As] R5[As] 0 MAB 31 CAB 0 Note: Four address processing methods: 1. 2. 3. 4. No update Index register addition (Is) Increment Decrement Post-increment Pre-decrement Figure 2.13 Single Data Transfer Addressing Rev. 5.00 Dec 12, 2005 page 50 of 1034 REJ09B0254-0500 Section 2 CPU Modulo Addressing: Like other DSPs, the SH7727 has a modulo addressing mode. Address registers are updated in the same way in this mode. When the address pointer value reaches the preset modulo end address, the address pointer value becomes the modulo start address. Modulo addressing is only available for the X and Y data transfer instructions (MOVX.W, MOVY.W). Modulo addressing mode is specified for the X address register by setting the DMX bit in the SR register, and for the Y address register by setting the DMY bit. Modulo addressing is valid for either the X or the Y address register, only; it cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set simultaneously (if they are, the DMY setting will be valid). The MOD register is provided to set the start and end addresses of the modulo address area. The MOD register contains MS (Modulo Start) and ME (Modulo End). An example of the use of the MOD register (MS and ME fields) is shown below. MOV.L ModAddr,Rn; LDC Rn,MOD; ModAddr: .DATA.W .DATA.W Rn=ModEnd, ModStart ME=ModEnd, MS=ModStart mEnd; ModEnd mStart; ModStart ModStart: .DATA : ModEnd: .DATA The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1. The address register contents are compared with ME, and if they match, start address MS is stored in the address register. The lower 16 bits of the address register are compared with ME. The maximum modulo size is 64 kbytes. This is sufficient to access the X and Y data memory. A block diagram of modulo addressing is shown in figure 2.14. Rev. 5.00 Dec 12, 2005 page 51 of 1034 REJ09B0254-0500 Section 2 CPU Instruction (MOVX/MOVY) 31 31 R8[Ix] +2 +0 0 16 15 R4[Ax] R5[Ax] 0 DMX DMY 31 16 15 R6[Ay] R7[Ay] 0 31 R9[Iy] +2 +0 0 CONT 15 MS 1 ALU CMP ABx 15 XAB 1 15 ME 1 15 YAB ABy 1 AU Figure 2.14 Modulo Addressing An example of modulo addressing is given below. MS = H'7008; ME=H'700C; R4=H'A5007008; DMX = 1; DMY = 0: (Modulo addressing setting for address register Ax (R4, R5)) As a result of the above settings, the R4 register changes as follows. R4: H'A5007008 Inc. Inc. Inc. R4: H'A500700A R4: H'A500700C R4: H'A5007008 (Reaches modulo end address, so becomes modulo start address) Place the data so that the upper 16 bits of the modulo start and end addresses are the same. This is because the modulo start address overwrites only the lower 15 bits of the address register, excluding bit 0. Note: When addition indexing is used for DSP data addressing, the address pointer may exceed the ME value without actually reaching it. In this case, the address pointer will not return to the modulo start address. Not only with modulo addressing, but when X and Y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, MS, and ME. Rev. 5.00 Dec 12, 2005 page 52 of 1034 REJ09B0254-0500 Section 2 CPU DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX), including modulo addressing, are shown below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy. The addresses to be used have not been updated */ /* Ax is one of R4,R5 */ if ( DMX==0 || DMX==1 && DMY == 1 )} Ax=Ax+(+2 or R8[Ix] or +0); /* Inc,Index,Not-Update */ else if (! not-update) Ax=modulo( Ax, (+2 or R8[Ix]) ); /* Ay is one of R6,R7 */ if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0); /* Inc,Index,Not-Update */ else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) ); } else if ( Operation is MOVS.W or MOVS.L ) { if ( Addressing is Nop, Inc, Add-index-reg ) { MAB=As; /* memory access cycle uses MAB. The address to be used has not been updated */ /* As is one of R2 to R5 */ As=As+(+2 or +4 or R8[Is] or +0); /* Inc,Index,Not-Update */ else { /* Decrement, Pre-update */ /* As is one of R2 to R5 */ As=As+(-2 or -4); MAB=As; /* memory access cycle uses MAB. The address to be used has been updated */ } Rev. 5.00 Dec 12, 2005 page 53 of 1034 REJ09B0254-0500 Section 2 CPU /* The value to be added to the address register depends on addressing operations. For example, (+2 or R8[Ix] or +0) means that +2 : if operation is increment R8[Ix] : if operation is add-index-reg +0 : if operation is not-update */ function modulo ( AddrReg, Index ) { if ( AdrReg[15:0]==ME ) AdrReg[15:0]==MS; else AdrReg=AdrReg+Index; return AddrReg; } 2.4.3 CPU Instruction Formats Table 2.14 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: mmmm: nnnn: iiii: dddd: Instruction code Source register Destination register Immediate data Displacement Rev. 5.00 Dec 12, 2005 page 54 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.14 CPU Instruction Formats Instruction Format 0 type 15 xxxx xxxx xxxx xxxx 0 Source Operand -- Destination Operand -- Sample Instruction NOP n type 15 xxxx nnnn xxxx xxxx 0 -- nnnn: register direct MOVT STS Rn MACH,Rn SR,@-Rn Control register or nnnn: register system register direct Control register or nnnn: preSTC.L system register decrement register indirect m type 15 xxxx mmmm xxxx xxxx 0 mmmm: register direct Control register or LDC system register Rm,SR @Rm+,SR mmmm: postControl register or LDC.L increment register system register indirect mmmm: register indirect PC-relative using Rm -- -- JMP BRAF @Rm Rm Rev. 5.00 Dec 12, 2005 page 55 of 1034 REJ09B0254-0500 Section 2 CPU Source Operand mmmm: register direct mmmm: register indirect Destination Operand nnnn: register direct nnnn: register indirect Instruction Format nm type 15 xxxx nnnn mmmm xxxx 0 Sample Instruction ADD Rm,Rn MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) nnnn: * postincrement register indirect (multiplyand-accumulate operation) mmmm: postincrement register indirect mmmm: register direct mmmm: register direct md type 15 xxxx xxxx mmmm dddd 0 nnnn: register direct MOV.L @Rm+,Rn nnnn: preMOV.L Rm,@-Rn decrement register indirect nnnn: indexed register indirect MOV.L Rm,@(R0,Rn) mmmmdddd: R0 (register direct) MOV.B @(disp,Rm),R0 register indirect with displacement R0 (register direct) nnnndddd: MOV.B R0,@(disp,Rn) register indirect with displacement nnnndddd: MOV.L Rm,@(disp,Rn) register indirect with displacement MOV.L @(disp,Rm),Rn nd4 type 15 xxxx xxxx nnnn dddd 0 nmd type 15 xxxx nnnn mmmm dddd 0 mmmm: register direct mmmmdddd: nnnn: register register indirect direct with displacement Rev. 5.00 Dec 12, 2005 page 56 of 1034 REJ09B0254-0500 Section 2 CPU Source Operand Destination Operand Instruction Format d type 15 xxxx xxxx dddd dddd 0 Sample Instruction dddddddd: R0 (register direct) MOV.L @@(disp,GBR),R0 GBR indirect with displacement R0 (register direct) dddddddd: PC-relative with displacement dddddddd: PC-relative dddddddd: GBR indirect with displacement MOV.L @R0,@(disp,GBR) R0 (register direct) MOVA @(disp,PC),R0 -- -- BF BRA label label (label=disp+PC) d12 type 15 xxxx dddd dddd dddd 0 dddddddddddd: PC-relative nd8 type 15 xxxx nnnn dddd dddd 0 dddddddd: PC-relative with displacement iiiiiiii: immediate iiiiiiii: immediate iiiiiiii: immediate nnnn: register direct MOV.L @(disp,PC),Rn i type 15 xxxx xxxx iiii iiii 0 Indexed GBR indirect AND.B #imm,@(R0,GBR) #imm,R0 R0 (register direct) AND -- nnnn: register direct TRAPA #imm ADD #imm,Rn ni type 15 xxxx nnnn iiii iiii 0 iiiiiiii: immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 5.00 Dec 12, 2005 page 57 of 1034 REJ09B0254-0500 Section 2 CPU 2.4.4 DSP Instruction Formats The SH7727 includes new instructions for digital signal processing. The new instructions are of the following two kinds. 1. Memory and DSP register double and single data transfer instructions (16-bit length) 2. Parallel processing instructions processed by the DSP unit (32-bit length) The instruction formats are shown in figure 2.15. 0 15 0000 . . . 1110 10 9 A field CPU core instructions 15 Double data transfer instructions 111100 15 Single data transfer instructions 0 10 9 A field 0 111101 31 26 25 16 15 A field B field 0 Parallel processing instructions 111110 Figure 2.15 DSP Instruction Formats Rev. 5.00 Dec 12, 2005 page 58 of 1034 REJ09B0254-0500 Section 2 CPU Double and Single Data Transfer Instructions: The format of double data transfer instructions is shown in table 2.15, and that of single data transfer instructions in table 2.16. Table 2.15 Double Data Transfer Instruction Formats Type data transfer Mnemonic MOVX.W @Ax,Dx MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data transfer MOVY.W @Ay,Dy MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay MOVY.W Da,@Ay+ MOVY.W Da,@Ay+Iy Note: Ax: Ay: Dx: Dy: Da: 0 = R4, 1 = R5 0 = R6, 1 = R7 0 = X0, 1 = X1 0 = Y0, 1 = Y1 0 = A0, 1 = A1 Da 1 1 1 1 1 0 0 0 Ay 0 Dy 0 0 Da 1 15 14 13 12 11 10 9 1 1 1 1 0 0 0 Ax 8 7 0 Dx 6 5 0 0 4 3 0 0 1 1 0 1 1 2 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 X memory NOPX Rev. 5.00 Dec 12, 2005 page 59 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.16 Single Data Transfer Instruction Formats Type Single data transfer Mnemonic MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Is Note: * Codes reserved for system use. 15 14 13 12 11 10 9 1 1 1 1 0 1 As 0:R4 1:R5 2:R2 3:R3 8 7 6 5 4 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 0 Ds 0:(*) 1:(*) 2:(*) 3:(*) 4:(*) 5:A1 6:(*) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:A1G E:M1 F:A0G Parallel Processing Instructions: Parallel processing instructions are provided for efficient execution of digital signal processing using the DSP unit. They are 32 bits long and allow four simultaneous processes, an ALU operation, multiplication, and two data transfers. Parallel processing instructions are divided into an A field and a B field. The A field defines data transfer instructions and the B field an ALU operation instruction and multiply instruction. These instructions can be defined independently, and the processing is executed in parallel, independently and simultaneously. A-field parallel data transfer instructions are shown in table 2.17, and B-field ALU operation instructions and multiply instructions in table 2.18. Rev. 5.00 Dec 12, 2005 page 60 of 1034 REJ09B0254-0500 Type 1111100 Ax B field 0 Dx 0 0 Mnemonic 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X memory data transfer Da 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 B field Y memory data transfer 111110 Da 1 NOPX MOVX.W @Ax, Dx MOVX.W @Ax+, Dx MOVX.W @Ax+Ix, Dx MOVX.W Da, @Ax MOVX.W Da, @Ax+ MOVX.W Da, @Ax+Ix NOPY MOVY.W @Ay, Dy MOVY.W @Ay+, Dy MOVY.W @Ay+Iy, Dy MOVY.W Da, @Ay MOVY.W Da, @Ay+ MOVY.W Da, @Ay+Iy 0 Ay 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 Dy Table 2.17 A-Field Parallel Data Transfer Instructions Note: Ax: Ay: Dx: Dy: Da: 0 = R4, 1 = R5 0 = R6, 1 = R7 0 = X0, 1 = X1 0 = Y0, 1 = Y1 0 = A0, 1 = A1 Rev. 5.00 Dec 12, 2005 page 61 of 1034 REJ09B0254-0500 Section 2 CPU Type 111110 Dz A field Dg 0:M0 1:M1 2:A0 3:A1 0 0 0 0 0 Du 0:X0 1:Y0 2:A0 3:A1 0 1 0 1 0:X0 1:X1 0 1 1 0 2:Y0 3:A1 0111 0:Y0 1:Y1 2:X0 3:A1 0:X0 1:X1 2:A0 3:A1 0000 0:Y0 1:Y1 2:M0 3:M1 0 0 0 0 1 0 0 0 -16 < = imm < = +16 0 1 0 -32 < = imm < = +32 1 0 1 00 Se Sf Sx Sy Mnemonic 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Section 2 CPU imm. shift PSHL #imm, Dz PSHA #imm, Dz Reserved 6-operand PMULS Se, Sf, Dg parallel instructions Reserved Rev. 5.00 Dec 12, 2005 page 62 of 1034 REJ09B0254-0500 Dz 01 10 100 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 11 3-operand instructions PSUB Sx, Sy, Du PMULS Se, Sf, Dg PADD Sx, Sy, Du PMULS Se, Sf, Dg Reserved Table 2.18 B-Field ALU Operation Instructions and Multiply Instructions PSUBC Sx, Sy, Dz PADDC Sx, Sy, Dz PCMP Sx, Sy Reserved Reserved Reserved PABS Sx, Dz PRND Sx, Dz PABS Sy, Dz PRND Sy, Dz Reserved 0:(*1) 1:(*1) 2:(*1) 3:(*1) 4:(*1) 5:A1 6:(*1) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:(*1) E:M1 F:(*1) Note: 1. Codes reserved for system use. Type 111110 Sx 0:Y0 1:Y1 2:M0 3:M1 Sy A field 0:X0 1:X1 01: 0 1 Uncon- 2:A0 ditional 3:A1 10: 1 0 DCT 0 0 if cc Dz Mnemonic 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11: 1 1 DCF 0:(*1) 1:(*1) 2:(*1) 3:(*1) 4:(*1) 5:A1 6:(*1) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:(*1) E:M1 F:(*1) 10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 110 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 11 00 if cc Conditional [if cc] PSHL Sx, Sy, Dz 3-operand [if cc] PSHA Sx, Sy, Dz instructions [if cc] PSUB Sx, Sy, Dz [if cc] PADD Sx, Sy, Dz Reserved [if cc] PAND Sx, Sy, Dz [if cc] PXOR Sx, Sy, Dz [if cc] POR Sx, Sy, Dz [if cc] PDEC Sx, Dz [if cc] PINC Sx, Dz [if cc] PDEC Sy, Dz [if cc] PINC Sy, Dz [if cc] PCLR Dz [if cc] PDMSB Sx, Dz Reserved [if cc] PDMSB Sy, Dz [if cc] PNEG Sx, Dz [if cc] PCOPY Sx, Dz [if cc] PNEG Sy, Dz [if cc] PCOPY Sy, Dz Reserved [if cc] PSTS MACH, Dz [if cc] PSTS MACL, Dz [if cc] PLDS Dz, MACH [if cc] PLDS Dz, MACL (*2) Reserved 00 0* 111111 Reserved Rev. 5.00 Dec 12, 2005 page 63 of 1034 REJ09B0254-0500 Notes: 1. Codes reserved for system use. 2. [if cc]: DCT (DC bit True), DCF (DC bit False) or none (unconditional instruction) Section 2 CPU Section 2 CPU 2.5 2.5.1 Instruction Set CPU Instruction Set The SH-1/SH-2/SH-3 compatible instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.19. Tables 2.20 to 2.25 show the instruction notation, machine code, execution time, and function. Rev. 5.00 Dec 12, 2005 page 64 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.19 CPU Instruction Types Type Kinds of Instruction Op Code MOV Function Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA MOVT SWAP XTRCT Arithmetic operation instructions 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Effective address transfer T bit transfer Upper/lower swap Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Signed division initialization Unsigned division initialization Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, doubleprecision multiply-and-accumulate Double-precision multiplication (32 x 32 bits) Signed multiplication (16 x 16 bits) Unsigned multiplication (16 x 16 bits) Sign inversion Sign inversion with borrow Binary subtraction Binary subtraction with carry Binary subtraction with underflow 33 Number of Instructions 39 Data transfer 5 instructions Rev. 5.00 Dec 12, 2005 page 65 of 1034 REJ09B0254-0500 Section 2 CPU Kinds of Instruction Op Code 6 AND NOT OR TAS TST XOR Shift instructions 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD Branch instructions 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Number of Instructions 14 Type Logic operation instructions Function Logical AND Bit inversion Logical OR Memory test and bit setting Logical AND and T bit setting Exclusive logical OR 1-bit left shift 1-bit right shift 1-bit left shift with T bit 1-bit right shift with T bit Arithmetic 1-bit left shift Arithmetic 1-bit right shift Logical 1-bit left shift Logical n-bit left shift Logical 1-bit right shift Logical n-bit right shift Arithmetic dynamic shift Logical dynamic shift Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 16 11 Rev. 5.00 Dec 12, 2005 page 66 of 1034 REJ09B0254-0500 Section 2 CPU Kinds of Instruction Op Code 15 CLRT CLRMAC CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA Total: 68 Number of Instructions 75 Type System control instructions Function T bit clear MAC register clear S bit clear Load into control register Load into system register PTEH/PTEL load into TLB No operation Data prefetch to cache Return from exception handling S bit setting T bit setting Transition to power-down mode Store from control register Store from system register Trap exception handling 189 Rev. 5.00 Dec 12, 2005 page 67 of 1034 REJ09B0254-0500 Section 2 CPU The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Instruction Indicated by mnemonic. Instruction Code Indicated in MSB LSB order. Operation Indicates summary of operation. Privilege Indicates a privileged instruction. Execution T Bit States Value when no wait states are inserted.*1 Value of T bit after instruction is executed. Explanation of Symbols --: No change Explanation of Symbols OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Rn: Source register Destination register Explanation of Symbols mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: dddd: Immediate data Displacement *2 Explanation of Symbols , : (xx): Transfer direction Memory operand M/Q/T: Flag bits in the SR &: |: ^: ~: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit imm: Immediate data disp: Displacement < Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following: (1) When there is contention between an instruction fetch and a data access (2) When the destination register of a load instruction (memory register) is also used by the following instruction 2. Scaled (x1, x2, or x4) according to the instruction operand size, etc. Rev. 5.00 Dec 12, 2005 page 68 of 1034 REJ09B0254-0500 Section 2 CPU Data Transfer Instructions Table 2.20 Data Transfer Instructions Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Operation imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn, Rm + 1 Rm (Rm) Sign extension Rn, Rm + 2 Rm Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Rm) Rn,Rm + 4 Rm 0110nnnnmmmm0110 R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 Rev. 5.00 Dec 12, 2005 page 69 of 1034 REJ09B0254-0500 Section 2 CPU Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Operation Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 R0,@(disp,GBR) R0 (disp + GBR) R0,@(disp,GBR) R0 (disp x 2 + GBR) R0,@(disp,GBR) R0 (disp x 4 + GBR) @(disp,GBR),R0 (disp + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 2 + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 4 + GBR) R0 @(disp,PC),R0 Rn disp x 4 + PC R0 T Rn Rm Swap the bottom two bytes REG Rm Swap two consecutive words Rn Rm: Middle 32 bits of Rn Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev. 5.00 Dec 12, 2005 page 70 of 1034 REJ09B0254-0500 Section 2 CPU Arithmetic Operation Instructions Table 2.21 Arithmetic Operation Instructions Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PZ CMP/PL Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T If Rn Rm with unsigned data, 1 T If Rn Rm with signed data, 1 T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn 0, 1 T If Rn > 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 CMP/STR Rm,Rn DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn Rm,Rn 2 -- (to 5)*1 Rev. 5.00 Dec 12, 2005 page 71 of 1034 REJ09B0254-0500 Section 2 CPU Privileged Mode Cycles T Bit -- 2 -- (to 5)*1 1 1 1 1 1 Comparison result -- -- -- -- Instruction DMULU.L Rm,Rn Operation Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn, if Rn = 0, 1 T, else 0 T A byte in Rm is signextended Rn A word in Rm is signextended Rn A byte in Rm is zeroextended Rn A word in Rm is zeroextended Rn Code 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 -- -- -- -- -- -- EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L @Rm+,@Rn+ Signed operation of (Rn) 0000nnnnmmmm1111 x (Rm) + MAC MAC, Rn + 4 Rn, Rm + 4 Rm, 32 x 32 + 64 64 bits Signed operation of (Rn) 0100nnnnmmmm1111 x (Rm) + MAC MAC, Rn + 2 Rn, Rm + 2 Rm, 16 x 16 + 64 64 bits Rn x Rm MACL, 32 x 32 32 bits Signed operation of Rn x Rm MACL, 16 x 16 32 bits Unsigned operation of Rn x Rm MACL, 16 x 16 32 bits 0-Rm Rn 0-Rm-T Rn, Borrow T Rn-Rm Rn Rn-Rm-T Rn, Borrow T Rn-Rm Rn, Underflow T 0000nnnnmmmm0111 0010nnnnmmmm1111 2 -- (to 5)*1 MAC.W @Rm+,@Rn+ -- 2 -- (to 5)*1 MUL.L Rm,Rn -- -- 2 -- (to 5)*1 1 -- (to 3)*2 1 -- (to 3)*2 1 1 1 1 1 -- Borrow -- Borrow Underflow MULS.W Rm,Rn MULU.W Rm,Rn 0010nnnnmmmm1110 -- NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 -- -- -- -- -- Rev. 5.00 Dec 12, 2005 page 72 of 1034 REJ09B0254-0500 Section 2 CPU Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required when the operation result is read from the MAC register immediately after the instruction. 2. The normal minimum number of execution cycles is one, but three cycles are required when the operation result is read from the MAC register immediately after the MUL instruction. Logic Operation Instructions Table 2.22 Logic Operation Instructions Instruction AND AND Rm,Rn #imm,R0 Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR) Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 3 1 1 1 3 4 1 1 3 1 1 3 -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- -- AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) TAS.B @Rn* TST TST Rm,Rn #imm,R0 TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0 XOR.B #imm,@(R0,GBR) Note: * An on-chip DMAC bus cycle is not inserted between a TAS instruction operand read cycle and write cycle. Also, bus release is not performed by BREQ. Rev. 5.00 Dec 12, 2005 page 73 of 1034 REJ09B0254-0500 Section 2 CPU Shift Instructions Table 2.23 Shift Instructions Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn Operation T Rn MSB LSB Rn T T Rn T T Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Privileged Mode Cycles T Bit -- -- -- -- -- 1 1 1 1 1 MSB LSB MSB LSB -- SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 -- -- -- 1 1 1 MSB LSB -- SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 MSB LSB -- -- -- -- -- -- SHLL16 Rn SHLR16 Rn Rev. 5.00 Dec 12, 2005 page 74 of 1034 REJ09B0254-0500 Section 2 CPU Branch Instructions Table 2.24 Branch Instructions Instruction BF label Operation If T = 0, disp x 2 + PC PC; if T = 1, nop (where label is disp + PC) Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC Code 10001011dddddddd Privileged Mode -- Cycles 3/1* T Bit -- BF/S label 10001111dddddddd -- 2/1* -- BT label 10001001dddddddd -- 3/1* -- BT/S BRA BRAF BSR BSRF JMP JSR RTS label label Rm label Rm @Rm @Rm 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 -- -- -- -- -- -- -- -- 2/1* 2 2 2 2 2 2 2 -- -- -- -- -- -- -- -- Note: * One state when the branch is not executed. Rev. 5.00 Dec 12, 2005 page 75 of 1034 REJ09B0254-0500 Section 2 CPU System Control Instructions Table 2.25 System Control Instructions Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK Operation 0 MACH, MACL 0S 0T Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm R0_BANK Rm R1_BANK Rm R2_BANK Rm R3_BANK Rm R4_BANK Rm R5_BANK Rm R6_BANK Rm R7_BANK (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) R0_BANK, Rm + 4 Rm (Rm) R1_BANK, Rm + 4 Rm (Rm) R2_BANK, Rm + 4 Rm (Rm) R3_BANK, Rm + 4 Rm (Rm) R4_BANK, Rm + 4 Rm Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111 0100mmmm10010111 0100mmmm10100111 0100mmmm10110111 0100mmmm11000111 Privileged Mode Cycles T Bit -- -- -- 1 1 1 5 3 3 3 3 3 3 3 3 3 3 3 3 7 5 5 5 5 5 5 5 5 5 -- -- 0 LSB -- -- -- -- -- -- -- -- -- -- -- -- LSB -- -- -- -- -- -- -- -- -- -- -- LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R2_BANK LDC.L @Rm+, R3_BANK LDC.L @Rm+, R4_BANK Rev. 5.00 Dec 12, 2005 page 76 of 1034 REJ09B0254-0500 Section 2 CPU Privileged Mode Cycles T Bit Instruction LDC.L @Rm+, R5_BANK LDC.L @Rm+, R6_BANK LDC.L @Rm+, R7_BANK LDS LDS LDS Rm,MACH Rm,MACL Rm,PR Operation (Rm) R5_BANK, Rm + 4 Rm (Rm) R6_BANK, Rm + 4 Rm (Rm) R7_BANK, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm PTEH/PTEL TLB No operation (Rm) cache Delayed branch, SSR/SPC SR/PC 1S 1T Sleep Code 0100mmmm11010111 0100mmmm11100111 0100mmmm11110111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000000000001001 0000mmmm10000011 0000000000101011 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010 0000nnnn11000010 0000nnnn11010010 0000nnnn11100010 0000nnnn11110010 -- -- -- -- -- -- 5 5 5 1 1 1 1 1 1 1 1 2 4 1 1 4* 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR LDTLB NOP PREF RTE SETS SETT SLEEP STC STC STC STC STC STC STC STC STC STC STC STC STC SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn R4_BANK,Rn R5_BANK,Rn R6_BANK,Rn R7_BANK,Rn @Rm -- -- -- -- -- SR Rn GBR Rn VBR Rn SSR Rn SPC Rn R0_BANK Rn R1_BANK Rn R2_BANK Rn R3_BANK Rn R4_BANK Rn R5_BANK Rn R6_BANK Rn R7_BANK Rn Rev. 5.00 Dec 12, 2005 page 77 of 1034 REJ09B0254-0500 Section 2 CPU Privileged Mode Cycles T Bit Instruction STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn STC.L SPC,@-Rn STC.L R0_BANK, @-Rn STC.L R1_BANK, @-Rn STC.L R2_BANK, @-Rn STC.L R3_BANK, @-Rn STC.L R4_BANK, @-Rn STC.L R5_BANK, @-Rn STC.L R6_BANK, @-Rn STC.L R7_BANK, @-Rn STS STS STS MACH,Rn MACL,Rn PR,Rn Operation Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) Rn-4 Rn, SSR (Rn) Rn-4 Rn, SPC (Rn) Rn-4 Rn, R0_BANK (Rn) Rn-4 Rn, R1_BANK (Rn) Rn-4 Rn, R2_BANK (Rn) Rn-4 Rn, R3_BANK (Rn) Rn-4 Rn, R4_BANK (Rn) Rn-4 Rn, R5_BANK (Rn) Rn-4 Rn, R6_BANK (Rn) Rn-4 Rn, R7_BANK (Rn) MACH Rn MACL Rn PR Rn Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC SPC, SR SSR, imm << 2 TRA, VBR + H'0100 PC Code 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn10000011 0100nnnn10010011 0100nnnn10100011 0100nnnn10110011 0100nnnn11000011 0100nnnn11010011 0100nnnn11100011 0100nnnn11110011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii -- 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn TRAPA #imm Note: * Number of states before the chip enters the sleep state. The table shows the minimum number of clocks required for execution. In practice, the number of execution cycles will be increased if there is contention between an instruction fetch and a data access, or if the destination register of a load instruction (memory register) is also used by the following instruction. Rev. 5.00 Dec 12, 2005 page 78 of 1034 REJ09B0254-0500 Section 2 CPU 2.6 2.6.1 DSP Extended-Function Instructions Introduction The newly added instructions are classified into the following three groups: 1. Additional system control instructions for the CPU unit 2. DSP unit memory-register single and double data transfer 3. DSP unit parallel processing Group 1 instructions are provided to support loop control and data transfer between CPU core registers or memory and new control registers added to the CPU core. DSP operations employ a multi-level nested-loop structure. With a single-level loop, use of the decrement and test, DTRn, and conditional delayed branch BF/S instructions supported by the SH-3 is adequate. However, with nested loops, DSP performance can be improved by means of a zero-overhead loop control function. The RS, RE, and MOD registers have been added to support loop control and modulo addressing functions. Instructions are supported for data transfer between these new control registers and general registers or memory. In addition, the LDRS and LDRE address calculation registers have been added to reduce the code size for the initial settings for zero-overhead loop control. An independent control register, DSR, is provided for the DSP engine. This register is treated as a system register such as MACL and MACH. The A0, X0, X1, Y0, and Y1 registers are treated as system registers from the CPU side, and LDS/STS instructions are supported for the same purpose. Table 2.26 shows the instruction code map for the new system control instructions for the CPU core. Group 2 instructions are provided to reduce DSP operation program code size. Data transfer instructions that perform no data processing are frequently executed by the DSP engine. In this case, a 32-bit instruction code is unnecessarily long, and wastes space in the program memory area. All instructions in this class have a 16-bit code length, the same as conventional SH core instructions. Single data transfer instructions have greater flexibility in terms of operands than the double data transfer instruction or parallel instruction class. Group 3 instructions are provided for fast execution of digital signal processing operations using the DSP unit. These instructions have a 32-bit instruction code, so that a maximum of four instructions--an ALU operation, multiplication, and two data transfer instructions--can be executed in parallel. Rev. 5.00 Dec 12, 2005 page 79 of 1034 REJ09B0254-0500 Section 2 CPU 2.6.2 Added CPU System Control Instructions The new instructions in this class are treated as part of the CPU core functions, and therefore all the added instructions have a 16-bit code length. All the additional instructions belong to the system control instruction group. Table 2.26 summarizes the added system instructions. New control registers--RS, RE, and MOD--have been added to the CPU core to support loop control and modulo addressing functions, and LDC and STS type instructions have been provided for these registers. The DSP engine's DSR, A0, X0, X1, Y0, and Y1 registers are treated as system registers such as MACH and MACL, and therefore STS and LDS instructions are supported for these registers. As digital signal processing operations usually employ a multi-level nested-loop structure, DSP performance can be improved by means of a zero-overhead loop control function. SETRC type instructions are provided to set the repeat count in the RC field in SR[27:16]. When an immediate operand type SETRC instruction is executed, the 8-bit immediate operand data is set in SR[23:16], and 0 is set in the remaining bits, SR[27:24]. When a register operand type SETRC instruction is executed, Rn[11:0] is set in SR[27:16]. The start address and end address of the repeat loop are set in the RS register and RE register. There are two ways of setting the addresses: by using an LDC type instruction, or by using the LDRS and LDRE instructions. Rev. 5.00 Dec 12, 2005 page 80 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.26 Added CPU System Control Instructions Execution States 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 5 5 Instruction SETRC #imm SETRC Rn LDRS LDRE STC STC STC STS STS STS STS STS STS @(disp,PC) @(disp,PC) MOD,Rn RS,Rn RE,Rn DSR,Rn A0,Rn X0,Rn X1,Rn Y0,Rn Y1,Rn Instruction Code 10000010iiiiiiii 0100nnnn00010100 10001100dddddddd 10001110dddddddd 0000nnnn01010010 0000nnnn01100010 0000nnnn01110010 0000nnnn01101010 0000nnnn01111010 0000nnnn10001010 0000nnnn10011010 0000nnnn10101010 0000nnnn10111010 0100nnnn01100010 0100nnnn01110010 0100nnnn10000010 0100nnnn10010010 0100nnnn10100010 0100nnnn10110010 0100nnnn01010011 0100nnnn01100011 0100nnnn01110011 0100nnnn01100110 0100nnnn01110110 0100nnnn10000110 0100nnnn10010110 0100nnnn10100110 0100nnnn10110110 0100nnnn01010111 0100nnnn01100111 Operation imm RC (of SR) Rn[11:0] R C (of SR) (disp x 2 + PC) RS (disp x 2 + PC) RE MOD Rn RS Rn RE Rn DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Rn Rn - 4 Rn, DSR (Rn) Rn - 4 Rn, A0 (Rn) Rn - 4 Rn, X0 (Rn) Rn - 4 Rn, X1 (Rn) Rn - 4 Rn, Y0 (Rn) Rn - 4 Rn, Y1 (Rn) Rn - 4 Rn, MOD (Rn) Rn - 4 Rn, RS (Rn) Rn - 4 Rn, RE (Rn) (Rn) DSR, Rn + 4 Rn (Rn) A0, Rn + 4 Rn (Rn) X0, Rn + 4 Rn (Rn) X1, Rn + 4 Rn (Rn) Y0, Rn + 4 Rn (Rn) Y1, Rn + 4 Rn (Rn) MOD, Rn + 4 Rn (Rn) RS, Rn + 4 Rn T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STS.L DSR,@-Rn STS.L A0,@-Rn STS.L X0,@-Rn STS.L X1,@-Rn STS.L Y0,@-Rn STS.L Y1,@-Rn STC.L MOD,@-Rn STC.L RS,@-Rn STC.L RE,@-Rn LDS.L @Rn+,DSR LDS.L @Rn+,A0 LDS.L @Rn+,X0 LDS.L @Rn+,X1 LDS.L @Rn+,Y0 LDS.L @Rn+,Y1 LDC.L @Rn+,MOD LDC.L @Rn+,RS Rev. 5.00 Dec 12, 2005 page 81 of 1034 REJ09B0254-0500 Section 2 CPU Execution States 5 1 1 1 1 1 1 3 3 3 Instruction LDC.L @Rn+,RE LDS LDS LDS LDS LDS LDS LDC LDC LDC Rn,DSR Rn,A0 Rn,X0 Rn,X1 Rn,Y0 Rn,Y1 Rn,MOD Rn,RS Rn,RE Instruction Code 0100nnnn01110111 0100nnnn01101010 0100nnnn01111010 0100nnnn10001010 0100nnnn10011010 0100nnnn10101010 0100nnnn10111010 0100nnnn01011110 0100nnnn01101110 0100nnnn01111110 Operation (Rn) RE, Rn + 4 Rn Rn DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Rn MOD Rn RS Rn RE T Bit -- -- -- -- -- -- -- -- -- -- 2.6.3 Single and Double Data Transfer for DSP Data Instructions The new instructions in this class are provided to reduce the program code size for DSP operations. All the new instructions in this class have a 16-bit code length. Instructions in this class are divided into two groups: single data transfer instructions and double data transfer instructions. The operand flexibility of the double data transfer instructions is the same as with the A field in parallel instruction class data transfer instructions described in section 2.6.4, DSP Operation Instruction Set. However, conditional load instructions cannot be used with these 16-bit instructions. In single transfer, the Ax pointer and two other pointers are used as the As pointer, but the Ay pointer is not used. Tables 2.27 and 2.28 list the single and double data transfer instructions. With double data transfer group instructions, X memory and Y memory can be accessed in parallel. The Ax pointer can only be used by X memory access instructions, and the Ay pointer only by Y memory access instructions. Double data transfer instructions can only access the onchip X and Y memory areas. Single data transfer instructions use a 16-bit instruction code, and can access any memory address space. Rn (n = 2 to 7) registers are normally used as the Ax, Ay, and As pointers. The pointer names themselves can be changed with the assembler rename function. The following renaming scheme is recommended. R2:As2, R3:As3, R4:Ax0 (As0), R5:Ax1 (As1), R6:Ay0, R7:Ay1, R8:Ix, R9:Iy Rev. 5.00 Dec 12, 2005 page 82 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.27 Double Data Transfer Instructions Execution States DC 1 1 1 -- -- -- Instruction X memory NOPX data transfer MOVX.W @Ax,Dx MOVX.W @Ax+,Dx Instruction Code 1111000*0*0*00** 111100A*D*0*01** 111100A*D*0*10** Operation X memory no access (Ax) MSW of Dx, 0 LSW of Dx (Ax) MSW of Dx, 0 LSW of Dx, Ax + 2 Ax (Ax) MSW of Dx, 0 LSW of Dx, Ax + Ix Ax MSW of Da (Ax) MSW of Da (Ax), Ax + 2 Ax MSW of Da (Ax), Ax + Ix Ax Y memory no access (Ay) MSW of Dy, 0 LSW of Dy (Ay) MSW of Dy, 0 LSW of Dy, Ay + 2 Ay (Ay) MSW of Dy, 0 LSW of Dy, Ay + Iy Ay MSW of Da (Ay) MSW of Da (Ay), Ay + 2 Ay MSW of Da (Ay), Ay + Iy Ay MOVX.W @Ax+Ix,Dx 111100A*D*0*11** 1 -- MOVX.W Da,@Ax MOVX.W Da,@Ax+ 111100A*D*1*01** 111100A*D*1*10** 1 1 1 1 1 1 -- -- -- -- -- -- MOVX.W Da,@Ax+Ix 111100A*D*1*11** Y memory NOPY data transfer MOVY.W @Ay,Dy MOVY.W @Ay+,Dy 111100*0*0*0**00 111100*A*D*0**01 111100*A*D*0**10 MOVY.W @Ay+Iy,Dy 111100*A*D*0**11 1 -- MOVY.W Da,@Ay MOVY.W Da,@Ay+ 111100*A*D*1**01 111100*A*D*1**10 1 1 1 -- -- -- MOVY.W Da,@Ay+Iy 111100*A*D*1**11 Rev. 5.00 Dec 12, 2005 page 83 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.28 Single Data Transfer Instructions Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Ix,Ds MOVS.W Ds,@-As* MOVS.W Ds,@As* MOVS.W Ds,@As+* Instruction Code 111101AADDDD0000 111101AADDDD0100 111101AADDDD1000 111101AADDDD1100 111101AADDDD0001 111101AADDDD0101 111101AADDDD1001 Operation As - 2 As, (As) MSW of Ds, 0 LSW of Ds (As) MSW of Ds, 0 LSW of Ds (As) MSW of Ds, 0 LSW of Ds, As + 2 As (Asc) MSW of Ds, 0 LSW of Ds, As + Ix As As - 2 As, MSW of Ds (As) MSW of Ds (As) MSW of Ds (As), As + 2 As MSW of Ds (As), As + Ix As As - 4 As, (As) Ds (As) Ds (As) Ds, As + 4 As (As) Ds, As + Ix As As - 4 As, Ds (As) Ds (As) Ds (As), As + 4 As Ds (As), As + Ix As DC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOVS.W Ds,@As+Ix* 111101AADDDD1101 MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Ix,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Ix 111101AADDDD0010 111101AADDDD0110 111101AADDDD1010 111101AADDDD1110 111101AADDDD0011 111101AADDDD0111 111101AADDDD1011 111101AADDDD1111 Note: * If guard bit registers A0G and A1G are specified in source operand Ds, the data is output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8]. Rev. 5.00 Dec 12, 2005 page 84 of 1034 REJ09B0254-0500 Section 2 CPU The correspondence between DSP data transfer operands and registers is shown in table 2.29. CPU core registers are used as a pointer address that indicates a memory address. Table 2.29 Correspondence between DSP Data Transfer Operands and Registers Register CPU register R0 R1 R2 (As2) R3 (As3) R4 (Ax0) R5 (Ax1) R6 (Ay0) R7 (Ay1) R8 (Ix) R9 (Iy) DSP register A0 A1 M0 M1 X0 X1 Y0 Y1 A0G A1G Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Ax Ix Dx Ay Iy Dy Da As Ds 2.6.4 DSP Operation Instruction Set DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into an A field and B field; a parallel data transfer instruction is specified in the A field, and a single or double data operation instruction in the B field. Instructions can be specified independently, and are also executed independently. The parallel data transfer instruction specified in the A field is exactly the same as a double data transfer instruction. The function of the A field--that is, the data transfer instruction field--is Rev. 5.00 Dec 12, 2005 page 85 of 1034 REJ09B0254-0500 Section 2 CPU basically the same as in the double data transfer instructions described in section 2.6.3, Single and Double Data Transfer for DSP Data Instructions, but has a special function in load instructions. B-field data operation instructions are of three kinds: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. The formats of the DSP operation instructions are shown in table 2.30. The respective operands are selected independently from the DSP registers. The correspondence between DSP operation instruction operands and registers is shown in table 2.31. Table 2.30 DSP Operation Instruction Formats Type Double data operation instructions Conditional single data operation instructions Instruction Formats ALUop. Sx, Sy, Du MLTop. Se, Df, Dg ALUop. Sx, Sy, Dz DCT DCF ALUop. Sx, Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz DCT DCF ALUop. Sx, Dz ALUop. Sx, Dz ALUop. Sy, Dz DCT DCF Unconditional single data operation instructions ALUop. Sy, Dz ALUop. Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz ALUop. Sy, Dz MLTop. Se, Sf, Dg Rev. 5.00 Dec 12, 2005 page 86 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.31 Correspondence between DSP Instruction Operands and Registers ALU/BPU Operations Register A0 A1 M0 M1 X0 X1 Y0 Y1 Yes Yes Yes Yes Sx Yes Yes Yes Yes Sy Dz Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes Yes Yes Se Multiply Operations Sf Dg Yes Yes Yes Yes When writing parallel instructions, the B-field instruction is written first, followed by the A-field instruction. A sample parallel processing program is shown in figure 2.16. PADD A0, M0, A0 DCF PINC X1, A1 PCMP X1, M0 PMULS X0, Y0, M0 MOVX.W @R4+, X0 MOVX.W A0, @R5+R8 MOVX.W @R4 MOVY.W @R6+, Y0 [;] MOVY.W @R7+, Y0 [;] [NOPY] [;] Figure 2.16 Sample Parallel Instruction Program Square brackets mean that the contents can be omitted. The no operation instructions NOPX and NOPY can be omitted. Table 2.32 gives an overview of the B field in parallel operation instructions. A semicolon is the instruction line delimiter, but this can also be omitted. If the semicolon delimiter is used, the area to the right of the semicolon can be used as a comment field. This has the same function as with conventional SH tools. The DSR register condition code bit (DC) is always updated on the basis of the result of an unconditional ALU or shift operation instruction. Conditional instructions do not update the DC bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means of bits CS0 to CS2 in the DSR register. The DC bit update rules are shown in table 2.33. Rev. 5.00 Dec 12, 2005 page 87 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.32 DSP Operation Instructions Execution States 1 1 1 1 1 1 1 1 1 1 Instruction Instruction Code Operation Se * Sf Dg (signed) Sx + Sy Du Se * Sf Dg (signed) Sy - Sy Du Se * Sf Dg (signed) Sx + Sy Dz If DC = 1, Sx + Sy Dz If DC = 0, nop If DC = 0, Sx + Sy Dz If DC = 1, nop Sx - Sy Dz If DC = 1, Sx - Sy Dz If DC = 0, nop If DC = 0, Sx - Sy Dz If DC = 1, nop If Sy > = 0, Sx << Sy Dz (arithmetic shift) If Sy<0, Sx>>Sy Dz If DC = 1 & Sy > = 0, Sx << Sy Dz (arithmetic shift) If DC = 1 & Sy < 0, Sx >> Sy Dz If DC = 0, nop DC -- * * * * * * * * * PMULS Se,Sf,Dg 111110********** 0100eeff0000gg00 PADD Sx,Sy,Du PMULS Se,Sf,Dg PSUB Sx,Sy,Du PMULS Se,Sf,Dg PADD Sx,Sy,Dz 111110********** 0111eeffxxyygguu 111110********** 0110eeffxxyygguu 111110********** 10110001xxyyzzzz DCT PADD Sx,Sy,Dz 111110********** 10110010xxyyzzzz DCF PADD Sx,Sy,Dz 111110********** 10110011xxyyzzzz PSUB Sx,Sy,Dz 111110********** 10100001xxyyzzzz DCT PSUB Sx,Sy,Dz 111110********** 10100010xxyyzzzz DCF PSUB Sx,Sy,Dz 111110********** 10100011xxyyzzzz PSHA Sx,Sy,Dz 111110********** 1010001xxyyzzzz DCT PSHA Sx,Sy,Dz 111110********** 10010010xxyyzzzz 1 * Rev. 5.00 Dec 12, 2005 page 88 of 1034 REJ09B0254-0500 Section 2 CPU Execution States 1 Instruction DCF PSHA Sx,Sy,Dz Instruction Code 111110********** 10010011xxyyzzzz Operation If DC = 0 & Sy > = 0, Sx << Sy Dz (arithmetic shift) If DC = 0 & Sy < 0, Sx >> Sy Dz If DC = 1, nop DC * PSHL Sx,Sy,Dz 111110********** 10000001xxyyzzzz If Sy > = 0, Sx << Sy Dz (logical shift) If Sy < 0, Sx >> Sy Dz 1 * DCT PSHL Sx,Sy,Dz 111110********** 10000010xxyyzzzz If DC = 1 & Sy > = 0, 1 Sx << Sy Dz (logical shift) If DC = 1 & Sy < 0, Sx >> Sy Dz If DC = 0, nop * DCF PSHL Sx,Sy,Dz 111110********** 10000011xxyyzzzz If DC = 0 & Sy > = 0, 1 Sx << Sy Dz (logical shift) If DC = 0 & Sy < 0, Sx >> Sy Dz If DC = 1, nop * PCOPY Sx,Dz 111110********** 11011001xx00zzzz Sx Dz Sy Dz If DC = 1, Sx Dz If DC = 0, nop If DC = 1, Sy Dz If DC = 0, nop If DC = 0, Sx Dz If DC = 1, nop If DC = 0, Sy Dz If DC = 1, nop Sx Dz normalization count shift value 1 1 1 1 1 1 1 * * * * * * * PCOPY Sy,Dz 111110********** 1111100100yyzzzz DCT PCOPY Sx,Dz 111110********** 11011010xx00zzzz DCT PCOPY Sy,Dz 111110********** 1111101000yyzzzz DCF PCOPY Sx,Dz 111110********** 11011011xx00zzzz DCF PCOPY Sy,Dz 111110********** 1111101100yyzzzz PDMSB Sx,Dz 111110********** 10011101xx00zzzz Rev. 5.00 Dec 12, 2005 page 89 of 1034 REJ09B0254-0500 Section 2 CPU Execution States 1 1 Instruction PDMSB Sy,Dz Instruction Code 111110********** 1011110100yyzzzz Operation Sx Dz normalization count shift value If DC = 1, normalization count shift value Sx Dz If DC = 0, nop If DC = 1, normalization count shift value Sy Dz If DC = 0, nop If DC = 0, normalization count shift value Sx Dz If DC = 1, nop If DC = 0, normalization count shift value Sy Dz If DC = 1, nop MSW of Sx Dz MSW of Sy Dz If DC = 1, MSW of Sx + 1 Dz If DC = 0, nop If DC = 1, MSW of Sy + 1 Dz If DC = 0, nop If DC = 0, MSW of Sx + 1 Dz If DC = 1, nop If DC = 0, MSW of Sy + 1 Dz If DC = 1, nop 0 - Sx Dz 0 - Sy Dz DC * * DCT PDMSB Sx,Dz 111110********** 10011110xx00zzzz DCT PDMSB Sy,Dz 111110********** 1011111000yyzzzz 1 * DCF PDMSB Sx,Dz 111110********** 10011111xx00zzzz 1 * DCF PDMSB Sy,Dz 111110********** 1011111100yyzzzz 1 * PINC Sx,Dz 111110********** 10011001xx00zzzz 1 1 1 * * * PINC Sy,Dz 111110********** 1011100100yyzzzz DCT PINC Sx,Dz 111110********** 10011010xx00zzzz DCT PINC Sy,Dz 111110********** 1011101000yyzzzz 1 * DCF PINC Sx,Dz 111110********** 10011011xx00zzzz 1 * DCF PINC Sy,Dz 111110********** 1011101100yyzzzz 1 * PNEG Sx,Dz 111110********** 11001001xx00zzzz 1 1 * * PNEG Sy,Dz 111110********** 1110100100yyzzzz Rev. 5.00 Dec 12, 2005 page 90 of 1034 REJ09B0254-0500 Section 2 CPU Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction DCT PNEG Sx,Dz Instruction Code 111110********** 11001010xx00zzzz Operation If DC = 1, 0 - Sx Dz If DC = 0, nop If DC = 1, 0 - Sy Dz If DC = 0, nop If DC = 0, 0 - Sx Dz If DC = 1, nop If DC = 0, 0 - Sy Dz If DC = 1, nop Sx | Sy Dz If DC = 1, Sx | Sy Dz If DC = 0, nop If DC = 0, Sx | Sy Dz If DC = 1, nop Sx & Sy Dz If DC = 1, Sx & Sy Dz If DC = 0, nop If DC = 0, Sx & Sy Dz If DC = 1, nop Sx ^ Sy Dz If DC = 1, Sx ^ Sy Dz If DC = 0, nop If DC = 1, Sx ^ Sy Dz If DC = 0, nop Sx [39:16] - 1 Dz Sy [31:16] - 1 Dz DC * * * * * * * * * * * * * * * DCT PNEG Sy,Dz 111110********** 1110101000yyzzzz DCF PNEG Sx,Dz 111110********** 11001011xx00zzzz DCF PNEG Sy,Dz 111110********** 1110101100yyzzzz POR Sx,Sy,Dz 111110********** 10110101xxyyzzzz DCT POR Sx,Sy,Dz 111110********** 10110110xxyyzzzz DCF POR Sx,Sy,Dz 111110********** 10110111xxyyzzzz PAND Sx,Sy,Dz 111110********** 10010101xxyyzzzz DCT PAND Sx,Sy,Dz 111110********** 10010110xxyyzzzz DCF PAND Sx,Sy,Dz 111110********** 10010111xxyyzzzz PXOR Sx,Sy,Dz 111110********** 10100101xxyyzzzz DCT PXOR Sx,Sy,Dz 111110********** 10100110xxyyzzzz DCF PXOR Sx,Sy,Dz 111110********** 10100111xxyyzzzz PDEC Sx,Dz 111110********** 10001001xx00zzzz PDEC Sy,Dz 111110********** 1010100100yyzzzz Rev. 5.00 Dec 12, 2005 page 91 of 1034 REJ09B0254-0500 Section 2 CPU Execution States 1 Instruction DCT PDEC Sx,Dz Instruction Code 111110********** 10001010xx00zzzz Operation If DC = 1, Sx [39:16] - 1 Dz If DC = 0, nop If DC = 1, Sy [31:16] - 1 Dz If DC = 0, nop If DC = 0, Sx [39:16] - 1 Dz If DC = 1, nop If DC = 0, Sy [31:16] - 1 Dz If DC = 1, nop H'00000000 Dz If DC = 1, H'00000000 Dz If DC = 0, nop If DC = 0, H'00000000 Dz If DC = 1, nop If imm > = 0, Dz << imm Dz (arithmetic shift) If imm<0, Dz>>imm Dz If imm > = 0, Dz << imm Dz (logical shift) If imm < 0, Dz >> imm Dz MACH Dz If DC = 1, MACH Dz If DC = 0, MACH Dz MACL Dz DC * DCT PDEC Sy,Dz 111110********** 1010101000yyzzzz 1 * DCF PDEC Sx,Dz 111110********** 10001011xx00zzzz 1 * DCF PDEC Sy,Dz 111110********** 1010101100yyzzzz 1 * PCLR Dz 111110********** 100011010000zzzz 1 1 1 1 * * * * DCT PCLR Dz 111110********** 100011100000zzzz DCF PCLR Dz 111110********** 100011110000zzzz PSHA #imm,Dz 111110********** 00010iiiiiiizzzz PSHL #imm,Dz 111110********** 00000iiiiiiizzzz 1 * PSTS MACH,Dz 111110********** 110011010000zzzz 1 1 1 1 -- -- -- -- DCT PSTS MACH,Dz 111110********** 110011100000zzzz DCF PSTS MACH,Dz 111110********** 110011110000zzzz PSTS MACL,Dz 111110********** 110111010000zzzz Rev. 5.00 Dec 12, 2005 page 92 of 1034 REJ09B0254-0500 Section 2 CPU Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction DCT PSTS MACL,Dz Instruction Code 111110********** 110111100000zzzz Operation If DC = 1, MACL Dz If DC = 0, MACL Dz Dz MACH If DC = 1, Dz MACH If DC = 0, Dz MACH Dz MACL If DC = 1, Dz MACL If DC = 0, Dz MACL Sx + Sy + DC Dz Carry DC Sx - Sy - DC Dz Borrow DC Sx - Sy DC update* If Sx < 0, 0 - Sx Dz If Sx > = 0, nop If Sy < 0, 0 - Sy Dz If Sx > = 0, nop Sx + H'00008000 Dz LSW of Dz H'0000 Sy + H'00008000 Dz LSW of Dz H'0000 DC -- -- -- -- -- -- -- -- Carry Borrow * * * * * DCF PSTS MACL,Dz 111110********** 110111110000zzzz PLDS Dz,MACH 111110********** 111011010000zzzz DCT PLDS Dz,MACH 111110********** 111011100000zzzz DCF PLDS Dz,MACH 111110********** 111011110000zzzz PLDS Dz,MACL 111110********** 111111010000zzzz DCT PLDS Dz,MACL 111110********** 111111100000zzzz DCF PLDS Dz,MACL 111110********** 111111110000zzzz PADDC Sx,Sy,Dz 111110********** 10110000xxyyzzzz PSUBC Sx,Sy,Dz 111110********** 10100000xxyyzzzz PCMP Sx,Sy 111110********** 10000100xxyy0000 PABS Sx,Dz 111110********** 10001000xx00zzzz PABS Sy,Dz 111110********** 1010100000yyzzzz PRND Sx,Dz 111110********** 10011000xx00zzzz PRND Sy,Dz Note: * See table 2.33. 111110********** 1011100000yyzzzz Rev. 5.00 Dec 12, 2005 page 93 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.33 DC Bit Update Definitions CS [2:0] 0 0 0 Condition Mode Carry or borrow mode Description The DC bit is set if an ALU arithmetic operation generates a carry or borrow, and is cleared otherwise. When a PSHA or PSHL shift instruction is executed, the last bit data shifted out is copied into the DC bit. When an ALU logical operation is executed, the DC bit is always cleared. 0 0 1 Negative value mode When an ALU or shift (PSHA) arithmetic operation is executed, the MSB of the result, including the guard bits, is copied into the DC bit. When an ALU or shift (PSHL) logical operation is executed, the MSB of the result, excluding the guard bits, is copied into the DC bit. 0 0 1 1 0 1 Zero value mode Overflow mode The DC bit is set if the result of an ALU or shift operation is allzeros, and is cleared otherwise. The DC bit is set if the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, excluding the guard bits, and is cleared otherwise. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. 1 0 0 Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is mode cleared if the result is all-zeros. DC = ~{(negative value ^ over-range) | zero value}; In case of arithmetic operation DC = 0; In case of logical operation 1 0 1 Signed greater-orequal mode If the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, including the guard bits ("over-range"), the definition is the same as in negative value mode. If the result is not over-range, the definition is the opposite of that in negative value mode. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. DC = ~(negative value ^ over-range); In case of arithmetic operation DC = 0; In case of logical operation 1 1 1 1 0 1 Reserved Reserved Rev. 5.00 Dec 12, 2005 page 94 of 1034 REJ09B0254-0500 Section 2 CPU Conditional Operations and Data Transfer: Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for which a parallel specification is made. Examples are shown in figure 2.17. DCT PADD X0,Y0,A0 When condition is True Before execution: X0=H'33333333, Y0=H'55555555, R4=H'00008000, R6=H'00008233, (R4)=H'1111, (R6)=H'2222 After execution: X0=H'11110000, Y0=H'55555555, R4=H'00008002, R6=H'00008237, (R4)=H'1111, (R6)=H'3456 When condition is False Before execution: X0=H'33333333, Y0=H'55555555, R4=H'00008000, R6=H'00008233, (R4)=H'1111, (R6)=H'2222 After execution: X0=H'11110000, Y0=H'55555555, R4=H'00008002, R6=H'00008237, (R4)=H'1111, (R6)=H'3456 A0=H'123456789A, R9=H'00000004 A0=H'123456789A, R9=H'00000004 A0=H'123456789A, R9=H'00000004 A0=H'0088888888, R9=H'00000004 MOVX.W @R4+,X0 MOVY.W A0,@R6+R9 ; Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions Assignment of NOPX and NOPY Instruction Codes: When there is no data transfer instruction to be parallel-processed simultaneously with a DSP operation instruction, an NOPX or NOPY instruction can be written as the data transfer instruction, or the instruction can be omitted. The instruction code is the same whether an NOPX or NOPY instruction is written or the instruction is omitted. Examples of NOPX and NOPY instruction codes are shown in table 2.34. Rev. 5.00 Dec 12, 2005 page 95 of 1034 REJ09B0254-0500 Section 2 CPU Table 2.34 Examples of NOPX and NOPY Instruction Codes Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 Code 1111100000001011 1011000100000111 PADD X0,Y0,A0 NOPX MOVY.W @R6+R9,Y0 1111100000000011 1011000100000111 PADD X0,Y0,A0 NOPX NOPY 1111100000000000 1011000100000111 PADD X0,Y0,A0 NOPX 1111100000000000 1011000100000111 PADD X0,Y0,A0 1111100000000000 1011000100000111 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVS.W @R4+,X0 NOPX MOVY.W @R6+R9,Y0 MOVY.W @R6+R9,Y0 NOPX NOP NOPY MOVY.W @R6+R9,Y0 NOPY 1111000000001011 1111000000001000 1111010010001000 1111000000000011 1111000000000011 1111000000000000 0000000000001001 Rev. 5.00 Dec 12, 2005 page 96 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) Section 3 Memory Management Unit (MMU) 3.1 3.1.1 Overview Features The SH7727 has an on-chip memory management unit (MMU) that implements address translation. The SH7727 features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables located in external memory. It enables highspeed translation of logical addresses into physical addresses. Address translation uses the paging system and supports two page sizes (1 kbyte and 4 kbytes). The access right to logical address space can be set for privileged and user modes to provide memory protection. 3.1.2 Role of MMU The MMU is a feature designed to make efficient use of physical memory. As shown in figure 3.1, if a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory. However, if the process increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands (1). Having the process itself consider this mapping onto physical memory would impose a large burden on the process. To lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory (2). In a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. Thus a process only has to consider operation in virtual memory. Mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. Switching of physical memory is carried out via secondary storage, etc. The virtual memory system that came into being in this way is particularly effective in a timesharing system (TSS) in which a number of processes are running simultaneously (3). If processes running in a TSS had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this load on the individual processes and so improve efficiency (4). In the virtual memory system, virtual memory is allocated to each process. The task of the MMU is to perform efficient mapping of these virtual memory areas onto physical memory. It also has a memory protection feature that prevents one process from inadvertently accessing another process's physical memory. Rev. 5.00 Dec 12, 2005 page 97 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) When address translation from virtual memory to physical memory is performed using the MMU, it may occur that the relevant translation information is not recorded in the MMU, with the result that one process may inadvertently access the virtual memory allocated to another process. In this case, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information. The TLB can be described as a cache for storing address translation information. Unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally performed by software. This makes it possible for memory management to be performed flexibly by software. The MMU has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. In the following text, the SH7727 address space in virtual memory is referred to as logical address space, and address space in physical memory as physical memory space. Rev. 5.00 Dec 12, 2005 page 98 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) Virtual memory Process 1 Physical memory Process 1 Process 1 Physical memory MMU Physical memory (1) (2) Process 1 Physical memory Process 2 Process 1 Virtual memory MMU Physical memory Process 2 Process 3 Process 3 (3) (4) Figure 3.1 MMU Functions 3.1.3 SH7727 MMU Logical Address Space: The SH7727 uses 32-bit logical addresses to access a 4-Gbyte logical address space that is divided into several areas. Address space mapping is shown in figure 3.2. In the privileged mode, there are five areas, P0 to P4. The P0 and P3 areas are mapped onto physical address space in page units, in accordance with address translation table information. Write-back or write-through can be selected for write access by means of a CCR setting. Mapping of the P1 area is fixed in physical address space (H'00000000 to H'1FFFFFFF). In the P1 area, setting a logical address MSB (bit 31) to 0 generates the corresponding physical address. P1 area accesses can be cached, and the cache control register (CCR) is set to indicate whether to cache or not. Write-back or write-through mode can be selected. Rev. 5.00 Dec 12, 2005 page 99 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) Mapping of the P2 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P2 area, setting the top three logical address bits (bits 31, 30, and 29) to 0 generates the corresponding physical address. P2 area access cannot be cached. The P1 and P2 areas are not mapped by the address translation table, so the TLB is not used and no exceptions like TLB misses occur. Initialization of MMU-related registers, exception handling, and the like are located in the P1 and P2 areas. Because the P1 area is cached, handlers that require high-speed processing are placed there. A part of the control register in the peripheral module is allocated in area 1 of the physical address space. When the physical address space is not used for address translation, allocate that part of the control register in the P2 area. When the physical address space is used for address translation, set no caching. The P4 area is used for mapping on-chip control register addresses. In the user mode, 2 Gbytes of the logical address space from H'00000000 to H'7FFFFFFF (area U0) can be accessed. U0 is mapped onto physical address space in page units, in accordance with address translation table information. When SR.DSP is off, 2 Gbytes of the logical address space from H'80000000 to H'FFFFFFFF cannot be accessed in the user mode. Attempting to do so creates an address error. Write-back or write-through mode can be selected for write accesses by means of a CCR setting. When the SR.DSP is on, a new 16-MB address space, Uxy, is defined from address H'A5000000 to H'A5FFFFFF for X/Y RAM. This Uxy space is non-cached, fixed physical address space. Any access to address space beyond U0 and Uxy creates an address error. For details on the X/Y RAM space, refer to section 6, X/Y Memory. Rev. 5.00 Dec 12, 2005 page 100 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) H'00000000 H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) Area P0 2-Gbyte virtual space, cacheable (write-back/write-through) Area U0 H'80000000 0.5-Gbyte fixed physical space, cacheable (write-back/write-through) 0.5-Gbyte fixed physical space, non-cacheable 0.5-Gbyte virtual space, cacheable (write-back/write-through) 0.5-Gbyte control space, non-cacheable H'80000000 Area P1 Address error H'A0000000 Area P2 H'C0000000 Area Uxy (present only when SR.DSP=1) Area P3 Address error Area P4 H'FFFFFFFF H'E0000000 H'FFFFFFFF Privileged mode User mode Figure 3.2 Logical Address Space Mapping Physical Address Space: The SH7727 supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 12, Bus State Controller (BSC), for details. Address Translation: When the MMU is enabled, the logical address space is divided into units called pages. Physical addresses are translated in page units. Address translation tables in external memory hold information such as the physical address that corresponds to the logical address and memory protection codes. When an access to an area other than P4 occurs, if the accessed logical address belongs to area P1 or P2 there is no TLB access and the physical address is uniquely defined. If it belongs to area P0, P3 or U0, the TLB is searched by logical address and, if that logical address is registered in the TLB, the access hits the TLB. The corresponding physical Rev. 5.00 Dec 12, 2005 page 101 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) address and the page control information are read from the TLB and the physical address is determined. If the logical address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the TLB. After returning from the handler, the instruction that caused the TLB miss is re-executed. When the MMU is enabled, address translation information that results in a physical address space of H'80000000 to H'FFFFFFFF should not be registered in the TLB. When the MMU is disabled, the logical address is used directly as the physical address. As the SH7727 supports a 29-bit address space as the physical address space, the top 3 bits of the physical address are ignored, and constitute a shadow space (see section 12, Bus State Controller (BSC)). For example, addresses H'00001000 in the P0 area, H'80001000 in the P1 area, H'A0001000 in the P2 area, and H'C0001000 in the P3 area are all mapped onto the same physical address. When access to these addresses is performed with the cache enabled, an address with the top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data congruity. Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual memory mode, multiple processes run in parallel using the logical address space exclusively and the physical address corresponding to a given logical address is specified uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the logical address space, so a given logical address may be translated into different physical addresses depending on the process. By the value set to the MMU control register (MMUCR), either single or multiple virtual mode is selected. In terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the TLB address comparison method (see section 3.3.3, TLB Address Comparison). Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate between processes running in parallel and sharing logical address space. The ASID is 8 bits in length and can be set by software setting of the ASID of the currently running process in PTEH within the MMU. When the process is switched using the ASID, the TLB does not have to be purged. In single virtual memory mode, the ASID is used to provide memory protection for processes running simultaneously and using the logical address space exclusively (see section 3.4.2, MMU Software Management). Rev. 5.00 Dec 12, 2005 page 102 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.1.4 Register Configuration Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Name Page table entry register low Translation table base register TLB exception address register MMU control register Register Configuration Abbreviation PTEL TTB TEA MMUCR R/W R/W R/W R/W R/W R/W Size Longword Longword Longword Longword Longword Initial Value* Undefined Undefined Undefined 1 Address H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0 Page table entry register high PTEH Undefined *2 Notes: 1. Initialized by a power-on reset or manual reset. 2. SV bit = undefined Other bits = 0 3.2 Register Description There are five registers for MMU processing. These are all peripheral module registers, so they are located in address space area P4 and can only be accessed from privileged mode by specifying the address. These registers consist of: 1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the logical address at which the exception is generated in case of an MMU exception or address error exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the logical address, but in this case the upper 22 bits of the logical address are set. The VPN can also be modified by software. As the ASID, software sets the number of the currently executing process. The VPN and ASID are recorded in the TLB by the LDTLB instruction. 2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to store the physical page number and page management information to be recorded in the TLB by the LDTLB instruction. The contents of this register are only modified in response to a software command. 3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the base address of the current page table. The software does not set any value in TTB automatically. TTB is available to software for general purposes. Rev. 5.00 Dec 12, 2005 page 103 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the logical address corresponding to a TLB or address error exception. This value remains valid until the next exception or interrupt. 5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in the P1 or P2 area. The MMU registers are shown in figure 3.3. 31 VPN PTEH 31 PPN PTEL 31 TTB TTB 31 Virtual address causing TLB-related or address error exception TEA 31 0 MMUCR 0: Reserved bits. Always read as 0. Writing is ignored. However, 0 should also be specified in a write to MMUCR only. SV: Single virtual memory mode bit. Set to 1 for the single virtual memory mode, cleared to 0 for the multiple virtual memory mode. RC: A 2-bit random counter, automatically updated by hardware according to the following rules in the event of an MMU exception. When a TLB miss exception occurs, all TLB entry ways corresponding to the virtual address at which the exception occurred are checked, and if all ways are valid, 1 is added to RC; if there is one or more invalid way, they are set by priority from way 0, in the order: way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB miss exception, the way which caused the exception is set in RC. TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always reads 0. IX: Index mode bit. When 0, VPN bits 16 to 12 are used as the TLB index number. When 1, the value obtained by EX-ORing ASID bits 4 to 0 in PTEH and VPN bits 16 to 12 are used as the TLB index number. AT: Address translation bit. Enables/disables the MMU. 0: MMU disabled 1: MMU enabled 8 7 6543 2 1 0 SV 00 RC 0 TF IX AT 0 0 10 9 8 7 6 4 321 0 10 0 7 ASID 0 0 V 0 PR SZ C D SH 0 Figure 3.3 MMU Register Contents Rev. 5.00 Dec 12, 2005 page 104 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.3 3.3.1 TLB Functions Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number, the address space identifier, and the control information for the page, which is the unit of address translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries for each way. Figure 3.5 shows the configuration of logical addresses and TLB entries. Ways 0 to 3 Ways 0 to 3 Entry 0 Entry 1 VPN(31-17) VPN(11-10) ASID(7-0) V Entry 0 PPN(31-10) PR(1-0) SZ C D SH Entry 1 Entry 31 Address array Entry 31 Data array Figure 3.4 Overall Configuration of the TLB Rev. 5.00 Dec 12, 2005 page 105 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 31 VPN 10 9 Offset Virtual address (1-kbyte page) 0 31 VPN 12 11 Offset 0 Virtual address (4-kbyte page) (15) (2) (8) (1) (1) (1) (22) PPN (2) (1) (1) PR C D VPN (31-17) VPN (11-10) ASID SH SZ V TLB entry Legend: VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. Since VPN bits 16 to 12 are used as the index number, they are not stored in the TLB entry. ASID: Address space identifier. Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, the address is compared with the ASID in PTEH when address comparison is performed. SH: Share status bit 0 = Page not shared between processes 1 = Page shared between processes SZ: Page-size bit 0 = 1-kbyte page 1 = 4-kbyte page V: Valid bit. Indicates whether entry is valid. 0 = Invalid 1 = Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. PPN: Physical page number. Top 22 bits of physical address. PPN bits 11 and 10 are not used in case of a 4-kbyte page. Attention must be paid to the synonym problem in case of a 1-kbyte page (see section 3.4.4, Avoiding Synonym Problems). PR: Set the most significant bit to 0. Protection key field. 2-bit field encoded to define the access rights to the page. 00: Reading only is possible in privileged mode. 01: Reading/writing is possible in privileged mode. 10: Reading only is possible in privileged/user mode. 11: Reading/writing is possible in privileged/user mode. C: Cacheable bit. Indicates whether the page is cacheable. 0 = Non-cacheable 1 = Cacheable D: Dirty bit. Indicates whether the page has been written to. 0 = Not written to 1 = Written to Figure 3.5 Logical Address and TLB Structure Rev. 5.00 Dec 12, 2005 page 106 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits 4 to 0 in PTEH are used as the index number. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR. 1. When IX = 0, VPN bits 16 to 12 alone are used as the index number 2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate the index number The method 1 is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same logical address space (multiple virtual memory) and a specific entry is selected by indexing of each process. Figures 3.6 and 3.7 show the indexing schemes. Virtual address 31 PTEH register 31 VPN ASID(4-0) 17 16 12 11 0 10 0 7 ASID 0 Exclusive-OR Index Ways 0 to 3 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(31-10) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.6 TLB Indexing (IX = 1) Rev. 5.00 Dec 12, 2005 page 107 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) Virtual address 31 17 16 12 11 0 Index Ways 0 to 3 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(31-10) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.7 TLB Indexing (IX = 0) 3.3.3 TLB Address Comparison A TLB address comparison is performed when an instruction is fetched from a program in external memory or data in external memory is referenced. The items used in the comparison are VPN and ASID. The VPN of the logical address that accesses external memory is compared to the VPN of the TLB entry selected with the index number. The ASID within the PTEH is compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered. It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. For example, if there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there is a possibility of simultaneous TLB hits in both these ways. It is therefore necessary to ensure that this kind of setting is not made by software. The object compared varies depending on the page management information (SZ, SH) in the TLB entry. It also varies depending on whether the system supports multiple virtual memory or single virtual memory. Rev. 5.00 Dec 12, 2005 page 108 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) The page-size information determines whether VPN (11, 10) is compared. VPN (11, 10) is compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1). The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not when there is sharing (SH = 1). When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged. The objects of address comparison are shown in figure 3.8. SH = 1 or (SR.MD = 1 and MMUCR.SV = 1)? Yes No No (4 kbytes) SZ = 0? Yes (1 kbyte) Bits compared: VPN (31-17) VPN (11-10) Bits compared: VPN (31-17) SZ = 0? No (4 kbytes) Yes (1 kbyte) Bits compared: VPN (31-17) VPN (11-10) ASID (7-0) Bits compared: VPN (31-17) ASID (7-0) Figure 3.8 Objects of Address Comparison Rev. 5.00 Dec 12, 2005 page 109 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception. For physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. To record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. The C bit in the entry indicates whether the referenced page resides in a cacheable or noncacheable area of memory. When the control register in area 1 is mapped, set the C bit to 0. The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory. Attempts at nonpermitted accesses result in TLB protection violation exceptions. Access states designated by the D, C, and PR bits are shown in table 3.2. Table 3.2 Access States Designated by D, C, and PR Bits Privileged Mode Reading D bit 0 1 C bit 0 1 PR bit 00 01 10 11 Permitted Permitted Permitted (no caching) Permitted (with caching) Permitted Permitted Permitted Permitted Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception Permitted TLB protection violation exception Permitted Reading Permitted Permitted Permitted (no caching) Permitted (with caching) User Mode Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection TLB protection violation exception violation exception TLB protection TLB protection violation exception violation exception Permitted Permitted TLB protection violation exception Permitted Rev. 5.00 Dec 12, 2005 page 110 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.4 3.4.1 MMU Functions MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the logical address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2. In address translation, the MMU receives page management information and bit information from the TLB, and determines the MMU exception and whether the cache is to be accessed (using the C bit). For details of the determination method and the hardware processing, see section 3.5, MMU Exceptions. 3.4.2 MMU Software Management There are three kinds of MMU software management, as follows. 1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2 for which address translation is not performed. Also, since SV and IX bit changes constitute address translation system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided with software that does not use the MMU. 2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3, MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6, MemoryMapped TLB, for details of the memory-mapped TLB. 3. MMU exception handling. When an MMU exception is generated, it is handled on the basis of information set from the hardware side. See section 3.5, MMU Exceptions, for details. When single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to specify recording of all TLB entries. This strengthens inter-process memory protection, and enables special access levels to be created in the privileged mode only. Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4, Avoiding Synonym Problems. Rev. 5.00 Dec 12, 2005 page 111 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in PTEH and ASID bits 4 to 0 in PTEH are used as the index number. Figure 3.9 shows the case where the IX bit in MMUCR is 0. When an MMU exception occurs, the virtual page number of the logical address that caused the exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each exception according to the rules shown in figure 3.9. Consequently, if the LDTLB instruction is issued after setting only PTEL in the MMU exception handling routine, TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR. As the LDTLB instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure, therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two instructions after the LDTLB instruction. Rev. 5.00 Dec 12, 2005 page 112 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) MMUCR 31 0 Index 9 0 SV 0 0 RC 0 TF IX AT Way selection PTEL register 31 10 PPN PTEH register 31 17 VPN 12 10 VPN 8 0 ASID 0 0 0 V 0 PR SZ C D SH 0 Write Ways 0 to 3 Write 0 VPN(31-17) VPN(11-10) ASID(7-) V PPN(31-10) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.9 Operation of LDTLB Instruction 3.4.4 Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of logical addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The reason why this problem only occurs when using a 1-kbyte page is explained below with reference to figure 3.10. To achieve high-speed operation of the SH7727 cache, an index number is created using logical address bits 11 to 4. When a 4-kbyte page is used, logical address bits 11 to 4 are included in the offset, and since they are not subject to address translation, they are the same as physical address bits 11 to 4. In cache-based address comparison and recording in the address array, since the cache tag address is a physical address, physical address bits 31 to 10 are recorded. When a 1-kbyte page is used, also, a cache index number is created using logical address bits 11 to 4. However, in case of a 1-kbyte page, logical address bits 11 and 10 are subject to address translation and therefore may not be the same as physical address bits 11 and 10. Consequently, Rev. 5.00 Dec 12, 2005 page 113 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array. Note: When multiple address information items use the same physical memory to provide for future expansion of the SuperH RISC engine family, it is recommended that VPN[20:10] be made equal. Also, the same physical addresses should not be used with different page size address conversion information. For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following translation has been performed are recorded in two TLBs: Logical address 1 Logical address 2 H'00000000 H'00000C00 physical address physical address H'00000C00 H'00000C00 Logical address 1 is recorded in cache entry H'00, and logical address 2 in cache entry H'C0. Since two logical addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will occur as soon as a write is performed to either logical address. Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same as a physical address already used in another TLB entry, it should be recorded in such a way that physical address bits 11 and 10 are the same. Rev. 5.00 Dec 12, 2005 page 114 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) When using a 4-kbyte page Virtual address 31 VPN 12 11 10 Offset 0 Physical address 31 PPN 12 11 10 Virtual address (11-4) 0 Offset Cache address array Physical address (31-10) When using a 1-kbyte page Virtual address 31 VPN 11 10 9 Offset 0 Physical address 31 PPN 11 10 9 Virtual address (11-4) 0 Offset Cache address array Physical address (31-10) Figure 3.10 Synonym Problem Rev. 5.00 Dec 12, 2005 page 115 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the logical address and the address array of the selected TLB entry are compared and no match is found. TLB miss exception handling includes both hardware and software operations. Hardware Operations: In a TLB miss, the SH7727 hardware executes a set of prescribed operations, as follows: 1. The VPN field of the logical address causing the exception is written to the PTEH register. 2. The logical address causing the exception is written to the TEA register. 3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the save program counter (SPC). If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of the status register (SR) at the time of the exception are written to the save status register (SSR). 6. The mode (MD) bit in SR is set to 1 to place the SH7727 in the privileged mode. 7. The block (BL) bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The random counter (RC) field in the MMU control register (MMUCR) is incremented by 1 when all ways are checked for the TLB entry corresponding to the logical address at which the exception occurred, and all ways are valid. If one or more ways are invalid, those ways are set in RC in prioritized order from way 0 through way 1, way 2, and way 3. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000400 to invoke the user-written TLB miss exception handler. Software (TLB Miss Handler) Operations: The software searches the page tables in external memory and allocates the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the value of the physical page number (PPN) field and the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry Rev. 5.00 Dec 12, 2005 page 116 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) recorded in the address translation table in the external memory into the PTEL register in the SH7727. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. 3.5.2 TLB Protection Violation Exception A TLB protection violation exception results when the logical address and the address array of the selected TLB entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the PR field. TLB protection violation exception handling includes both hardware and software operations. Hardware Operations: In a TLB protection violation exception, the SH7727 hardware executes a set of prescribed operations, as follows: 1. The VPN field of the logical address causing the exception is written to the PTEH register. 2. The logical address causing the exception is written to the TEA register. 3. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written into SPC (if the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written into SPC). 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7727 in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The way that generated the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the TLB protection violation exception handler. Software (TLB Protection Violation Handler) Operations: Software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Rev. 5.00 Dec 12, 2005 page 117 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.5.3 TLB Invalid Exception A TLB invalid exception results when the logical address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception handling includes both hardware and software operations. Hardware Operations: In a TLB invalid exception, the SH7727 hardware executes a set of prescribed operations, as follows: 1. The VPN number of the logical address causing the exception is written to the PTEH register. 2. The logical address causing the exception is written to the TEA register. 3. The way number causing the exception is written to RC in MMUCR. 4. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 5. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the delayed branch instruction is written to the SPC. 6. The contents of SR at the time of the exception are written into SSR. 7. The mode (MD) bit in SR is set to 1 to place the SH7727 in the privileged mode. 8. The block (BL) bit in SR is set to 1 to mask any further exception requests. 9. The register bank (RB) bit in SR is set to 1. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100, and the TLB protection violation exception handler starts. Software (TLB Invalid Exception Handler) Operations: The software searches the page tables in external memory and assigns the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the values of the physical page number (PPN) field and the values of the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in the external memory to the PTEL register. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Rev. 5.00 Dec 12, 2005 page 118 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.5.4 Initial Page Write Exception An initial page write exception results in a write access when the logical address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial page write exception handling includes both hardware and software operations. Hardware Operations: In an initial page write exception, the SH7727 hardware executes a set of prescribed operations, as follows: 1. The VPN field of the logical address causing the exception is written to the PTEH register. 2. The logical address causing the exception is written to the TEA register. 3. Exception code H'080 is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7727 in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The way that caused the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the user-written initial page write exception handler. Software (Initial Page Write Handler) Operations: The software must execute the following operations: 1. Retrieve the required page table entry from external memory. 2. Set the D bit of the page table entry in the external memory to 1. 3. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table entry in the external memory to the PTEL register. 4. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 5. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 6. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Figure 3.11 shows the flowchart for MMU exceptions. Rev. 5.00 Dec 12, 2005 page 119 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) Start SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? Yes VPNs match? No Yes VPNs and ASIDs match? Yes No TLB invalid exception Privileged mode No No V = 1? TLB miss exception User mode Yes User or privileged? PR check 00/01 W 10 R/W? R 11 R/W? R No D = 1? Yes TLB protection violation exception Initial page write exception No (noncacheable) Memory access C = 1? W W PR check 01/11 R/W? R 00/10 W R/W? R TLB protection violation Yes (cacheable) Cache access Figure 3.11 MMU Exception Generation Flowchart Rev. 5.00 Dec 12, 2005 page 120 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) MMU Exception in the Instruction Fetch Mode IF ID EX ID MA EX ID WB MA EX WB MA NOP NOP WB Handler transition processing MMU exception handler IF ID EX MA WB : Exception source stage IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation Figure 3.12 MMU Exception Signals in Instruction Fetch Rev. 5.00 Dec 12, 2005 page 121 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) MMU Exception in the Data Access Mode IF ID IF EX ID IF MA EX ID WB MA EX ID WB MA EX ID WB MA EX ID WB MA EX WB MA WB NOP NOP Handler transition processing MMU exception handler : Exception source stage : Stage cancellation for instruction that has begun execution IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation IF ID EX MA WB Figure 3.13 MMU Exception Signals in Data Access Rev. 5.00 Dec 12, 2005 page 122 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.5.6 MMU Exception in Repeat Loop When MMU exception or CPU address error occurs immediately before or within a repeat loop, the PC of the instruction that generated the exception can not be saved in SPC correctly and repeat loop can not be restarted after returning from exception handler. EXPEVT is set to H'070 in cases of TLB miss, TLB invalid, and CPU address error. EXPEVT is set to H'0D0 in case of TLB protection violation. Figure 3.14 describes the places where this case occurs. In a repeat loop of 4 or more instructions, only the last 4 instructions are relevant (see figure 3.14 (4)). (1) 1 instruction repeated (inst1, SR.RC=2) inst-1 inst0 inst1 inst1 inst2 IF ID IF EX MA WB ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB (2) 2 instructions repeated (inst1 and inst2, SR.RC=2) inst-1 inst0 inst1 inst2 inst1 inst2 inst3 IF ID IF EX MA WB ID EX MA WB IF ID EX MA IF ID EX IF ID IF WB MA EX ID IF WB MA WB EX MA WB ID EX MA WB (3) 3 instructions repeated (inst1, inst2 and inst3, SR.RC=2) inst-1 inst0 inst1 inst2 inst3 inst1 inst2 inst3 inst4 IF ID IF EX MA WB ID EX MA WB IF ID EX MA IF ID EX IF ID IF WB MA EX ID IF WB MA EX ID IF WB MA EX ID IF WB MA WB EX MA WB ID EX MA WB : Exception source stage where SPC is not correct and repeat loop can not be restarted Figure 3.14 MMU Exception in Repeat Loop Rev. 5.00 Dec 12, 2005 page 123 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) (4) 4 or more instructions repeated (inst1, inst2, ..., instN, SR.RC=2) inst-1 IF inst0 inst1 inst2 : instN-3 instN-2 instN-1 instN inst1 inst2 : instN-3 instN-2 instN-1 instN instN+1 ID IF EX MA WB ID EX MA WB IF ID EX MA WB IF ID EX MA WB : IF ID IF EX MA WB ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB : IF ID IF EX MA WB ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB : Exception source stage where SPC is not correct and repeat loop can not be restarted Figure 3.14 MMU Exception in Repeat Loop (cont) 3.6 Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the logical address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only longword access is possible for both the address array and the data array. Rev. 5.00 Dec 12, 2005 page 124 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.6.1 Address Array The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the 32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the VPN, V bit and ASID to be written to the address array ((1) in figure 3.15). In the address field, specify VPN (16 to 12) as the index address for selecting the entry (bits 16 to 12), the W bits for selecting the way (bits 9 and 8), and H'F2 to indicate address array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR of VPN (16 to 12) and ASID (4 to 0) in the PTEH register is taken as the index address. When writing, the write is performed to the entry selected with the index address and way. When reading, the VPN, V bit, and ASID of the entry selected with the index address and way in the format of the data field in figure 3.12 without comparing addresses. 0 is written to data field bits 16 to 12. To invalidate a specific entry, specify the entry and way, and write 0 to the corresponding V bit. 3.6.2 Data Array The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. The address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array ((2) in figure 3.15). Longword data has the same bit configuration as PTEL. In the address field, specify VPN (16 to 12) as the index address for selecting the entry (bits 16 to 12), the W bits for selecting the way (bits 9 and 8), and H'F3 to indicate data array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR of VPN (16 to 12) and ASID (4 to 0) in the PTEH register is taken as the index address. Both reading and writing use the longword of the data array specified by the entry address and way number. Rev. 5.00 Dec 12, 2005 page 125 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) (1) TLB Address Array Access Read access 31 Address field 31 Data field VPN 11110010 24 23 17 16 12 11 10 9 8 7 6 0 * * 17 16 0 VPN ** W 0 * ASID * 0 12 11 10 9 8 7 0 VPN 0 V Write access 31 Address field 31 Data field VPN: V: W: VPN 11110010 24 23 17 16 12 11 10 9 8 7 6 VPN 0 * * 17 16 ** W 0 * ASID * 0 12 11 10 9 8 7 * * VPN * V Virtual page number ASID: Address space identifier Valid bit *: Don't care bit Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) (2) TLB Data Array Access Read/write access 31 Address field 31 Data field 11110011 29 28 PPN 24 23 17 16 12 11 10 9 8 7 VPN 0 * * ** W * 32 1 * 0 10 9 8 7 6 5 4 000 X V X PR SZ C D SH X PPN: PR: C: SH: VPN: X: W: Physical page number V: Valid bit Protection key field SZ: Page-size bit Cacheable bit D: Dirty bit Share status bit *: Don't care bit Virtual page number 0 for read, don't care bit for write Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) Figure 3.15 Specifying Address and Data for Memory-Mapped TLB Access Rev. 5.00 Dec 12, 2005 page 126 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C ; MMUCR.IX=0 ; VPN(31-17)=B'0001 0101 0100 011 VPN(11-10)=B'10 ASID=B'0001 1100 R1=H'F201 30 ; corresponding entry association is made from the entry selected by ; the VPN(16-12)=B'1 0011 index, the V bit of the hit way is cleared to ; 0,achieving invalidation. MOV.L R0,@R1 Reading the Data of a Specific Entry: This example reads the data section of a specific TLB entry. The bit order indicated in the data field in figure 3.15 (2) is read. R0 specifies the address and the data section of a selected entry is read to R1. ; R1=H'F300 4300 ; MOV.L @R0,R1 VPN(16-12)=B'00100 Way 3 Rev. 5.00 Dec 12, 2005 page 127 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) 3.7 1. Usage Notes Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction, LDC @Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB instruction, should be used with the TLB disabled or in a fixed physical address space (the P1 or P2 space). The value of the RC bit in MMUCR may be set abnormally if all of the following conditions are met: 2. (1) MMU is on (AT is set to 1 in MMUCR). (2) Identical entries in the TLB address array reference the same VPN using multiple ways. (3) A TLB related exception occurs. The VPN is not initialized at power on reset or manual reset. Therefore, identical entries may access two or more VPNs using the same value. In such cases, certain entries in the TLB address array may end up as shown below if, for example, they are registered in way 3. In this case way 0 and way 3 reference the same VPN, thereby satisfying condition (2). After reset WAY VPN 0 3 12345 12345 V 0 0 After registration to way 3 WAY VPN 0 3 12345 12345 V 0 1 The above conditions can also be satisfied by TLB handling in software. For example, the situation shown below could occur if, after invalidating way 0 (by setting V from 1 to 0) for an entry in the TLB address array, the entry is registered to way 3. In this case as well, the same VPN is assigned for both way 0 and way 3, thereby satisfying condition (2) above. After invalidation of way 0 WAY VPN 0 3 12345 11111 V 0 0 0 3 After registration to way 3 WAY VPN 12345 12345 V 0 1 Rev. 5.00 Dec 12, 2005 page 128 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) Measures to avoid the problem The following two measures should be taken to avoid the problem described above: a. After performing a reset and before setting AT to 1 in MMUCR, initialize to 1 the upper four bits of the VPNs for each entry in the TLB address array. b. When invalidating an entry in the TLB address array, initialize to 1 the upper four bits of the corresponding VPN in addition to setting V to 0. The above measures will ensure that the VPN is not in the area referenced after address conversion. This will prevent condition (3) from being satisfied and prevent the problem described above from arising. Rev. 5.00 Dec 12, 2005 page 129 of 1034 REJ09B0254-0500 Section 3 Memory Management Unit (MMU) Rev. 5.00 Dec 12, 2005 page 130 of 1034 REJ09B0254-0500 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler. However, in response to an interrupt request, normal program execution continues until the end of the executing instruction. Here, all exceptions other than resets and interrupts will be called general exceptions. There are thus three types of exceptions: resets, general exceptions, and interrupts. 4.1.2 Register Configuration Table 4.1 lists the registers used for exception handling. A register with an undefined initial value should be initialized by software. Table 4.1 Register Exception event register Interrupt event register Interrupt event register2 Register Configuration Abbr. R/W R/W Size Longword Longword Longword Longword Initial Value Undefined Address H'FFFFFFD0 TRAPA exception register TRA EXPEVT R/W INTEVT R/W Power-on reset: H'000 H'FFFFFFD4 Manual reset: H'020 Undefined Undefined H'FFFFFFD8 H'04000000 (H'A4000000)* INTEVT2 R Note: * When address translation by the MMU does not apply, the address in parentheses should be used. 4.2 4.2.1 Exception Handling Function Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. The return from exception handler (RTE) Rev. 5.00 Dec 12, 2005 page 131 of 1034 REJ09B0254-0500 Section 4 Exception Handling instruction is issued by the exception handler routine at the completion of the routine, restoring the contents of the PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations: 1. The contents of the PC and SR are saved in the SPC and SSR, respectively. 2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. 3. The mode (MD) bit in SR is set to 1 to place the SH7727 in the privileged mode. 4. The register bank (RB) bit in SR is set to 1. 5. An exception code identifying the exception event is written to bits 11 to 0 of the exception event (EXPEVT) or interrupt event (INTEVT or INTEVT2) register. 6. Instruction execution jumps to the designated exception handling vector address to invoke the handler routine. 4.2.2 Exception Handling Vector Addresses The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an offset from the vector base address of H'00000400. The vector address offset for general exception events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is H'00000600. The vector base address is loaded into the vector base register (VBR) by software. The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows the relationship between the vector base address, the vector offset, and the vector table. VBR (Vector base address) + Vector offset H'A000 0000 Vector address Figure 4.1 Vector Table With regard to exceptions and their vector addresses, table 4.2 lists exception type, instruction completion state, priority, exception order, vector address, and vector offset. Rev. 5.00 Dec 12, 2005 page 132 of 1034 REJ09B0254-0500 Section 4 Exception Handling Table 4.2 Exception Type Reset Exception Event Vectors Current Instruction Aborted Exception Event Power-on reset Manual reset H-UDI reset Priority*1 1 1 1 2 2 Exception Order -- -- -- 1 2 Vector Address H'A0000000 H'A0000000 H'A0000000 -- -- Vector Offset -- -- -- H'00000100 H'00000400 General exception events Aborted and retried CPU address error (instruction access) TLB miss (instruction access not in repeat loop) TLB miss (instruction access in repeat loop)*4 TLB invalid (instruction access) TLB protection violation (instruction access) General illegal instruction exception Illegal slot instruction exception CPU address error (data access) TLB miss (data access not in repeat loop) 2 2 -- H'00000100 2 2 3 4 -- -- H'00000100 H'00000100 2 2 2 2 5 5 6 7 -- -- -- -- H'00000100 H'00000100 H'00000100 H'00000400 TLB miss 2 (data access in repeat loop)*4 TLB invalid (data access) TLB protection violation (data access) Initial page write Completed Unconditional trap (TRAPA instruction) User breakpoint trap DMA address error 2 2 7 -- H'00000100 8 9 -- -- H'00000100 H'00000100 2 2 2 2 10 5 n*2 12 -- -- -- -- H'00000100 H'00000100 H'00000100 H'00000100 Rev. 5.00 Dec 12, 2005 page 133 of 1034 REJ09B0254-0500 Section 4 Exception Handling Exception Type General interrupt requests Current Instruction Completed Priority*1 4*3 4*3 Exception Order -- -- -- Vector Address -- -- -- Exception Event External hardware interrupt H-UDI interrupt Vector Offset H'00000600 H'00000600 H'00000600 Nonmaskable interrupt 3 Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest. 2. The user defines the break point traps. 1 is a break point before instruction execution and 11 is a break point after instruction execution. For an operand break point, use 11. 3. Use software to specify relative priorities of external hardware interrupts and peripheral module interrupts (see section 7, Interrupt Controller (INTC)). 4. See section 4.5.2, General Exceptions for details. 4.2.3 Acceptance of Exceptions Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. When a power-on reset and a manual reset occur simultaneously, the power-on reset has priority. All general exception events occur in a relative order in the execution sequence of an instruction (i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program order), where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction. Three general exception events (general illegal instruction exception, unconditional trap exception, and illegal slot instruction exception) are detected in the decode stage (ID stage) of different instructions and are mutually exclusive events in the instruction pipeline. They have the same execution priority. Figure 4.2 shows the order of general exception acceptance. Rev. 5.00 Dec 12, 2005 page 134 of 1034 REJ09B0254-0500 Section 4 Exception Handling Pipeline Sequence: Instruction n IF ID EX MA WB TLB miss (data access) Instruction n + 1 IF ID EX MA WB TLB miss (instruction access) Instruction n + 2 Detection Order: TLB miss (instruction n+1) IF ID EX MA WB RIE (reserved instruction exception) TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection Handling Order: TLB miss (instruction n) 1 Re-execution of instruction n Program Order: TLB miss (instruction n + 1) 2 Re-execution of instruction n + 1 RIE (instruction n + 2) 3 IF ID EX MA WB = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back Figure 4.2 Example of Acceptance Order of General Exceptions Rev. 5.00 Dec 12, 2005 page 135 of 1034 REJ09B0254-0500 Section 4 Exception Handling All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction boundaries. However, an exception is not accepted between a delayed branch instruction and the delay slot. A re-execution type exception detected in a delay slot is accepted before execution of the delayed branch instruction. A completion type exception detected in a delayed branch instruction or delay slot is accepted after execution of the delayed branch instruction. The delay slot here refers to the next instruction after a delayed unconditional branch instruction, or the next instruction when a delayed conditional branch instruction is true. 4.2.4 Exception Codes Table 4.3 lists the exception codes written to bits 11 to 0 of the EXPEVT register (for reset or general exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to identify each specific exception event. An additional exception register, the TRAPA (TRA) register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction). Table 4.3 Exception Codes Exception Event Power-on reset Manual reset H-UDI reset General exception events TLB miss/invalid (read) TLB miss/invalid (write) TLB miss/invalid/CPU Address error in repeat loop Initial page write TLB protection violation (read) TLB protection violation (write) TLB protection violation in repeat loop CPU Address error (read) CPU Address error (write) Unconditional trap (TRAPA instruction) Illegal general instruction exception Illegal slot instruction exception User breakpoint trap DMA address error Exception Code H'000 H'020 H'000 H'040 H'060 H'070 H'080 H'0A0 H'0C0 H'0D0 H'0E0 H'100 H'160 H'180 H'1A0 H'1E0 H'5C0 Exception Type Reset Rev. 5.00 Dec 12, 2005 page 136 of 1034 REJ09B0254-0500 Section 4 Exception Handling Exception Type General interrupt requests Exception Event Nonmaskable interrupt H-UDI interrupt External hardware interrupts: IRL3 to IRL0 = 0000 IRL3 to IRL0 = 0001 IRL3 to IRL0 = 0010 IRL3 to IRL0 = 0011 IRL3 to IRL0 = 0100 IRL3 to IRL0 = 0101 IRL3 to IRL0 = 0110 IRL3 to IRL0 = 0111 IRL3 to IRL0 = 1000 IRL3 to IRL0 = 1001 IRL3 to IRL0 = 1010 IRL3 to IRL0 = 1011 IRL3 to IRL0 = 1100 IRL3 to IRL0 = 1101 IRL3 to IRL0 = 1110 Note: Exception codes H'120, H'140, and H'3E0 are reserved. H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Exception Code H'1C0 H'5E0 4.2.5 Exception Request Masks When the BL bit in SR is 0, exceptions and interrupts are accepted. If a general exception event occurs when the BL bit in SR is 1, the CPU's internal registers are set to their post-reset state, other module registers retain their contents prior to the general exception, and a branch is made to the same address (H'A0000000) as for a reset. If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted until the BL bit is cleared to 0 by software. For reentrant exception handling, the SPC and SSR must be saved and the BL bit in SR cleared to 0. Rev. 5.00 Dec 12, 2005 page 137 of 1034 REJ09B0254-0500 Section 4 Exception Handling 4.2.6 Returning from Exception Handling The RTE instruction is used to return from exception handling. When RTE is executed, the SPC value is set in the PC, and the SSR value in SR, and the return from exception handling is performed by branching to the SPC address. If the SPC and SSR have been saved in the external memory, set the BL bit in SR to 1, then restore the SPC and SSR, and issue an RTE instruction. 4.3 Register Description There are four registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in the privileged mode only. 1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. 2. Interrupt event register 2 (INTEVT2) resides at address H'04000000, and contains a 12-bit exception code. The exception code set in INTEVT2 is that for an interrupt request. The exception code is set automatically by hardware when an exception occurs. 3. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit interrupt exception code or a code indicating the interrupt priority. Which is set when an interrupt occurs depends on the interrupt source (see tables 7.4 and 7.5). The exception code or interrupt priority code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. 4. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of the EXPEVT, INTEVT, INTEVT2, and TRA registers are shown in figure 4.3. Rev. 5.00 Dec 12, 2005 page 138 of 1034 REJ09B0254-0500 Section 4 Exception Handling EXPEVT register, INTEVT and INTEVT2 registers 31 0 0: 11 0 0 Exception code Reserved bits, always read as zero TRA register 31 0 0 9 imm 20 00 imm: 8-bit immediate data in TRAPA instruction Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers 4.4 4.4.1 Exception Handling Operation Reset The reset sequence is used to power up or restart the SH7727 from the initialization state. The RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are canceled, and reset processing is executed immediately. In the case of a manual reset, however, processing to retain external memory contents is continued. The reset sequence consists of the following operations: 1. The MD bit in SR is set to 1 to place the SH7727 in privileged mode. 2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when BLMSK bit is 1). 3. The RB bit in SR is set to 1. 4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11 to 0 of the EXPEVT register to identify the exception event. 5. Instruction execution jumps to the user-written exception handler at address H'A0000000. 4.4.2 Interrupts An interrupt processing request is accepted on completion of the current instruction. The interrupt acceptance sequence consists of the following operations: 1. The contents of the PC and SR are saved in SPC and SSR, respectively. 2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when BLMSK bit is 1). 3. The MD bit in SR is set to 1 to place the SH7727 in privileged mode. 4. The RB bit in SR is set to 1. Rev. 5.00 Dec 12, 2005 page 139 of 1034 REJ09B0254-0500 Section 4 Exception Handling 5. An encoded value identifying the exception event is written to bits 11 to 0 of the INTEVT and INTEVT2 registers. 6. Instruction execution jumps to the vector location designated by the sum of the value of the contents of the vector base register (VBR) and H'00000600 to invoke the exception handler. 4.4.3 General Exceptions When the SH7727 encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. The contents of the PC and SR are saved in the SPC and SSR, respectively. 2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when BLMSK bit is 1). 3. The MD bit in SR is set to 1 to place the SH7727 in privileged mode. 4. The RB bit in SR is set to 1. 5. An encoded value identifying the exception event is written to bits 11 to 0 of the EXPEVT register. 6. Instruction execution jumps to the vector location designated by either the sum of the vector base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke the exception handler. 4.5 Individual Exception Operations This section describes the conditions for specific exception handling, and the processor operations. 4.5.1 Resets * Power-On Reset Conditions: RESETP low Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'00000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting modules are initialized. See the register descriptions in the relevant sections for details. A power-on reset must always be performed when powering on. A high level is output from the STATUS0 and STATUS1 pins. Rev. 5.00 Dec 12, 2005 page 140 of 1034 REJ09B0254-0500 Section 4 Exception Handling * Manual Reset Conditions: RESETM low Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'00000000. In SR, the MD, RB, and BL bits are set to 1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting modules are initialized. See the register descriptions in the relevant sections for details. A high level is output from the STATUS0 and STATUS1 pins. * H-UDI Reset Conditions: H-UDI reset command input (see section 31.4.3, H-UDI Reset) Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting modules are initialized. See the register descriptions in the relevant sections for details. Table 4.4 Types of Reset Conditions for Transition to Reset State RESETP = Low RESETM = Low H-UDI reset command input Internal State CPU Initialized Initialized Initialized On-Chip Supporting Modules (See register configuration in relevant sections) Type Power-on reset Manual reset H-UDI reset 4.5.2 General Exceptions * TLB miss exception Conditions: Comparison of TLB addresses shows no address match Operations: The logical address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The RC bit in MMUCR is incremented by 1 when all ways are enabled, and if there is a disabled way, setting is prioritized starting from way 0. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0400. Rev. 5.00 Dec 12, 2005 page 141 of 1034 REJ09B0254-0500 Section 4 Exception Handling To speed up TLB miss processing, the offset differs from other exceptions. * TLB invalid exception Conditions: Comparison of TLB addresses shows address match but V = 0. Operations: The logical address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. The PC and SR of the instruction that generated the exception are saved in the SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * TLB exception/CPU address error in repeat loop Conditions: TLB miss, TLB invalid or CPU address error in the last several instructions of repeat loop (see section 3.5.6, MMU Exception in Repeat Loop) Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of exception. The SR of the instruction that generated the exception are saved in the SSR. But the SPC is not the PC of the instruction that generated the exception. Repeat loop can not be restarted after returning from exception handler. In order to complete a repeat loop, ensure not to cause TLB exceptions or CPU address error in the last several instructions of repeat loop (see section 3.5.6, MMU Exception in Repeat Loop). If the TLB exception or CPU address error occurred in the last several instructions of repeat loop, H'070 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * Initial page write exception Conditions: A hit occurred to the TLB for a store access, but D = 0. This occurs for initial writes to the page registered by the load. Operations: The logical address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bit in MMUCR. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs in PC = VBR + H'0100. Rev. 5.00 Dec 12, 2005 page 142 of 1034 REJ09B0254-0500 Section 4 Exception Handling * TLB protection exception Conditions: When a hit access violates the TLB protection information (PR bits) shown below: PR 00 01 10 11 Privileged mode Only read enabled Read/write enabled Only read enabled Read/write enabled User mode No access No access Only read enabled Read/write enabled Operations: The logical address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * TLB protection violation in repeat loop Conditions: TLB protection violation in the last several instruction of repeat loop (see section 3.5.6, MMU Exception in Repeat Loop) Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of exception. The SR of the instruction that generated the exception are saved in the SSR. But the SPC is not the PC of the instruction that generated the exception. Repeat loop can not be restarted after returning from exception handler. In order to complete a repeat loop, ensure not to cause TLB exceptions or CPU address error in the last several instructions of repeat loop (see section 3.5.6, MMU Exception in Repeat Loop). If a TLB protection violation occurs in an instruction immediately before or during a repeat loop, H'0D0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * CPU Address error Conditions: a. Instruction fetch from odd address (4n + 1, 4n + 3) b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF. Rev. 5.00 Dec 12, 2005 page 143 of 1034 REJ09B0254-0500 Section 4 Exception Handling Operations: The logical address (32 bits) that caused the exception is set in TEA. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 3.5.5, Processing Flow in Event of MMU Exception, for more information. * Unconditional trap Conditions: TRAPA instruction executed Operations: The exception is a processing-completion type, so the PC of the instruction after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA instruction is quadrupled and set in TRA (9 to 0). H'160 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * Illegal general instruction exception Conditions: a. When undefined code not in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'Fxxx b. When a privileged instruction not in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. c. When a DSP instruction not in a delay slot is decoded without DSP extension (SR.DSP=0) DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+, DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD, STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx d. When an instruction that rewrites the PC/SR/RS/RE in the last three instructions of repeat loop is decoded. Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR Instructions that rewrite the SR: LDC Rm, SR, LDC.L @Rm+, SR, SETRC Instructions that rewrite the RS: LDC Rm, RS, LDC.L @Rm+, RS, LDRS Instructions that rewrite the RE: LDC Rm, RE, LDC.L @Rm+, RE, LDRE Rev. 5.00 Dec 12, 2005 page 144 of 1034 REJ09B0254-0500 Section 4 Exception Handling Operations: The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed. * Illegal slot instruction Conditions: a. When undefined code in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S, Undefined instruction: H'Fxxx b. When an instruction that rewrites the PC in a delay slot is decoded Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR c. When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. d. When a DSP instruction in a delay slot is decoded without DSP extension (SR.DSP=0) DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+, DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD, STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed. * User break point trap Conditions: When a break condition set in the user break controller is satisfied Operations: When a post-execution break occurs, the PC of the instruction immediately after the instruction that set the break point is set in the SPC. If a pre-execution break occurs, the PC of the instruction that set the break point is set in the SPC. SR when the break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 8, User Break Controller (UBC), for more information. Rev. 5.00 Dec 12, 2005 page 145 of 1034 REJ09B0254-0500 Section 4 Exception Handling * DMA Address error Conditions: a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) Operations: The PC of the instruction immediately after the instruction executed before the exception occurs is saved to the SPC. SR when the exception occurs is saved to SSR. H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. 4.5.3 1. NMI Conditions: NMI pin edge detection Operations: The PC and SR after the instruction that receives the interrupt are saved to the SPC and SSR, respectively. H'1C0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by SR.IMASK and received with top priority when the SR's BL bit in SR is 0. When the BL bit is 1, the interrupt is masked. See section 7, Interrupt Controller (INTC), for more information. 2. IRL Interrupts Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC value after the instruction at which the interrupt is accepted is saved to the SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to the IRL3 to IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as H'200 + [IRL3 to IRL0] x H'20. See table 7.5, for the corresponding codes. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set in SR.IMASK. See section 7, Interrupt Controller (INTC), for more information. 3. IRQ Pin Interrupts Conditions: IRQ pin is asserted and SR.IMASK is lower than the IRQ priority level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC value after the instruction at which the interrupt is accepted is saved to the SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set to SR.IMASK. See section 7, Interrupt Controller (INTC), for more information. Interrupts Rev. 5.00 Dec 12, 2005 page 146 of 1034 REJ09B0254-0500 Section 4 Exception Handling 4. PINT Pin Interrupts Conditions: The PINT pin is asserted and SR.IMASK is lower than the PINT priority level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC value after the instruction at which the interrupt is accepted is saved to the SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set to SR.IMASK. See section 7, Interrupt Controller (INTC), for more information. 5. On-Chip Peripheral Interrupts Conditions: SR.IMASK is lower than the on-chip module (TMU, RTC, SCI, SIOF, SCIF, A/D, DMAC, CPG, REF, PCC, USBH, USBF, LCDC, AFEIF) interrupt level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC value after the instruction at which the interrupt is accepted is saved to the SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR + H'0600. See section 7, Interrupt Controller (INTC), for more information. 6. H-UDI Interrupt Conditions: H-UDI interrupt command is input (see section 31.4.4, H-UDI Interrupt), the value of the interrupt mask bits of SR is lower than 15, and the BL bit in SR is 0, the interrupt is accepted at an instruction boundary. Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The SR at the point the interrupt is accepted is saved to the SSR. H'5E0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR + H'0600. See section 7, Interrupt Controller (INTC), for more information. 4.6 Usage Notes * Return from exception handling Check the BL bit in SR with software. When the SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. Issue an RTE instruction. Set the SPC in the PC and SSR in SR with the RTE instruction, branch to the SPC address, and return from exception handling. * Operation when exception or interrupt occurs while SR.BL = 1 Interrupt: Acceptance is suppressed until the BL bit in SR is set to 0 by software. If there is a request and the reception conditions are satisfied, the interrupt is accepted after the Rev. 5.00 Dec 12, 2005 page 147 of 1034 REJ09B0254-0500 Section 4 Exception Handling execution of the instruction that sets the BL bit in SR to 0. During the sleep or standby mode, however, the interrupt will be accepted even when the BL bit in SR is 1. NMI is accepted when BLMSK in ICR1 is 1, regardless of the setting of the BL bit. Exception: No user break point trap will occur even when the break conditions are met. When one of the other exceptions occurs, a branch is made to the fixed address of the reset (H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are undefined. * SPC when an Exception Occurs: The PC saved to the SPC when an exception occurs is as shown below: Re-executing-type exceptions: The PC of the instruction that caused the exception is set in the SPC and re-executed after return from exception handling. If the exception occurred in a delay slot, however, the PC of the immediately prior delayed branch instruction is set in the SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. Completed-type exceptions and interrupts: The PC of the instruction after the one that caused the exception is set in the SPC. If the exception was caused by a delayed conditional branch instruction, however, the branch destination PC is set in SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. * Initial register values after reset Undefined registers R0_BANK0/1 to R7_BANK0/1, R8 to R15, GBR, SPC, SSR, MACH, MACL, PR Initialized registers VBR = H'00000000 SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3 to SR.I0 = H'F. Other SR bits are undefined. PC = H'A0000000 * Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not guaranteed in this case. * When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address error does not occur at an LDC instruction that updates the SR register and the following instruction. This occurrence will be identified as multiple exceptions, and may initiate reset processing. Rev. 5.00 Dec 12, 2005 page 148 of 1034 REJ09B0254-0500 Section 5 Cache Section 5 Cache 5.1 5.1.1 Overview Features The cache specifications are listed in table 5.1. Table 5.1 Parameter Capacity Structure Locking Line size Number of entries Write system Replacement method Cache Specifications Specification 16 kbytes Instruction/data mixed, 4-way set associative Way 2 and way 3 are lockable 16 bytes 256 entries/way P0, P1, P3, U0: Write-back/write-through selectable Least-recently-used (LRU) algorithm 5.1.2 Cache Structure The cache mixes data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 4 kbytes (16 bytes x 256 entries), with a total of 16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure. Rev. 5.00 Dec 12, 2005 page 149 of 1034 REJ09B0254-0500 Section 5 Cache Address array (ways 0 to 3) Data array (ways 0 to 3) LRU Entry 0 V U Tag address Entry 1 . . . . . . 0 1 . . . . . . LW0 LW1 LW2 LW3 0 1 . . . . . . Entry 255 24 (1 + 1 + 22) bits 255 128 (32 x 4) bits LW0-LW3: Longword data 0 to 3 255 6 bits Figure 5.1 Cache Structure Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag holds the physical address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used for comparison during cache searches. In the SH7727, the top three of 32 physical address bits are used as shadow bits (see section 12, Bus State Controller (BSC)), and therefore in a normal replace operation the top three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. The tag address is not initialized by either a power-on or manual reset. Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11 to 4) can be registered in the cache. When an entry is registered, the LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way. In normal operation, four ways are used as cache and six LRU bits indicate the way to be replaced (table 5.2). If a bit pattern other than those listed in table 5.2 is set in the LRU bits by software, the Rev. 5.00 Dec 12, 2005 page 150 of 1034 REJ09B0254-0500 Section 5 Cache cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 5.2. The LRU bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. Table 5.2 LRU (5-0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 LRU and Way Replacement Way to be Replaced 3 2 1 0 5.1.3 Register Configuration Table 5.3 shows details of the cache control register. Table 5.3 Register Cache control register Cache control register 2 Register Configuration Abbr. CCR CCR2 R/W R/W W Size Longword Longword Initial Value H'00000000 H'00000000 Address H'FFFFFFEC H'040000B0 (H'A40000B0)* Note: * When address translation by the MMU does not apply, the address in parentheses should be used. 5.2 5.2.1 Register Description Cache Control Register (CCR) The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either writethrough mode or write-back mode). Programs that change the contents of the CCR register should be placed in address space that is not cached. Figure 5.2 shows the configuration of the CCR register. Rev. 5.00 Dec 12, 2005 page 151 of 1034 REJ09B0254-0500 Section 5 Cache 31 ... ... ... ... ... ... ... ... 6 5 4 3 CF 2 CB 1 WT 0 CE : CF: Reserved bits. These bits are always read as 0. The write value should always be 0. Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). Always reads 0. Write-back to external memory is not performed when the cache is flushed. Write-through bit. Indicates the cache's operating mode for areas P0, U0 and P3. 1 = write-through mode, 0 = write-back mode. Cache enable bit. Indicates whether the cache function is used. 1 = cache used, 0 = cache not used. Cache write-back bit. Indicates the cache's operating mode for area P1. 1 = write-back mode, 0 = write-through mode. WT: CE: CB: Figure 5.2 CCR Register Configuration 5.2.2 Cache Control Register 2 (CCR2) CCR2 register is used to enable or disable cache locking mechanism during DSP mode (CPU status register bit 12) only. Executing a prefetch instruction (PREF) during DSP mode will bring in one line size of data pointed by Rn to cache, according to the setting of CCR2 [9:8] (W3LOAD, W3LOCK) and [1:0] (W2LOAD, W2LOCK): When CCR2[9:8]=11, during DSP mode PREF @Rn will bring the data into way 3. When CCR2[9:8]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will place the data into the way pointed by LRU. When CCR2[1:0]=11, during DSP mode PREF @Rn will bring the data into way 2. When CCR2[1:0]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will place the data into the way pointed by LRU. CCR2 must be set before cache is enabled. When a PREF instruction is issued and there is a cache hit, the operation is treated as NOP. Figure 5.3 shows the configuration of the CCR2 register. The CCR2 register is a write-only register. If read, an undefined value will be returned. Rev. 5.00 Dec 12, 2005 page 152 of 1034 REJ09B0254-0500 Section 5 Cache 31 9 8 7 2 1 0 W3 W3 LOAD LOCK W2 W2 LOAD LOCK W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & DSP = 1, the prefetched data will always be loaded into Way2. In all other conditions the prefetched data will be loaded into the way pointed by LRU. W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit. When W3LOCK = 1 & W3LOAD = 1 & DSP = 1, the prefetched data will always be loaded into Way3. In all other conditions the prefetched data will be loaded into the way pointed by LRU. Note: W2LOAD and W3LOAD should not be set to high at the same time. Figure 5.3 CCR2 Register Configuration Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high the cache is locked. The locked data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be replaced by tables 5.4 to 5.6. Table 5.4 LRU (5-0) 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 LRU and Way Replacement (when W2LOCK=1) Way to be Replaced 3 1 0 Table 5.5 LRU (5-0) LRU and Way Replacement (when W3LOCK=1) Way to be Replaced 2 1 0 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 5.00 Dec 12, 2005 page 153 of 1034 REJ09B0254-0500 Section 5 Cache Table 5.6 LRU (5-0) LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) Way to be Replaced 1 0 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 5.3 5.3.1 Cache Operation Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.4 illustrates the method by which the cache is searched. The cache is a physical cache and holds physical addresses in its address section. Entries are selected using bits 11 to 4 of the address (virtual) of the access to memory and the address tag of that entry is read. In parallel to reading of the address tag, the logical address is translated to a physical address in the MMU. The physical address after translation and the physical address read from the address section are compared. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 5.4 shows a hit on way 1. Rev. 5.00 Dec 12, 2005 page 154 of 1034 REJ09B0254-0500 Section 5 Cache Virtual address 31 12 11 4 3 210 Entry selection Longword (LW) selection Ways 0 to 3 Ways 0 to 3 MMU 0 1 V U Tag address LW0 LW1 LW2 LW3 255 Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 5.4 Cache Search Scheme Rev. 5.00 Dec 12, 2005 page 155 of 1034 REJ09B0254-0500 Section 5 Cache 5.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The LRU is updated. Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one least recently used. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0 and the V bit is set to 1. In the write-back mode, when the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes back the entry to the memory. The write-back unit is 16 bytes. 5.3.3 Prefetch Operations Prefetch Hit: The LRU is updated so that the hit way becomes the most recent. Other cache contents are not updated. Instruction or data transfer to the CPU is not performed. Prefetch Miss: Instruction or data transfer to the CPU is not performed, and the way replaced is as shown in table 5.2, table 5.4, table 5.5, and table 5.6. Other operations are the same as in the case of a read miss. 5.3.4 Write Access Write Hit: In a write access in the write-back mode, the data is written to the cache and the U bit of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is issued. In the write-through mode, the data is written to the cache and an external memory write cycle is issued. Write Miss: In the write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. The way to be replaced is the one least recently used. When the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the writeback buffer. The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1 and the V bit is also set to 1. After the cache completes its update cycle, the write-back buffer writes back the entry to the memory. In the write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. Rev. 5.00 Dec 12, 2005 page 156 of 1034 REJ09B0254-0500 Section 5 Cache 5.3.5 Write-Back Buffer When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. During the write back cycles, the cache can be accessed. The write-back buffer can hold one line of the cache data (16 bytes) and its physical address. Figure 5.5 shows the configuration of the write-back buffer. PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31 to 4): Physical address written to external memory Longword 0 to 3: The line of cache data to be written to external memory Figure 5.5 Write-Back Buffer Configuration 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is accessed, the latest data may be in a write-back mode cache, so invalidate the entry that includes the latest data in the cache, generate a write back, and update the data in memory before using it. When the caching area is updated by a device other than the SH7727, invalidate the entry that includes the updated data in the cache. 5.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions in the privileged mode. The cache is mapped onto the P4 area in logical address space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 5.4.1 Address Array The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data Rev. 5.00 Dec 12, 2005 page 157 of 1034 REJ09B0254-0500 Section 5 Cache field specifies the address, V bit, U bit, and LRU bits to be written to the address array ((1) in figure 5.6). In the address field, specify the entry address selecting the entry (bits 11 to 4), W for selecting the way (bits 12 and 11: in normal mode (8-kbyte cache), 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), and H'F0 to indicate address array access (bits 31 to 24). When writing, specify bit 3 as the A bit. The A bit indicates whether addresses are compared during writing. When the A bit is 1, the addresses of four entries selected by the entry addresses are compared to the addresses to be written into the address array specified in the data field. Writing takes place to the way that has a hit. When a miss occurs, nothing is written to the address array and no operation occurs. The way number (W) specified in bits 12 and 11 is not used. When the A bit is 0, it is written to the entry selected with the entry address and way number without comparing addresses. The address specified by bits 31 to 10 in the data specification in figure 5.6 (1), address array access, is a logical address. When the MMU is enabled, the address is translated into a physical address, then the physical address is used in comparing addresses when the A bit is 1. The physical address is written into the address array. When reading, the address tag, V bit, U bit, and LRU bits of the entry specified by the entry address and way number (W) are read using the data format shown in figure 5.6 without comparing addresses. To invalidate a specific entry, specify the entry by its entry address and way number, and write 0 to its V bit. To invalidate only an entry for an address to be invalidated, specify 1 for the A bit. When an entry for which 0 is written to the V bit has a U bit set to 1, it will be written back. This allows coherency to be achieved between the external memory and cache by invalidating the entry. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. In the SH7727, the upper 3 bits of the 32-bit physical address are treated as a shadow field (see section 12, Bus State Controller (BSC)). Therefore, when a cache miss occurs, 0 is stored in the upper 3 bits of the address array address tag. When using an MOV instruction to modify the address array directly, a nonzero value must not be written to the upper 3 bits of the address tag. 5.4.2 Data Array The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array ((2) in figure 5.6). Rev. 5.00 Dec 12, 2005 page 158 of 1034 REJ09B0254-0500 Section 5 Cache Specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3), W for selecting the way (bits 12 and 11: in normal mode, 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), and H'F1 to indicate data array access (bits 31 to 24). Both reading and writing use the longword of the data array specified by the entry address, way number and longword address. The access size of the data array is fixed at longword. 1. Address array access Address specification Read access 31 24 23 14 13 12 11 4 3 2 0 1111 0000 *............* W Entry 0 * 0 0 Write access 31 24 23 14 13 12 11 4 3 2 0 1111 0000 *............* W Entry A * 0 0 Data specification 31 30 29 10 9 4 3 2 1 0 000 Address tag (31-10) LRU X X U V 2. Data array access (both read and write accesses) Address specification 31 24 23 14 13 12 11 4 3 2 1 0 1111 0001 *............* W Entry L 0 0 Data specification 31 0 Longword X: 0 for read, don't care for write *: Don't care bit Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access Rev. 5.00 Dec 12, 2005 page 159 of 1034 REJ09B0254-0500 Section 5 Cache 5.5 5.5.1 Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written when a match is found. If no match is found, there is no operation. R0 specifies the write data in R0 and R1 specifies the address. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. ; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0 ; R1=H'F0000088; address array access, entry=B'00001000, A=1 ; MOV.L R0,@R1 5.5.2 Reading the Data of a Specific Entry This example reads the data section of a specific cache entry. The longword indicated in the data field of the data array in figure 5.6 is read to the register. R0 specifies the address and R1 is read. ; R1=H'F100 004C; data array access, entry=B'00000100, Way = 0, ; longword address = 3 ; MOV.L @R0,R1 ; Longword 3 is read. Rev. 5.00 Dec 12, 2005 page 160 of 1034 REJ09B0254-0500 Section 6 X/Y Memory Section 6 X/Y Memory 6.1 Overview The SH7727 has on-chip X-RAM and Y-RAM. It can be used by CPU, DSP and DMAC to store instructions or data. 6.1.1 Features The X/Y Memory features are listed in table 6.1. Table 6.1 Parameter Addressing method X/Y Memory Specifications Features User selectable mapping mechanism * * Fixed mapping for mission-critical realtime applications (P2/Uxy area) Automatic mapping through TLB for easy to use (P0/P3/U0 area) Ports 3 independent read/write ports * * * 8-/16-/32-bit access from the CPU Maximum of two simultaneous 16-bit accesses, or 16/32-bit accesses, from the DSP 8-/16-/32-bit access from the DMAC Size 8-kbyte RAM for X and Y memory each Rev. 5.00 Dec 12, 2005 page 161 of 1034 REJ09B0254-0500 Section 6 X/Y Memory 6.2 X/Y Memory Access from the CPU The X/Y memory can be located in either map-enabled area or fixed-mapped area, depending on the mode bit (MD) and DSP bit (DSP) setting in the status register (SR). Figure 6.1 shows X/Y memory logical mapping. 1. Privileged Mode MD = 1, DSP = 0; Any physical address in space P0 or P3 can map to X/Y memory through TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can also fixed map to X/Y memory. Since the DSP extension is disabled, the DSP instruction set and registers are not available to the programmer. 2. User Mode MD = 0, DSP = 0; Any physical address in the U0 space can access X/Y memory through TLB translation. Any access to addresses beyond the U0 space will cause an address error. Since the DSP extension is disabled, the DSP instruction set and registers are not available to the programmer. 3. Privileged-DSP Mode MD = 1, DSP = 1; Any physical address in space P0 or P3 can map to X/Y memory through TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can also fixed-map to X/Y memory. Since the DSP extension is enabled, the DSP instruction set and registers are available to the programmer. 4. User-DSP Mode MD = 0, DSP = 1; Any physical address in space U0 can map to X/Y memory through TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the Uxy spaces can also fixed map to X/Y memory. Any access to outside of U0 and Uxy space will cause an address error. Since the DSP extension is enabled, the DSP instruction set and registers are available to the programmer. It is recommended that for the mappable area, the C (cacheable) bit in the TLB entry must be set to 0 to guarantee a two-cycle access. Mapping through TLB translation provides a flexible X/Y memory addressing scheme but takes two cycles even when the C bit in the TLB entry is cleared to 0. Fixed mapping provides a onecycle access for read and two-cycle access for write, which is the appropriate method for missioncritical realtime operations. Rev. 5.00 Dec 12, 2005 page 162 of 1034 REJ09B0254-0500 Section 6 X/Y Memory The X/Y memory resides on the second 16 MB of physical address space area 1, from H'A500 0000 to H'A5FF FFFF. These 16-MB address spaces are shadowed and maps to the same 128kbyte X/Y ROM/RAM. Figures 6.1 and 6.2 show X/Y memory physical mapping. MD = 1, DSP = 0 Privileged mode MD = 0, DSP = 0 User mode P0 Same as SH-3 In MD = 1, CPU can change DSP bit U0 Same as SH-3 In MD = 0, user cannot change DSP bit P1 P2 P3 P4 Address error MD = 1, DSP = 1 Privileged DSP mode MD = 0, DSP = 1 User DSP mode P0 In MD = 1, CPU can change DSP bit X Y U0 X Address error Y P1 P2 P3 P4 Address range From H'A500 0000 To H'A5FF FFFF Address error Uxy: Address range From H'A500 0000 To H'A5FF FFFF Figure 6.1 X/Y Memory Logical Address Mapping Rev. 5.00 Dec 12, 2005 page 163 of 1034 REJ09B0254-0500 Section 6 X/Y Memory Area 1, 64 Mbytes 4000000 I/O register space 16 Mbytes A5007000 5000000 5020000 X/Y Memory 6000000 A5008FFF Reserved space 16 Mbytes A5010000 A5000000 128-kbyte X/Y Memory X-ROM/X-RAM Reserved space X-RAM, 8 kbytes X-ROM/X-RAM Reserved space Y-ROM/Y-RAM Reserved space Reserved area 32 Mbytes A5017000 A5018FFF Y-RAM, 8 kbytes Y-ROM/Y-RAM Reserved space 7FFFFFF A501FFFF Figure 6.2 X/Y Memory Physical Address Mapping 6.3 X/Y Memory Access from the DSP The X/Y memory can be accessed by the DSP through the X bus and Y bus. Accesses via the X bus/Y bus are always 16-bit, while accesses via the L bus are either 16-bit or 32-bit. Accesses via the X bus and Y bus cannot be specified simultaneously. 6.4 X/Y Memory Access from the DMAC The X/Y memory also exists on the I bus and can be accessed by the DMAC. The DMAC access is 8-/16-/32-bit unit. If the I bus accesses X/Y memory simultaneously with an access from X bus/Y bus or L bus, the I bus master has a higher priority. To access the X/Y memory by the DMAC, the physical address from H'05000000 to H'0501FFFF should be used. Rev. 5.00 Dec 12, 2005 page 164 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Section 7 Interrupt Controller (INTC) 7.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 7.1.1 Features INTC has the following features: * 16 levels of interrupt priority can be set: By setting the five interrupt-priority registers, the priorities of on-chip supporting module, IRQ, and PINT interrupts can be selected from 16 levels for individual request sources. * NMI noise canceller function: NMI input-level bit indicates NMI pin states. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceller. Rev. 5.00 Dec 12, 2005 page 165 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.1.2 Block Diagram Figure 7.1 is a block diagram of the INTC. NMI IRL3 to IRL0 IRQ0 to IRQ5 PINT0 to PINT15 4 6 16 Input control Interrupt request SR 3210 Priority identifier (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) CPU PCC LCDC USBH USBF AFE DMAC SIOF SCIF SCI ADC TMU RTC WDT REF H-UDI (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (refresh request) (Interrupt request) Comparator ICR IPR IPRA to IPRG Internal bus Bus interface INTC Legend: TMU: RTC: SCI: SCIF: WDT: REF: ICR: IPRA to IPRG: SR: Timer unit Realtime clock unit Serial communication interface Serial communication interface (with FIFO) Watchdog timer Refresh requests in the bus state controller Interrupt control register Registers A-E for setting the interrupt proprity levels Status register DMAC: ADC: H-UDI: PCC: LCDC: USBH: USBF: AFE: SIOF: Direct memory access controller Analog-to-digital converter Hitachi user-debugging interface PCMCIA controller LCD controller USB host USB function controller AFE interface Serial IO Figure 7.1 INTC Block Diagram Rev. 5.00 Dec 12, 2005 page 166 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.1.3 Pin Configuration Table 7.1 lists the INTC pin configuration. Table 7.1 Name Nonmaskable interrupt input pin Interrupt input pins Port interrupt input pins Pin Configuration Abbreviation NMI IRQ5 to IRQ0 IRL3 to IRL0 PINT0 to PINT15 I/O I I I Description Input of interrupt request signal, which is nonmaskable by SR.IMASK Input of interrupt request signals, which is maskable by SR.IMASK Port input of interrupt request signals, which is maskable by SR.IMASK 7.1.4 Register Configuration The INTC has 17 registers listed in table 7.2. Rev. 5.00 Dec 12, 2005 page 167 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Table 7.2 Name Register Configuration Abbr. ICR0 ICR1 ICR2 ICR3 PINTER IPRA IPRB IPRC IPRD IPRE IPRF IPRG IRR0 IRR1 IRR2 IRR3 IRR4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R Initial 1 Value* *2 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'00 H'00 H'00 H'00 Address H'FFFFFEE0 H'04000010 3 (H'A4000010)* H'04000012 3 (H'A4000012)* H'04000228 3 (H'A4000228)* H'04000014 3 (H'A4000014)* H'FFFFFEE2 H'FFFFFEE4 H'04000016 3 (H'A4000016)* H'04000018 3 (H'A4000018)* H'0400001A 3 (H'A400001A)* H'04000220 3 (H'A4000220)* H'04000222 3 (H'A4000222)* H'04000004 3 (H'A4000004)* H'04000006 3 (H'A4000006)* H'04000008 3 (H'A4000008)* H'04000224 3 (H'A4000224)* H'04000226 3 (H'A4000226)* Access Size 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 16 16 Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 PINT interrupt enable register Interrupt priority level setting register A Interrupt priority level setting register B Interrupt priority level setting register C Interrupt priority level setting register D Interrupt priority level setting register E Interrupt priority level setting register F Interrupt priority level setting register G Interrupt request register 0 Interrupt request register 1 Interrupt request register 2 Interrupt request register 3 Interrupt request register 4 Notes: 1. Initialized by a power-on or manual reset. 2. H'8000 when the NMI pin is at high level. H'0000 when the NMI pin is at low level. 3. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 168 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.2 Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL, PINT, and on-chip supporting modules. Each interrupt has priority levels (0 to 16) with 0 the lowest and 16 the highest. Priority level 0 masks an interrupt. 7.2.1 NMI Interrupts The NMI interrupt has the highest priority level of 16. When the BLMSK bit of the interrupt control register (ICR1) is 1 or the BL bit of the status register (SR) is 0, NMI interrupts are accepted when the MAI bit of the ICR1 register is 0. NMI interrupts are edge-detected. In sleep or standby mode, the interrupt is accepted regardless of the BL. The NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) is used to select either the rising or falling edge. When the NMIE bit of the ICR0 register is changed, the NMI interrupt is not detected for 20 cycles after changing the ICR0.NMIE to avoid a false detection of the NMI interrupt. NMI interrupt exception handling does not affect the interrupt mask level bits (I3 to I0) in the status register (SR). When the BLMSK bit of the ICR1 register is set to 1 and only NMI interrupts are accepted, the SPC register and SSR register are updated by the NMI interrupt handler, making it impossible to return to the original processing from exception handling initiated prior to the NMI. Use should therefore be restricted to cases where return is not necessary. It is possible to wake the chip up from the standby state with an NMI interrupt (except when the MAI bit of the ICR1 register is set to 1). 7.2.2 IRQ Interrupt IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority level can be set by priority setting registers C, D (IPRC, IPRD) in a range from levels 0 to 15. When using edge sensing for IRQ interrupts, do the following to clear IR0. To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared; write 1 to the other bits. The values of the bits to which 1 is written do not change. When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to IRQ0R alone. Rev. 5.00 Dec 12, 2005 page 169 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0). It is necessary for an edge input interrupt detection to input a pulse width more than two-cycle width by P clock basis. With level detection, the level must be maintained until the interrupt is accepted and the CPU starts interrupt handling. The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by IRQ interrupt processing. Interrupts IRQ5 to IRQ0 can be used to wake the chip up from the software standby mode (but only when the RTC 32 kHz oscillator is used). In this case, the priority level of the interrupt to be used must be higher than the level of bits I3 to I0 in the SR register. Notes: The following cautions apply when IRQ edge detection is used: 1. If an IRQ edge is input immediately before the CPU enters the standby mode (between when the CPU executes the SLEEP instruction and when STATUS0 goes high), the interrupt may not be detected properly. After this, if the IRQ edge is input again after STATUS0 goes high, the interrupt will be detected. 2. If an IRQ edge is input while the frequency is changing due to a change in the value of the STC bit in the FRQCR register (during the count by WDT), the interrupt may not be detected properly. If the IRQ edge is input again after the WDT count completes, the interrupt will be detected. 7.2.3 IRL Interrupts IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the higher level indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). Figure 7.2 shows an example of an IRL interrupt connection. Table 7.3 shows IRL pins and interrupt levels. Rev. 5.00 Dec 12, 2005 page 170 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) SH7727 Interrupt request Priority encoder 4 IRL3 to IRL0 IRL3 to IRL0 Figure 7.2 Example of IRL Interrupt Connection Table 7.3 IRL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IRL3 to IRL0 Pins and Interrupt Levels IRL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request Level 7 interrupt request Level 6 interrupt request Level 5 interrupt request Level 4 interrupt request Level 3 interrupt request Level 2 interrupt request Level 1 interrupt request No interrupt request A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that no transient level on the IRL pin change is detected. In the standby mode, as the peripheral clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead. Therefore Rev. 5.00 Dec 12, 2005 page 171 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) when the RTC is not used, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt processing starts. Correct operation cannot be guaranteed if the level is not maintained. However, the priority level can be changed to a higher one. The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRL interrupt processing. 7.2.4 PINT Interrupt PINT interrupts are input by priority from pins PINT0 to PINT15 with a level. The priority level can be set by priority setting registers D (IPRD) in a range from levels 0 to 15, in the unit of PINT0 to PINT7 or PINT8 to PINT15. The PINT interrupt level should be held until the interrupt is accepted and interrupt handling is started. The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by PINT interrupt processing. PINT interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator is used). 7.2.5 On-Chip Supporting Module Interrupts On-chip supporting module interrupts are generated by the following fourteen modules: * Timer unit (TMU) * Realtime clock (RTC) * Serial communication interface (SCI, SCIF) * Bus state controller (BSC) * Watchdog timer (WDT) * Direct memory access controller (DMAC) * Analog-to-digital converter (ADC) * PC Card controller (PCC) * OHCI compliant USB HOST controller (USBH) * USB function controller (USBF) * AFE interface (AFEIF) Rev. 5.00 Dec 12, 2005 page 172 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) * LCD controller (LCDC) * Hitachi user-debugging interface (H-UDI) * Serial IO (SIOF) Not every interrupt source is assigned a different interrupt vector. Sources are reflected on the interrupt event register (INTEVT and INTEVT2). It is easy to identify sources by using the values of the INTEVT or INTEVT2 register as branch offsets. The priority level (from 0 to 15) can be set for each module except for H-UDI by writing to the interrupt priority setting registers A to G (IPRA to IPRG). The priority level of H-UDI interrupt is 15 (fixed). The interrupt mask bits (I3 to I0) of the status register are not affected by the on-chip supporting module interrupt processing. TMU and RTC interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator is used). 7.2.6 Interrupt Exception Handling and Priority Tables 7.4 and 7.5 list the codes for the interrupt event register (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned unique code. The start address of the interrupt service routine is common to each interrupt source. This is why, for instance, the value of INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to identify the interrupt source. The order of priority of the on-chip supporting module, IRQ, and PINT interrupts is set within the priority levels 0 to 15 at will by using the interrupt priority level set to registers A to G (IPRA to IPRG). The order of priority of the on-chip supporting module, IRQ, and PINT interrupts is set to zero by RESET. When the order of priorities for multiple interrupt sources are set to the same level and such interrupts are generated at the same time, they are processed according to the default order listed in tables 7.4 and 7.5. Rev. 5.00 Dec 12, 2005 page 173 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Priority IPR (Bit (Initial Value) Numbers) 16 15 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) -- -- IPRC (3-0) IPRC (7-4) IPRC (11-8) IPRC (15-12) IPRD (3-0) IPRD (7-4) IPRD (15-12) IPRD (11-8) IPRE (15-12) Priority within IPR Setting Default Priority Unit -- -- -- -- -- -- -- -- -- -- High High Interrupt Source NMI H-UDI IRQ IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 PINT DMAC PINT0-7 PINT8-15 DEI0 DEI1 DEI2 DEI3 SCIF ERI2 RXI2 BRI2 TXI2 ADC LCDC SIOF ADI LCDCI SIFERI SIFTXI SIFRXI SIFCCI USBH USBF AFEIF USBHI USBFI0 USBFI1 AFEIFI INTEVT Code (INTEVT2 Code) H'1C0 (H'1C0) H'5E0 (H'5E0) H'200-3C0* (H'600) H'200-3C0* (H'620) H'200-3C0* (H'640) H'200-3C0* (H'660) H'200-3C0* (H'680) H'200-3C0* (H'6A0) H'200-3C0* (H'700) H'200-3C0* (H'720) H'200-3C0* (H'800) H'200-3C0* (H'820) H'200-3C0* (H'840) H'200-3C0* (H'860) H'200-3C0* (H'900) H'200-3C0* (H'920) H'200-3C0* (H'940) H'200-3C0* (H'960) H'200-3C0* (H'980) H'200-3C0* (H'9A0) H'200-3C0* (H'B00) H'200-3C0* (H'B20) H'200-3C0* (H'B40) H'200-3C0* (H'B60) H'200-3C0* (H'A00) H'200-3C0* (H'A20) H'200-3C0* (H'A40) Low 0-15 (0) IPRE (7-4) High Low 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) IPRG(15-12) IPRG(11-8) IPRG(7-4) IPRG(3-0) Low -- High Low -- Low IPRE (3-0) IPRF(11-8) IPRF(3-0) -- -- High H'200-3C0* (H'A 60) 0-15 (0) Rev. 5.00 Dec 12, 2005 page 174 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Priority within IPR Setting Default Priority Unit High High Interrupt Source PCC0 PC0IRIR PC0SCIR PC0CDIR PC0RCIR PC0BDIR TMU0 TMU1 TMU2 RTC TUNI0 TUNI1 TUNI2 ATI PRI CUI SCI0 ERI RXI TXI TEI WDT REF ITI RCMI ROVI INTEVT Code (INTEVT2 Code) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'400 (H'400) H'420 (H'420) H'440 (H'440) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) H'560 (H'560) H'580 (H'580) H'5A0 (H'5A0) Interrupt Priority IPR (Bit (Initial Value) Numbers) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) IPRA (15-12) IPRA (11-8) IPRA (7-4) IPRA (3-0) IPRF(7-4) PC0SWIR H'200-3C0* (H'9C0) PC0BWIR H'200-3C0* (H'9C0) Low -- -- -- High Low 0-15 (0) IPRB (7-4) High Low 0-15 (0) 0-15 (0) IPRB (15-12) IPRB (11-8) -- High Low Low Note: * The code corresponding to an interrupt level shown in table 7.6 is set. Rev. 5.00 Dec 12, 2005 page 175 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Table 7.5 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Priority (Initial IPR (Bit Numbers) Value) 16 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IPRD (3-0) IPRD (7-4) IPRD (11-8) Priority within IPR Setting Default Priority Unit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- High Interrupt Source NMI H-UDI IRL IRL(3:0) = 0000 IRL(3:0) = 0001 IRL(3:0) = 0010 IRL(3:0) = 0011 IRL(3:0) = 0100 IRL(3:0) = 0101 IRL(3:0) = 0110 IRL(3:0) = 0111 IRL(3:0) = 1000 IRL(3:0) = 1001 IRL(3:0) = 1010 IRL(3:0) = 1011 IRL(3:0) = 1100 IRL(3:0) = 1101 IRL(3:0) = 1110 IRQ PINT DMAC IRQ4 IRQ5 PINT0-7 PINT8-15 DEI0 DEI1 DEI2 DEI3 SCIF ERI2 RXI2 BRI2 TXI2 INTEVT Code (INTEVT2 Code) H'1C0 (H'1C0) H'5E0 (H'5E0) H'200 (H'200) H'220 (H'220) H'240 (H'240) H'260 (H'260) H'280 (H'280) H'2A0 (H'2A0) H'2C0 (H'2C0) H'2E0 (H'2E0) H'300 (H'300) H'320 (H'320) H'340 (H'340) H'360 (H'360) H'380 (H'380) H'3A0 (H'3A0) H'3C0 (H'3C0) H'200-3C0* (H'680) H'200-3C0* (H'6A0) H'200-3C0* (H'700) H'200-3C0* (H'720) H'200-3C0* (H'800) H'200-3C0* (H'820) H'200-3C0* (H'840) H'200-3C0* (H'860) H'200-3C0* (H'900) H'200-3C0* (H'920) H'200-3C0* (H'940) H'200-3C0* (H'960) IPRD (15-12) -- IPRE (15-12) High Low 0-15 (0) IPRE (7-4) High Low Low Rev. 5.00 Dec 12, 2005 page 176 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Interrupt Priority (Initial IPR (Bit Numbers) Value) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) 0-15 (0) IPRA (11-8) IPRA (7-4) IPRA (3-0) Low IPRA (15-12) -- -- -- High Low 0-15 (0) IPRB (7-4) High IPRG (11-8) IPRG (7-4) IPRG (3-0) IPRF (7-4) Low IPRG (15-12) -- High Low -- High IPRE (3-0) IPRF (11-8) IPRF (3-0) Priority within IPR Setting Default Priority Unit -- -- High High Interrupt Source ADC LCDC SIOF ADI LCDCI SIFERI SIFTXI SIFRXI SIFCCI USBH USBF AFEIF PCC0 USBHI USBFI0 USBFI1 AFEIFI PC0SWIR PC0IRIR PC0SCIR PC0CDIR PC0RCIR PC0BWIR PC0BDIR TMU0 TMU1 TMU2 RTC TUNI0 TUNI1 TUNI2 ATI PRI CUI SCI0 ERI RXI TXI TEI WDT REF ITI RCMI ROVI INTEVT Code (INTEVT2 Code) H'200-3C0* (H'980) H'200-3C0* (H'9A0) H'200-3C0* (H'B00) H'200-3C0* (H'B20) H'200-3C0* (H'B40) H'200-3C0* (H'B60) H'200-3C0* (H'A00) H'200-3C0* (H'A20) H'200-3C0* (H'A40) H'200-3C0* (H'A60) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'200-3C0* (H'9C0) H'400 (H'400) H'420 (H'420) H'440 (H'440) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) H'560 (H'560) H'580 (H'580) H'5A0 (H'5A0) Low 0-15 (0) 0-15 (0) IPRB (15-12) -- IPRB (11-8) High Low Low Note: * The code corresponding to an interrupt level shown in table 7.6 is set. Rev. 5.00 Dec 12, 2005 page 177 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Table 7.6 Interrupt Level and INTEVT Code INTEVT Code H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Interrupt level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Rev. 5.00 Dec 12, 2005 page 178 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.3 7.3.1 INTC Registers Interrupt Priority Registers A to G (IPRA to IPRG) Interrupt priority registers A to G (IPRA to IPRG) are 16-bit read/write registers that set priority levels from 0 to 15 for on-chip supporting module, IRQ, and PINT interrupts. These registers are initialized to H'0000 at power-on reset, and manual reset, but are not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W Table 7.7 lists the relationship between the interrupt sources and the IPRA to IPRG bits. Table 7.7 Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG Interrupt Request Sources and IPRA to IPRG Bits 15 to 12 TMU0 WDT IRQ3 PINT0 to PINT7 DMAC Reserved* USBH Bits 11 to 8 TMU1 REF IRQ2 PINT8 to PINT15 Reserved* LCDC USBF0 Bits 7 to 4 TMU2 SCI IRQ1 IRQ5 SCIF PCC0 USBF1 Bits 3 to 0 RTC Reserved* IRQ0 IRQ4 ADC SIOF AFEIF Note: * Always read as 0. Only 0 should be written in. As listed in table 7.7, four sets of on-chip supporting modules or IRQ or PINT interrupts are assigned to each register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is priority level 15 (the highest level). A reset initializes IPRA to IPRG to H'0000. Rev. 5.00 Dec 12, 2005 page 179 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.3.2 Interrupt Control Register 0 (ICR0) The ICR0 is a register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. This register is initialized to H'0000 or H'8000 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 NMIL 0/1* R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 NMIE 0 R/W 0 -- 0 R Note: * When NMI input is high: 1; when NMI input is low: 0. Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Bit 15: NMIL 0 1 Description NMI input level is low NMI input level is high Bit 8--NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt request signal to the NMI is detected. Bit 8: NMIE 0 1 Description Interrupt request is detected on the falling edge of NMI input Interrupt request is detected on rising edge of NMI input (Initial value) Bits 14 to 9 and 7 to 0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Dec 12, 2005 page 180 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.3.3 Interrupt Control Register 1 (ICR1) The ICR1 is a 16-bit register that specifies the detection mode to external interrupt input pins, IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register, initialized to H'4000 at power-on reset or manual reset, is not initialized in the standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 MAI 0 R/W 7 0 R/W 14 1 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 -- 0 -- 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W IRQLVL BLMSK IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Bit 15--Mask All Interrupts (MAI): Masks NMI interrupts in standby mode when set to 1. Also selects whether or not all interrupt requests are masked when a low level is being input to the NMI pin. Bit 15: MAI 0 1 Description All interrupt requests are not masked while NMI pin is receiving low-level input (Initial value) All interrupt requests are masked while NMI pin is receiving low-level input Bit 14--Interrupt Request Level Detect (IRQLVL): Selects whether the IRQ3 to IRQ0 pins are used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3 to IRL0. Bit 14: IRQLVL Description 0 1 Used as four independent interrupt request pins IRQ3 to IRQ0 Used as encoded 15-level interrupt pins as IRL3 to IRL0 (Initial value) Bit 13--BL Bit Mask (BLMSK): Specifies whether NMI interrupts are masked when the BL bit of the SR register is 1. Rev. 5.00 Dec 12, 2005 page 181 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 13: BLMSK Description 0 1 NMI interrupts are masked when the BL bit is 1 NMI interrupts are accepted regardless of the BL bit setting (Initial value) Bit 12--Reserved: This bit is always read as 0. The write value should always be 0. Bits 11 and 10--IRQ5 Sense Select (IRQ51S and IRQ50S): Select whether the interrupt signal to the IRQ5 pin is detected at the rising edge, at the falling edge, or at low level. Bit 11: IRQ51S Bit 10: IRQ50S Description 0 0 1 1 0 1 An interrupt request is detected at IRQ5 input falling edge (Initial value) An interrupt request is detected at IRQ5 input rising edge An interrupt request is detected at IRQ5 input low level Reserved Bits 9 and 8--IRQ4 Sense Select (IRQ41S and IRQ40S): Select whether the interrupt signal to the IRQ4 pin is detected at the rising edge, at the falling edge, or at low level. Bit 9: IRQ41S 0 Bit 8: IRQ40S 0 1 1 0 1 Description An interrupt request is detected at IRQ4 input falling edge (Initial value) An interrupt request is detected at IRQ4 input rising edge An interrupt request is detected at IRQ4 input low level Reserved Bits 7 and 6--IRQ3 Sense Select (IRQ31S and IRQ30S): Select whether the interrupt signal to the IRQ3 pin is detected at the rising edge, at the falling edge, or at low level. Bit 7: IRQ31S 0 Bit 6: IRQ30S 0 1 1 0 1 Description An interrupt request is detected at IRQ3 input falling edge (Initial value) An interrupt request is detected at IRQ3 input rising edge An interrupt request is detected at IRQ3 input low level Reserved Rev. 5.00 Dec 12, 2005 page 182 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bits 5 and 4--IRQ2 Sense Select (IRQ21S and IRQ20S): Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge, or at low level. Bit 5: IRQ21S 0 Bit 4: IRQ20S 0 1 1 0 1 Description An interrupt request is detected at IRQ2 input falling edge (Initial value) An interrupt request is detected at IRQ2 input rising edge An interrupt request is detected at IRQ2 input low level Reserved Bits 3 and 2--IRQ1 Sense Select (IRQ11S and IRQ10S): Select whether the interrupt signal to the IRQ1 pin is detected at the rising edge, at the falling edge, or at low level. Bit 3: IRQ11S 0 Bit 2: IRQ10S 0 1 1 0 1 Description An interrupt request is detected at IRQ1 input falling edge (Initial value) An interrupt request is detected at IRQ1 input rising edge An interrupt request is detected at IRQ1 input low level Reserved Bits 1 and 0--IRQ0 Sense Select (IRQ01S and IRQ00S): Select whether the interrupt signal to the IRQ0 pin is detected at the rising edge, at the falling edge, or at low level. Bit 1: IRQ01S 0 Bit 0: IRQ00S 0 1 1 0 1 Description An interrupt request is detected at IRQ0 input falling edge (Initial value) An interrupt request is detected at IRQ0 input rising edge An interrupt request is detected at IRQ0 input low level Reserved Rev. 5.00 Dec 12, 2005 page 183 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.3.4 Interrupt Control Register 2 (ICR2) The ICR2 is a 16-bit read/write register that sets the detection mode to external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W PINT15S PINT14S PINT13S PINT14S PINT11S PINT10S PINT9S PINT8S PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S Bits 15 to 0--PINT15 to PINT0 Sense Select (PINT15S to PINT0S): Select whether interrupt request signals to PINT15 to PINT0 are detected at low levels or high levels. Bits 15 to 0: PINT15S to PINT0S 0 1 Description Interrupt requests are detected at low level input to the PINT pins (Initial value) Interrupt requests are detected at high level input to the PINT pins Rev. 5.00 Dec 12, 2005 page 184 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.3.5 Interrupt Control Register 3 (ICR3) The ICR3 is a 16-bit read/write register that sets the mask to PC Card controller. This register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R/W 7 -- 0 R/W 14 0 R/W 6 -- 0 R/W 13 0 R/W 5 -- 0 R/W 12 0 R/W 4 -- 0 R/W 11 0 R/W 3 -- 0 R/W 10 0 R/W 2 -- 0 R/W 9 0 R/W 1 -- 0 R/W 8 0 R/W 0 -- 0 R/W PC0SWIM PC0IRIM PC0SCIM PC0CDIM PC0RCIM PC0BWIM PC0BDIM Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. Bit 14--PC0SWIM: PC Card controller0 SWI mask. Bit 14: PC0SWIM 0 1 Description Interrupt requests is masked Interrupt requests is not masked (Initial value) Bit 13--PC0IRIM: PC Card controller0 IRI mask. Bits 13: PC0IRIM 0 1 Description Interrupt requests is masked Interrupt requests is not masked (Initial value) Bit 12--PC0SCIM: PC Card controller0 SCI mask. Bit 12: PC0SCIM 0 1 Description Interrupt requests is masked Interrupt requests is not masked (Initial value) Rev. 5.00 Dec 12, 2005 page 185 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 11--PC0CDIM: PC Card controller0 CDI mask. Bit 11: PC0CDIM 0 1 Description Interrupt requests is masked Interrupt requests is not masked (Initial value) Bit 10--PC0RCIM: PC Card controller0 RCI mask. Bit 10: PC0RCIM 0 1 Description Interrupt requests is masked Interrupt requests is not masked (Initial value) Bit 9--PC0BWIM: PC Card controller0 BWI mask. Bit 9: PC0BWIM 0 1 Description Interrupt requests is masked Interrupt requests is not masked (Initial value) Bit 8--PC0BDIM: PC Card controller0 BDI mask. Bit 8: PC0BDIM 0 1 Description Interrupt requests is masked Interrupt requests is not masked (Initial value) Bits 7 to 0-- Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Dec 12, 2005 page 186 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.3.6 PINT Interrupt Enable Register (PINTER) The PINTER is a 16-bit read/write register that enables interrupt requests input to external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT8E PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E Bits 15 to 0--PINT15 to PINT0 Interrupt Enable (PINT15E to PINT0E): Enable whether the interrupt requests input to the PINT15 to PINT0 pins. Bits 15 to 0: PINT15E to PINT0E 0 1 Description Disables PINT input interrupt requests Enables PINT input interrupt requests (Initial value) When all or some of these pins, PINT0 to PINT15 are not used as an interrupt input, a bit corresponding to a pin unused as an interrupt request should be set to 0. 7.3.7 Interrupt Request Register 0 (IRR0) The IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. This register is initialized to H'00 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: 7 0 R 6 0 R 5 IRQ5R 0 R/W 4 IRQ4R 0 R/W 3 IRQ3R 0 R/W 2 IRQ2R 0 R/W 1 IRQ1R 0 R/W 0 IRQ0R 0 R/W PINT0R PINT1R Rev. 5.00 Dec 12, 2005 page 187 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) When using edge sensing for IRQ interrupts, do the following to clear IR0. To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared; write 1 to the other bits. The values of the bits to which 1 is written do not change. When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to IRQ0R alone. Bit 7--PINT0 to PINT7 Interrupt Request (PINT0R): Indicates whether interrupt requests are input to PINT0 to PINT7 pins. Bit 7: PINT0R 0 1 Description Interrupt requests are not input to PINT0 to PINT7 pins Interrupt requests are input to PINT0 to PINT7 pins. (Initial value) Bit 6--PINT8 to PINT15 Interrupt Request (PINT1R): Indicates whether interrupt requests are input to PINT8 to PINT15 pins. Bit 6: PINT1R 0 1 Description Interrupt requests are not input to PINT8 to PINT15 pins Interrupt requests are input to PINT8 to PINT15 pins. (Initial value) Bit 5--IRQ5 Interrupt Request (IRQ5R): Indicates whether an interrupt request is input to the IRQ5 pin. When edge detection mode is set for IRQ5, an interrupt request is cleared by clearing the IRQ5R bit. Bit 5: IRQ5R 0 1 Description An interrupt request is not input to IRQ5 pin An interrupt request is input to IRQ5 pin (Initial value) Rev. 5.00 Dec 12, 2005 page 188 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 4--IRQ4 Interrupt Request (IRQ4R): Indicates whether an interrupt request is input to the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing the IRQ4R bit. Bit 4: IRQ4R 0 1 Description An interrupt request is not input to IRQ4 pin An interrupt request is input to IRQ4 pin (Initial value) Bit 3--IRQ3 Interrupt Request (IRQ3R): Indicates whether an interrupt request is input to the IRQ3 pin. When edge detection mode is set for IRQ3, an interrupt request is cleared by clearing the IRQ3R bit. Bit 3: IRQ3R 0 1 Description An interrupt request is not input to IRQ3 pin An interrupt request is input to IRQ3 pin (Initial value) Bit 2--IRQ2 Interrupt Request (IRQ2R): Indicates whether an interrupt request is input to the IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by clearing the IRQ2R bit. Bit 2: IRQ2R 0 1 Description An interrupt request is not input to IRQ2 pin An interrupt request is input to IRQ2 pin (Initial value) Bit 1--IRQ1 Interrupt Request (IRQ1R): Indicates whether an interrupt request is input to the IRQ1 pin. When edge detection mode is set for IRQ1, an interrupt request is cleared by clearing the IRQ1R bit. Bit 1: IRQ1R 0 1 Description An interrupt request is not input to IRQ1 pin An interrupt request is input to IRQ1 pin (Initial value) Bit 0--IRQ0 Interrupt Request (IRQ0R): Indicates whether an interrupt request is input to the IRQ0 pin. When edge detection mode is set for IRQ0, an interrupt request is cleared by clearing the IRQ0R bit. Rev. 5.00 Dec 12, 2005 page 189 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 0: IRQ0R 0 1 Description An interrupt request is not input to IRQ0 pin An interrupt request is input to IRQ0 pin (Initial value) 7.3.8 Interrupt Request Register 1 (IRR1) The IRR1 is an 8-bit read-only register that indicates whether DMAC or interrupt requests are generated. This register is initialized to H'00 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 DEI3R 0 R 2 DEI2R 0 R 1 DEI1R 0 R 0 DEI0R 0 R Bits 7 to 4--Reserved: These bits are always read as 0. The write value should always be 0. Bit 3--DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request is generated. Bit 3: DEI3R 0 1 Description A DEI3 interrupt request is not generated A DEI3 interrupt request is generated (Initial value) Bit 2--DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request is generated. Bit 2: DEI2R 0 1 Description A DEI2 interrupt request is not generated A DEI2 interrupt request is generated (Initial value) Bit 1--DEI1 Interrupt Request (DEI1R): Indicates whether a DEI1 (DMAC) interrupt request is generated. Bit 1: DEI1R 0 1 Description A DEI1 interrupt request is not generated A DEI1 interrupt request is generated (Initial value) Rev. 5.00 Dec 12, 2005 page 190 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 0--DEI0 Interrupt Request (DEI0R): Indicates whether a DEI0 (DMAC) interrupt request is generated. Bit 0: DEI0R 0 1 Description A DEI0 interrupt request is not generated A DEI0 interrupt request is generated (Initial value) 7.3.9 Interrupt Request Register 2 (IRR2) The IRR2 is an 8-bit read-only register that indicates whether A/D converter, or SCIF interrupt requests are generated. This register is initialized to H'00 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 ADIR 0 R 3 TXI2R 0 R 2 BRI2R 0 R 1 RXI2R 0 R 0 ERI2R 0 R Bits 7 to 5--Reserved: These bits are always read as 0. The write value should always be 0. Bit 4--ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request is generated. Bit 4: ADIR 0 1 Description An ADI interrupt request is not generated An ADI interrupt request is generated (Initial value) Bit 3--TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request is generated. Bit 3: TXI2R 0 1 Description A TXI2 interrupt request is not generated A TXI2 interrupt request is generated (Initial value) Rev. 5.00 Dec 12, 2005 page 191 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 2--BRI2 Interrupt Request (BRI2R): Indicates whether a BRI2 (SCIF) interrupt request is generated. Bit 2: BRI2R 0 1 Description A BRI2 interrupt request is not generated A BRI2 interrupt request is generated (Initial value) Bit 1--RXI2 Interrupt Request (RXI2R): Indicates whether an RXI2 (SCIF) interrupt request is generated. Bit 1: RXI2R 0 1 Description An RXI2 interrupt request is not generated An RXI2 interrupt request is generated (Initial value) Bit 0--ERI2 Interrupt Request (ERI2R): Indicates whether an ERI2 (SCIF) interrupt request is generated. Bit 0: ERI2R 0 1 Description An ERI2 interrupt request is not generated An ERI2 interrupt request is generated (Initial value) 7.3.10 Interrupt Request Register 3 (IRR3) The IRR3 is a 16-bit read-only register that indicates whether PC Card controller, USB Controller or LCDC interrupt requests are generated. This register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R 7 0 R 14 0 R 6 0 R 13 0 R 5 0 R 12 0 R 4 0 R 11 0 R 3 -- 0 R 10 0 R 2 -- 0 R 9 0 R 1 -- 0 R 8 0 R 0 -- 0 R LCDCIR PC0SWIR PC0IRIR PC0SCIR PC0CDIR PC0RCIR PC0BWIR PC0BDIR USBHIR USBF0IR USBF1IR AFEIFIR Rev. 5.00 Dec 12, 2005 page 192 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 15--LCDCI interrupt request (LCDCIR): Indicates whether a LCDCI (LCDC) interrupt request is generated. Bit 15: LCDCIR 0 1 Description A LCDCI interrupt request is not generated A LCDCI interrupt request is generated (Initial value) Bit 14--PC0SWI Interrupt Request (PC0SWIR): Indicates whether a PC0SWI (PCC0) interrupt request is generated. Bit 14: PC0SWIR 0 1 Description A PC0SWI interrupt request is not generated A PC0SWI interrupt request is generated (Initial value) Bit 13--PC0IRI Interrupt Request (PC0IRIR): Indicates whether a PC0IREQ (PCC0) interrupt request is generated. Bit 13: PC0IRIR 0 1 Description A PC0IRI interrupt request is not generated A PC0IRI interrupt request is generated (Initial value) Bit 12--PC0SCI Interrupt Request (PC0SCIR): Indicates whether a PC0SCI (PCC0) interrupt request is generated. Bit 12: PC0SCIR 0 1 Description A PC0SCI interrupt request is not generated A PC0SCI interrupt request is generated (Initial value) Bit 11--PC0CDI Interrupt Request (PC0CDIR): Indicates whether a PC0CDI (PCC0) interrupt request is generated. Bit 11: PC0CDIR 0 1 Description A PC0CDI interrupt request is not generated A PC0CDI interrupt request is generated (Initial value) Rev. 5.00 Dec 12, 2005 page 193 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 10--PC0RCI Interrupt Request (PC0RCIR): Indicates whether a PC0RCI (PCC0) interrupt request is generated. Bit 10: PC0RCIR 0 1 Description A PC0RCI interrupt request is not generated A PC0RCI interrupt request is generated (Initial value) Bit 9--PC0BWI Interrupt Request (PC0BWIR): Indicates whether a PC0BWI (PCC0) interrupt request is generated. Bit 9: PC0BWIR 0 1 Description A PC0BWI interrupt request is not generated A PC0BWI interrupt request is generated (Initial value) Bit 8--PC0BDI Interrupt Request (PC0BDIR): Indicates whether a PC0BDI (PCC0) interrupt request is generated. Bit 8: PC0BDIR 0 1 Description A PC0BDI interrupt request is not generated A PC0BDI interrupt request is generated (Initial value) Bit 7--USBHI Interrupt Request (USBHIR): Indicates whether a USBHI (USB Host) interrupt request is generated. Bit 7: USBHIR 0 1 Description A USBHI interrupt request is not generated A USBHI interrupt request is generated (Initial value) Bit 6--USBF0I Interrupt Request (USBF0IR): Indicates whether a USBF0I (USB function) interrupt request is generated. Bit 6: USBF0IR 0 1 Description A USBF0I interrupt request is not generated A USBF0I interrupt request is generated (Initial value) Rev. 5.00 Dec 12, 2005 page 194 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 5--USBF1I Interrupt Request (USBF1IR): Indicates whether a USBF1I (USB function) interrupt request is generated. Bit 5: USBF1IR 0 1 Description A USBF1I interrupt request is not generated A USBF1I interrupt request is generated (Initial value) Bit 4--AFEIFI Interrupt Request (AFEIFIR): Indicates whether a AFEIFI (AFE I/F) interrupt request is generated. Bit 4: AFEIFIR 0 1 Description An AFE I/F interrupt request is not generated An AFE I/F interrupt request is generated (Initial value) Bits 3 to 0--Reserved: These bits are always read as 0. 7.3.11 Interrupt Request Register 4 (IRR4) The IRR4 is a 16-bit read-only register that indicates whether SIOF interrupt requests are generated. This register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 ERI 0 R 10 -- 0 R 2 TXI 0 R 9 -- 0 R 1 RXI 0 R 8 -- 0 R 0 CCI 0 R Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Dec 12, 2005 page 195 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Bit 3--ERI Interrupt Request (ERI): Indicates whether a ERI (SIOF) interrupt request is generated. Bit 3: ERI 0 1 Description ERI interrupt request is not generated ERI interrupt request is generated (Initial value) Bit 2--TXI Interrupt Request (TXI): Indicates whether a TXI (SIOF) interrupt request is generated. Bit 2:TXI 0 1 Description TXI interrupt request is not generated TXI interrupt request is generated (Initial value) Bit 1--RXI Interrupt Request (RXI): Indicates whether a RXI (SIOF) interrupt request is generated. Bit 1: RXI 0 1 Description RXI interrupt request is not generated RXI interrupt request is generated (Initial value) Bit 0--CCI Interrupt Request (CCI): Indicates whether a CCI (CCI) interrupt request is generated. Bit 0: CCI 0 1 Description CCI interrupt request is not generated CCI interrupt request is generated (Initial value) Rev. 5.00 Dec 12, 2005 page 196 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.4 7.4.1 INTC Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 7.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers A to G (IPRA to IPRG). Lower priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting unit (as indicated in tables 7.4 and 7.5) is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in synchronization with the peripheral clock (P). The CPU receives an interrupt at a break in instructions. 5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt handler may branch with the INTEVT and INTEVT2 register value as its offset in order to identify the interrupt source. This enables it to branch to the processing routine for the individual interrupt source. Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by acceptance of an interrupt in the SH7727. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 7.8 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. Rev. 5.00 Dec 12, 2005 page 197 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Program execution state ICR1.MAI = 1? No No Yes NMI = low? No Yes Interrupt generated? Yes No ICR1.BLMSK = 1? Yes Yes No NMI? Yes Yes NMI? No No SR.BL= 0 or sleep mode? Level 15 interrupt? Yes Yes Set interrupt cause in INTEVT, INTEVT2 Save SR to SSR; save PC to SPC Set BL/MD/RB bits in SR to 1 Branch to exception handler I3-I0 level 14 or lower? No Yes No Level 14 interrupt? Yes I3-I0 level 13 or lower? No Yes No Level 1 interrupt? Yes I3-I0 level 0? No No I3-I0: Interrupt mask bits in status register (SR) Figure 7.3 Interrupt Operation Flowchart Rev. 5.00 Dec 12, 2005 page 198 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) 7.4.2 Multiple Interrupts When processing multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the specific handler. 2. Clear the cause of the interrupt in each specific handler. 3. Save SSR and SPC to the memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. 7.5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 7.8. Figure 7.4 shows an example of pipeline operation when an IRL interrupt is accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until completion of an instruction that clears BL to 0. Rev. 5.00 Dec 12, 2005 page 199 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Table 7.8 Interrupt Response Time Number of States Peripheral Modules 0.5 x Icyc + 1.5 x Pcyc*5 0.5 x Icyc + 3 x Pcyc*6 Item Time for priority decision and SR mask bit comparison NMI 0.5 x Icyc + 0.5 x Bcyc + 0.5 x Pcyc IRQ PINT Notes 0.5 x Icyc 0.5 x Icyc + 1 x Bcyc + 3.5 x Pcyc + 4.5 x Pcyc*4 Wait time until end of sequence being executed by CPU X ( 0) x Icyc X ( 0) x Icyc X ( 0) x Icyc X ( 0) x Icyc Interrupt exception handling is kept waiting until the executing instruction ends. If the number of instruction execution states is S*1, the maximum wait time is: X = S - 1. However, if BL is set to 1 by instruction execution or by an exception, interrupt exception handling is deferred until completion of an instruction that clears BL to 0. If the following instruction masks interrupt exception handling, the processing may be further deferred. Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started 5 x Icyc 5 x Icyc 5 x Icyc 5 x Icyc Rev. 5.00 Dec 12, 2005 page 200 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Number of States Item Response time Total NMI (5.5 + X) x Icyc + 0.5 x Bcyc + 0.5 x Pcyc IRQ (5.5 + X) x Icyc + 1 x Bcyc + 4.5 x Pcyc*4 PINT (5.5 + X) x Icyc + 3.5 x Pcyc*5 Peripheral Modules (5.5 + X) x Icyc + 1.5 x Pcyc*5 (5.5 + X) x Icyc + 3 x Pcyc*6 Minimum case*2 Maximum case*3 7.5 16.5 12.5 8.5*5/11.5*6 At 60-MHz (CKIO = 30) operation: 0.13-0.28 s At 60-MHz (CKIO = 15) operation: 0.26-0.56 s (in case of operand cache-hit) At 60-MHz (CKIO = 15) operation: 0.29-0.59 s (when external memory access is performed with wait = 0) Notes 8.5 + S 26.5 + S 18.5 + S 10.5 + S*5 16.5 + S*6 Icyc: Duration of one cycle of internal clock supplied to CPU. Bcyc: Duration of one CKIO cycle. Pcyc: Duration of one cycle of peripheral clock supplied to peripheral modules. Notes: 1. S also includes the memory access wait time. The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the memory access is a cache-hit, this requires seven instruction execution cycles. When the external access is performed, the corresponding number of cycles must be added. There are also instructions that perform two external memory accesses; if the external memory access is slow, the number of instruction execution cycles will increase accordingly. 2. The internal clock: CKIO: peripheral clock ratio is 2:1:1. 3. The internal clock: CKIO: peripheral clock ratio is 4:1:1. 4. IRQ mode 5. Modules: TMU, RTC, SCI, WDT, REFC 6. Modules: DMAC, ADC, SCIF, LCDC, PCC, USB host, USB function, AFE interface Rev. 5.00 Dec 12, 2005 page 201 of 1034 REJ09B0254-0500 Section 7 Interrupt Controller (INTC) Interrupt acceptance 0.5 x Icyc + 0.5 x Bcyc + 2 x Pcyc IRL Instruction (instruction replaced by interrupt exception processing) Overrun fetch First instruction of interrupt handler Start of interrupt processing 5 x Icyc IF ID EX EX EX EX IF IF ID EX IF: Instruction fetch: Instruction is fetched from memory in which program is stored. ID: Instruction decode: Fetched instruction is decoded. EX: Instruction execution: Data operation and address calculation are performed in accordance with result of decoding. Figure 7.4 Example of Pipeline Operations when IRL Interrupt is Accepted Rev. 5.00 Dec 12, 2005 page 202 of 1034 REJ09B0254-0500 Section 8 User Break Controller Section 8 User Break Controller 8.1 Overview The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and timing in the case of instruction fetch. 8.1.1 Features The UBC has the following features: * The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and, then channel B match with logical AND, but not in the same bus cycle). Address (Compares 40 bits comprised of a 32-bit logical address prefixed with an ASID address Comparison bits are maskable in 32-bit units, user can easily program it to mask addresses at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc. The 8-bit ASID checking is from MMU control to indicate hit or not hit.) One of four address buses (CPU address bus (LAB), cache address bus (IAB), X-memory address bus (XAB) and Y-memory address bus (YAB)) can be selected. Data (only on channel B, 32-bit maskable) One of the four data buses (CPU data bus (LDB), cache data bus (IDB), X-memory data bus (XDB) and Y-memory data bus (YDB)) can be selected. Bus master: CPU cycle or DMAC cycle Bus cycle: instruction fetch or data access Read/write Operand size: byte, word, or longword * User break is generated upon satisfying break conditions. A user-designed user-break condition exception processing routine can be run. * In an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. Rev. 5.00 Dec 12, 2005 page 203 of 1034 REJ09B0254-0500 Section 8 User Break Controller * Maximum repeat times for the break condition: 212 - 1 times. (It is only for channel B) * Eight pairs of branch source/destination buffers. 8.1.2 Block Diagram Figure 8.1 is a block diagram of the UBC. XAB/YAB IAB LAB Access comparator MDB Access Control BBRA BARA Address comparator BAMRA ASID comparator Channel A BASRA Access comparator BBRB BARB Address comparator BAMRB ASID comparator BASRB BDRB BDMRB BETR BRSR Data comparator Channel B PC Trace BRDR CONTROL BRCR LDB/IDB/ XDB/YDB CPU state signals User break request UBC Location CCN Location Legend BBRA: BARA: BAMRA: BASRA: BBRB: BARB: BAMRB: Break bus cycle register A Break address register A Break address mask register A Break ASID register A Break bus cycle register B Break address register B Break address mask register B BASRB: BDRB: BDMRB: BETR: BRSR: BRDR: BRCR: Break ASID register B Break data register B Break data mask register B Break execution times register Branch source register Branch destination register Break control register Figure 8.1 Block Diagram of User Break Controller Rev. 5.00 Dec 12, 2005 page 204 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.1.3 Table 8.1 Name Register Configuration Register Configuration Abbr. BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR BETR BRSR BRDR BASRA BASRB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W Initial 1 Value* H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 H'0000 Undefined* 2 Undefined* 2 Address H'FFFFFFB0 H'FFFFFFB4 H'FFFFFFB8 H'FFFFFFA0 H'FFFFFFA4 H'FFFFFFA8 H'FFFFFF90 H'FFFFFF94 H'FFFFFF98 H'FFFFFF9C Access Size Location 32 32 16 32 32 16 32 32 32 16 UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC CCN CCN Break address register A Break address mask register A Break bus cycle register A Break address register B Break address mask register B Break bus cycle register B Break data register B Break data mask register B Break control register Execution count break register Branch source register Branch destination register Break ASID register A Break ASID register B H'FFFFFFAC 32 H'FFFFFFBC 32 H'FFFFFFE4 H'FFFFFFE8 8 8 Undefined Undefined Notes: 1. Initialized by power-on reset. Values held in standby state and undefined by manual resets. 2. Bit 31 of BRSR and BRDR (valid flag) is initialized by power-on resets. But other bits are not initialized. Rev. 5.00 Dec 12, 2005 page 205 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2 8.2.1 Register Descriptions Break Address Register A (BARA) Bit: 31 BAA 31 30 BAA 30 0 R/W 29 BAA 29 0 R/W 28 BAA 28 0 R/W 27 BAA 27 0 R/W 26 BAA 26 0 R/W 25 BAA 25 0 R/W 24 BAA 24 0 R/W 23 BAA 23 0 R/W 22 BAA 22 0 R/W 21 BAA 21 0 R/W 20 BAA 20 0 R/W 19 BAA 19 0 R/W 18 BAA 18 0 R/W 17 BAA 17 0 R/W 16 BAA 16 0 R/W Initial value: R/W: 0 R/W Bit: 15 BAA 15 14 BAA 14 0 R/W 13 BAA 13 0 R/W 12 BAA 12 0 R/W 11 BAA 11 0 R/W 10 BAA 10 0 R/W 9 BAA 9 0 R/W 8 BAA 8 0 R/W 7 BAA 7 0 R/W 6 BAA 6 0 R/W 5 BAA 5 0 R/W 4 BAA 4 0 R/W 3 BAA 3 0 R/W 2 BAA 2 0 R/W 1 BAA 1 0 R/W 0 BAA 0 0 R/W Initial value: R/W: 0 R/W BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA to H'00000000. Bits 31 to 0--Break Address A31 to A0 (BAA31 to BAA0): Stores the address on the LAB or IAB specifying break conditions of channel A. 8.2.2 Break Address Mask Register A (BAMRA) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. A power-on reset initializes BAMRA to H'00000000. Rev. 5.00 Dec 12, 2005 page 206 of 1034 REJ09B0254-0500 Section 8 User Break Controller Bits 31 to 0--Break Address Mask Register A31 to A0 (BAMA31 to BAMA0): Specifies bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). Bits 31 to 0: BAMAn 0 1 Description Break address bit BAAn of channel A is included in the break condition (Initial value) Break address bit BAAn of channel A is masked and is not included in the break condition n = 31 to 0 8.2.3 Break Bus Cycle Register A (BBRA) Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 6 5 4 3 2 1 0 CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: 0 R Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A. A power-on reset initializes BBRA to H'0000. Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. Bits 7 and 6--CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Selects the CPU cycle or DMAC cycle as the bus cycle of the channel A break condition. Bit 7: CDA1 0 * 1 Bit 6: CDA0 0 1 0 Description Condition comparison is not performed The break condition is the CPU cycle The break condition is the DMAC cycle (Initial value) Note: * Don't care Rev. 5.00 Dec 12, 2005 page 207 of 1034 REJ09B0254-0500 Section 8 User Break Controller Bits 5 and 4--Instruction Fetch/Data Access Select A (IDA1, IDA0): Selects the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. Bit 5: IDA1 0 1 Bit 4: IDA0 0 1 0 1 Description Condition comparison is not performed The break condition is the instruction fetch cycle The break condition is the data access cycle The break condition is the instruction fetch cycle or data access cycle (Initial value) Bits 3 and 2--Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the bus cycle of the channel A break condition. Bit 3: RWA1 0 1 Bit 2: RWA0 0 1 0 1 Description Condition comparison is not performed The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle (Initial value) Bits 1 and 0--Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle for the channel A break condition. Bit 1: SZA1 0 Bit 0: SZA0 0 1 1 0 1 Description The break condition does not include operand size (Initial value) The break condition is byte access The break condition is word access The break condition is longword access Rev. 5.00 Dec 12, 2005 page 208 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.4 Break Address Register B (BARB) Bit: 31 BAB 31 30 BAB 30 0 R/W 29 BAB 29 0 R/W 28 BAB 28 0 R/W 27 BAB 27 0 R/W 26 BAB 26 0 R/W 25 BAB 25 0 R/W 24 BAB 24 0 R/W 23 BAB 23 0 R/W 22 BAB 22 0 R/W 21 BAB 21 0 R/W 20 BAB 20 0 R/W 19 BAB 19 0 R/W 18 BAB 18 0 R/W 17 BAB 17 0 R/W 16 BAB 16 0 R/W Initial value: R/W: 0 R/W Bit: 15 BAB 15 14 BAB 14 0 R/W 13 BAB 13 0 R/W 12 BAB 12 0 R/W 11 BAB 11 0 R/W 10 BAB 10 0 R/W 9 BAB 9 0 R/W 8 BAB 8 0 R/W 7 BAB 7 0 R/W 6 BAB 6 0 R/W 5 BAB 5 0 R/W 4 BAB 4 0 R/W 3 BAB 3 0 R/W 2 BAB 2 0 R/W 1 BAB 1 0 R/W 0 BAB 0 0 R/W Initial value: R/W: 0 R/W BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. Control bits XYE and XYS in the BBRB selects an address bus for break condition B. If the XYE is 0, then BARB specifies the break address on logic or internal bus, LAB or IAB. If the XYE is 1, then the BAB31 to 16 specifies the break address on XAB (bits 15 to 1) and the BAB15 to 0 specifies the break address on YAB (bits 15 to 1). However, you have to choose one of two address buses for the break. A power-on reset initializes BARB to H'00000000. BAB31 to 16 XYE = 0 XYE = 1 L(I) AB31 to 16 XAB15 to 1 (XYS = 0) BAB15 to 0 L(I) AB15 to 0 YAB15 to 1 (XYS = 1) Rev. 5.00 Dec 12, 2005 page 209 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.5 Break Address Mask Register B (BAMRB) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB BAMB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address specified by BARB. A power-on reset initializes BAMRB to H'00000000. BAMB31 to 16 XYE = 0 XYE = 1 Bits 31 to 0: BAMBn 0 1 Mask L(I) AB31 to 16 Mask XAB15 to 1 (XYS = 0) BAMB15 to 0 Mask L(I) AB15 to 0 Mask YAB15 to 1 (XYS = 1) Description Break address BABn of channel B is included in the break condition (Initial value) Break address BABn of channel B is masked and is not included in the break condition n = 31 to 0 Rev. 5.00 Dec 12, 2005 page 210 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.6 Break Data Register B (BDRB) Bit: 31 BDB 31 30 BDB 30 0 R/W 29 BDB 29 0 R/W 28 BDB 28 0 R/W 27 BDB 27 0 R/W 26 BDB 26 0 R/W 25 BDB 25 0 R/W 24 BDB 24 0 R/W 23 BDB 23 0 R/W 22 BDB 22 0 R/W 21 BDB 21 0 R/W 20 BDB 20 0 R/W 19 BDB 19 0 R/W 18 BDB 18 0 R/W 17 BDB 17 0 R/W 16 BDB 16 0 R/W Initial value: R/W: 0 R/W Bit: 15 BDB 15 14 BDB 14 0 R/W 13 BDB 13 0 R/W 12 BDB 12 0 R/W 11 BDB 11 0 R/W 10 BDB 10 0 R/W 9 BDB 9 0 R/W 8 BDB 8 0 R/W 7 BDB 7 0 R/W 6 BDB 6 0 R/W 5 BDB 5 0 R/W 4 BDB 4 0 R/W 3 BDB 3 0 R/W 2 BDB 2 0 R/W 1 BDB 1 0 R/W 0 BDB 0 0 R/W Initial value: R/W: 0 R/W BDRB is a 32-bit read/write register. The control bits XYE and XYS in BBRB select a data bus for break condition B. If the XYE is 0, then BDRB specifies the break data on LDB or IDB. If the XYE is 1, then BDB 31 to 16 specifies the break data on XDB (bits 15 to 0) and BDB 15 to 0 specifies the break data on YDB (bits 15 to 0). However, you have to choose one of two data buses for the break. A power-on reset initializes BDRB to H'00000000. BDB31 to 16 XYE = 0 XYE = 1 L(I) DB31 to 16 XDB15 to 0 (XYS = 0) BDB15 to 0 L(I) DB15 to 0 YDB15 to 0 (XYS = 1) Rev. 5.00 Dec 12, 2005 page 211 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.7 Break Data Mask Register B (BDMRB) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB BDMB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. A power-on reset initializes BDMRB to H'00000000. BDMB31 to 16 XYE = 0 XYE = 1 Bits 31 to 0: BDMBn 0 1 Mask L(I) DB31 to 16 Mask XDB15 to 0 (XYS = 0) BDMB15 to 0 Mask L(I) DB15 to 0 Mask YDB15 to 0 (XYS = 1) Description Break data BDBn of channel B is included in the break condition (Initial value) Break data BDBn of channel B is masked and is not included in the break condition n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When a byte size is selected as a break condition, the same break data (byte size) must be set both in bits 15 to 8 and in bits 7 to 0 in BDRB. Rev. 5.00 Dec 12, 2005 page 212 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.8 Break Bus Cycle Register B (BBRB) Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 XYE 0 R/W 8 7 6 5 4 3 2 1 0 XYS CDB1 CDB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: 0 R Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies (1) logic or internal bus (L or I bus), X bus, of Y bus, (2) CPU cycle or DMAC cycle, (3) instruction fetch or data access, (4) read/write, and (5) operand size in the break conditions of channel B. A power-on reset initializes BBRB to H'0000. Bits 15 to 10--Reserved: These bits are always read as 0. The write value should always be 0. Bit 9--X/Y Memory Bus Enable (XYE): Selects the logic bus or internal bus (L bus or I bus) or the X/Y memory bus as the bus of the channel B break condition. Bit 9: XYE 0 1 Description Select internal bus (I bus) for the channel B break condition Select X/Y memory bus (X/Y bus) for the channel B break condition Bits 8--X or Y Memory Bus Select (XYS): Selects the X bus or the Y bus as the bus of the channel B break condition. Bit 8: XYS 0 1 Description Select the X bus for the channel B break condition Select the Y bus for the channel B break condition Bits 7 and 6--CPU Cycle/DMAC Cycle Select B (CDB1 and CDB0): Select the CPU cycle or DMAC cycle as the bus cycle of the channel B break condition. Bit 7: CDB1 0 * 1 Bit 6: CDB0 0 1 0 Description Condition comparison is not performed The break condition is the CPU cycle The break condition is the DMAC cycle (Initial value) Note: * Don't care. Rev. 5.00 Dec 12, 2005 page 213 of 1034 REJ09B0254-0500 Section 8 User Break Controller Bits 5 and 4--Instruction Fetch/Data Access Select B (IDB1 and IDB0): Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. Bit 5: IDB1 0 1 Bit 4: IDB0 0 1 0 1 Description Condition comparison is not performed The break condition is the instruction fetch cycle The break condition is the data access cycle The break condition is the instruction fetch cycle or data access cycle (Initial value) Bits 3 and 2--Read/Write Select B (RWB1 and RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition. Bit 3: RWB1 0 1 Bit 2: RWB0 0 1 0 1 Description Condition comparison is not performed The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle (Initial value) Bits 1 and 0--Operand Size Select B (SZB1 and SZB0): Select the operand size of the bus cycle for the channel B break condition. Bit 1: SZB1 0 Bit 0: SZB0 0 1 1 0 1 Description The break condition does not include operand size (Initial value) The break condition is byte access The break condition is word access The break condition is longword access Rev. 5.00 Dec 12, 2005 page 214 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.9 Break Control Register (BRCR) Bit: 31 -- 30 -- 0 R 29 -- 0 R 28 -- 0 R 27 -- 0 R 26 -- 0 R 25 -- 0 R 24 -- 0 R 23 -- 0 R 22 -- 0 R 21 BAS MA 0 R/W 20 BAS MB 0 R/W 19 -- 0 R 18 -- 0 R 17 -- 0 R 16 -- 0 R Initial value: R/W: 0 R Bit: 15 14 13 12 11 10 9 -- 0 R 8 -- 0 R 7 6 5 -- 0 R 4 -- 0 R 3 SEQ 0 R/W 2 -- 0 R 1 -- 0 R 0 ETBE 0 R/W SCM SCM SCM SCM PCTE PCBA FCA FCB FDA FDB Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DBEB PCBB 0 R/W 0 R/W BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition. 2. A break is set before or after instruction execution. 3. A break is set by the number of execution times. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace. 6. Enable the ASID check. The break control register (BRCR) is a 32-bit read/write register that has break conditions match flags and bits for setting a variety of break conditions. A power-on reset initializes BRCR to H'00000000. Bits 31 to 22--Reserved: These bits are always read as 0. The write value should always be 0. Bit 21--Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break ASID7 to ASID0 (BASA7 to BASA0) set in BASRA are masked or not. Bit 21: BASMA Description 0 1 All BASRA bits are included in break condition, and ASID is checked (Initial value) No BASRA bits are included in break condition, and ASID is not checked Rev. 5.00 Dec 12, 2005 page 215 of 1034 REJ09B0254-0500 Section 8 User Break Controller Bit 20--Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7 to ASID0 (BASB7 to BASB0) set in BASRB are masked or not. Bit 20: BASMB Description 0 1 All BASRB bits are included in break condition, and ASID is checked (Initial value) No BASRB bits are included in break condition, and ASID is not checked Bits 19 to 16--Reserved: These bits are always read as 0. The write value should always be 0. Bit 15--CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 15: SCMFCA 0 1 Description The CPU cycle condition for channel A does not match The CPU cycle condition for channel A matches (Initial value) Bit 14--CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 14: SCMFCB 0 1 Description The CPU cycle condition for channel B does not match The CPU cycle condition for channel B matches (Initial value) Bit 13--DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 13: SCMFDA 0 1 Description The DMAC cycle condition for channel A does not match The DMAC cycle condition for channel A matches (Initial value) Rev. 5.00 Dec 12, 2005 page 216 of 1034 REJ09B0254-0500 Section 8 User Break Controller Bit 12--DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 12: SCMFDB 0 1 Description The DMAC cycle condition for channel B does not match The DMAC cycle condition for channel B matches (Initial value) Bit 11--PC Trace Enable (PCTE): Enables PC trace. Bit 11: PCTE 0 1 Description Disables PC trace Enables PC trace (Initial value) Bit 10--PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. Bit 10: PCBA 0 1 Description PC break of channel A is set before instruction execution PC break of channel A is set after instruction execution (Initial value) Bits 9 and 8--Reserved: These bits are always read as 0. The write value should always be 0. Bit 7--Data Break Enable B (DBEB): Selects whether or not the data bus condition is included in the break condition of channel B. Bit 7: DBEB 0 1 Description No data bus condition is included in the condition of channel B The data bus condition is included in the condition of channel B (Initial value) Bit 6--PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. Bit 6: PCBB 0 1 Description PC break of channel B is set before instruction execution PC break of channel B is set after instruction execution (Initial value) Rev. 5.00 Dec 12, 2005 page 217 of 1034 REJ09B0254-0500 Section 8 User Break Controller Bits 5 and 4--Reserved: These bits are always read as 0. The write value should always be 0. Bit 3--Sequence Condition Select (SEQ): Selects two conditions of channels A and B as independent or sequential. Bit 3: SEQ 0 1 Description Channels A and B are compared under the independent condition (Initial value) Channels A and B are compared under the sequential condition Bits 2 and 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--The Number of Execution Times Break Enable (ETBE): Enable the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by the BETR register. Bit 0: ETBE 0 1 Description The execution-times break condition is disabled on channel B The execution-times break condition is enabled on channel B (Initial value) 8.2.10 Execution Times Break Register (BETR) Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 -- 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 - 1 times. A power-on reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A break is issued when the break condition is satisfied after the BETR becomes H'0001. Bits 15 to 12 are always read as 0 and 0 should always be written in these bits. Rev. 5.00 Dec 12, 2005 page 218 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.11 Branch Source Register (BRSR) Bit: 31 SVF 30 29 28 27 BSA 27 * R 26 BSA 26 * R 25 BSA 25 * R 24 BSA 24 * R 23 BSA 23 * R 22 BSA 22 * R 21 BSA 21 * R 20 BSA 20 * R 19 BSA 19 * R 18 BSA 18 * R 17 BSA 17 * R 16 BSA 16 * R PID2 PID1 PID0 * R * R * R Initial value: R/W: 0 R Bit: 15 BSA 15 14 BSA 14 * R 13 BSA 13 * R 12 BSA 12 * R 11 BSA 11 * R 10 BSA 10 * R 9 BSA 9 * R 8 BSA 8 * R 7 BSA 7 * R 6 BSA 6 * R 5 BSA 5 * R 4 BSA 4 * R 3 BSA 3 * R 2 BSA 2 * R 1 BSA 1 * R 0 BSA 0 * R Initial value: R/W: * R Note: * Undefined BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted every branch. Bit 31--BRSR Valid Flag (SVF): Indicates whether the address and the pointer by which the branch source address can be calculated. When a branch source address is fetched, this flag is set to 1. This flag is cleared to 0 in reading BRSR. Bit 31: SVF 0 1 Description The value of BRSR register is invalid The value of BRSR register is valid Bits 30 to 28--Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0 to 7). These bits indicate the instruction buffer number which stores the last executed instruction before branch. Bits 30 to 28: PID Even Odd Description PID indicates the instruction buffer number. PiD+2 indicates the instruction buffer number Rev. 5.00 Dec 12, 2005 page 219 of 1034 REJ09B0254-0500 Section 8 User Break Controller Bits 27 to 0--Branch Source Address (BSA27 to BSA0): These bits store the last fetched address before branch. 8.2.12 Branch Destination Register (BRDR) Bit: 31 DVF Initial value: R/W: 0 R 30 -- * R 29 -- * R 28 -- * R 27 BDA 27 * R 26 BDA 26 * R 25 BDA 25 * R 24 BDA 24 * R 23 BDA 23 * R 22 BDA 22 * R 21 BDA 21 * R 20 BDA 20 * R 19 BDA 19 * R 18 BDA 18 * R 17 BDA 17 * R 16 BDA 16 * R Bit: 15 BDA 15 14 BDA 14 * R 13 BDA 13 * R 12 BDA 12 * R 11 BDA 11 * R 10 BDA 10 * R 9 BDA 9 * R 8 BDA 8 * R 7 BDA 7 * R 6 BDA 6 * R 5 BDA 5 * R 4 BDA 4 * R 3 BDA 3 * R 2 BDA 2 * R 1 BDA 1 * R 0 BDA 0 * R Initial value: R/W: * R Note: * Undefined BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight BRDR registers have queue structure and a stored register is shifted every branch. Bit 31--BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 in reading BRDR. Bit 31: DVF 0 1 Description The value of BRDR register is invalid The value of BRDR register is valid Bits 30 to 28--Reserved: These bits are always read as 0. The write value should always be 0. Bits 27 to 0--Branch Destination Address (BDA27 to BDA0): These bits store the first fetched address after branch. Rev. 5.00 Dec 12, 2005 page 220 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.2.13 Break ASID Register A (BASRA) Bit: Initial value: R/W: 7 BASA7 * R/W 6 BASA6 * R/W 5 BASA5 * R/W 4 BASA4 * R/W 3 BASA3 * R/W 2 BASA2 * R/W 1 BASA1 * R/W 0 BASA0 * R/W Note: * Undefined Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves as the break condition for channel A. It is not initialized by resets. It is located in CCN. Bits 7 to 0--Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0) that is the channel A break condition. 8.2.14 Break ASID Register B (BASRB) Bit: Initial value: R/W: Note: * Undefined 7 BASB7 * R/W 6 BASB6 * R/W 5 BASB5 * R/W 4 BASB4 * R/W 3 BASB3 * R/W 2 BASB2 * R/W 1 BASB1 * R/W 0 BASB0 * R/W Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves as the break condition for channel B. It is not initialized by resets. It is located in CCN. Bits 7 to 0: Break ASID A7 to 0 (BASB7 to BASB0): These bits store the ASID (bits 7 to 0) that is the channel B break condition. Rev. 5.00 Dec 12, 2005 page 221 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.3 8.3.1 Operation Description Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and the corresponding ASIDs are loaded in the break address registers (BARA and BARB) and break ASID registers (BASRA and BASRB in CCN). The masked addresses are set in the break address mask registers (BAMRA and BAMRB). The break data is set in the break data register (BDRB). The masked data is set in the break data mask register (BDMRB). The breaking bus conditions are set in the break bus cycle registers (BBRA and BBRB). Three groups of the BBRA and BBRB (CPU cycle/DMAC cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with 00. The respective conditions are set in the bits of the BRCR. 2. When the break conditions are satisfied, the UBC sends a user break request to the interrupt controller. The break type will be sent to CPU indicating the instruction fetch, pre/post instruction break, data access break, or on-chip I/O access/LDTLB break. When conditions match up, the CPU condition match flags (SCMFCA and SCMFCB) and DMAC condition match flags (SCMFDA and SCMFDB) for the respective channels are set. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. There is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one break request to the CPU, but these two break channel match flags could both be set. 8.3.2 Break on Instruction Fetch Cycle 1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers (BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then breaks before or after the execution of the instruction can then be selected with the PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delay branch instruction, the break is generated prior to execution of the instruction that then first accepts the break. Meanwhile, the break set for pre-instruction-break on delay slot instruction and postinstruction-break on SLEEP instruction are also prohibited. Rev. 5.00 Dec 12, 2005 page 222 of 1034 REJ09B0254-0500 Section 8 User Break Controller 3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delay branch instruction, the break is generated at the instruction that then first accepts the break. 4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored. There is thus no need to set break data for the break of the instruction fetch cycle. 8.3.3 Break by Data Access Cycle 1. The memory cycles in which CPU data access breaks occur are from instructions. 2. The relationship between the data access cycle address and the comparison condition for operand size are listed in table 8.2: Table 8.2 Access Size Longword Word Byte Data Access Cycle Addresses and Operand Size Comparison Conditions Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set without specifying the size condition, for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions on B channel: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. 4. When the DMAC data access is included in the break condition: When the address is included in the break condition on DMAC data access, the operand size of the break bus cycle registers (BBRA and BBRB) should be byte, word or no operand size specification. When the data value is included, select either byte or word. Rev. 5.00 Dec 12, 2005 page 223 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.3.4 Break on X/Y-Memory Bus Cycle 1. The break condition on X/Y-memory bus cycle is specified only in channel B. If XYE in BBRB is set to 1, break address and break data on X/Y-memory bus are selected. At this time, select X-memory bus or Y-memory bus by specifying XYS in BBRB. The Break condition cannot include both X-memory and Y-memory at the same time. The break condition is applied to X/Y-memory bus cycle by specifying CPU/data access/read or write/word or no operand size specification in the break bus cycle register B (BBRB). 2. When X-memory address is selected as the break condition, specify X-memory address in upper 16 bits in BARB and BAMRB. When Y-memory address is selected, specify Y-memory address in lower 16 bits. Specification of X/Y-memory data is the same for BDRB and BDMRB. 8.3.5 Sequential Break 1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break condition matches after channel A break condition matches. A user break is ignored even if channel B break condition matches before channel A break condition matches. When channels A and B condition match at the same time, the sequential break is not issued. 2. In sequential break specification, internal/X/Y bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied at channel B condition match with BETR = H'0001 after channel A condition match. 8.3.6 Value of Saved Program Counter The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows depending on the type of break. 1. When instruction fetch (before instruction execution) is specified as a break condition: The value of the program counter (PC) saved is the address of the instruction that matches the break condition. The fetched instruction is not executed, and a break occurs before it. 2. When instruction fetch (after instruction execution) is specified as a break condition: The PC value saved is the address of the instruction to be executed following the instruction in which the break condition matches. The fetched instruction is executed, and a break occurs before the execution of the next instruction. Rev. 5.00 Dec 12, 2005 page 224 of 1034 REJ09B0254-0500 Section 8 User Break Controller 3. When data access (address only) is specified as a break condition: The PC value is the address of the instruction to be executed following the instruction that matched the break condition. The instruction that matched the condition is executed and the break occurs before the next instruction is executed. 4. When data access (address + data) is specified as a break condition: The PC value is the start address of the instruction that follows the instruction already executed when break processing started up. When a data value is added to the break conditions, the place where the break will occur cannot be specified exactly. The break will occur before the execution of an instruction fetched around the data access where the break occurred. 8.3.7 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in BRSR and BRDR, respectively. The branch address and the pointer, which corresponds to the branch, are included in BRSR. 2. The branch address before branch occurs can be calculated from the address and the pointer stored in BRSR. The expression from BSA (the address in BRSR), PID (the pointer in BRSR), and IA (the instruction address before branch occurs) is as follows: IA = BSA - 2 * PID. Notes are needed when an interrupt (a branch) is issued before the branch destination instruction is executed. In case of the next figure, the instruction "Exec" executed immediately before branch is calculated by IA = BSA - 2 * PID. However, when branch "branch" has delay slot and the destination address is 4n + 2 address, the address "Dest" which is specified by branch instruction is stored in BRSR (Dest = BSA). Therefore, as IA = BSA - 2 * PID is not applied to this case, this PID is invalid. The case where BSA is 4n + 2 boundary is applied only to this case and then some cases are classified as follows: Exec: branch Dest: instr interrupt Int: interrupt routine If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions in this table are accounted for it. Therefore, the true branch source address is calculated with BSA and PID values stored in BRSR. Dest (not executed) Rev. 5.00 Dec 12, 2005 page 225 of 1034 REJ09B0254-0500 Section 8 User Break Controller 3. The branch address before branch occurrence, IA, has different values due to some kinds of branch. a. Branch instruction The branch instruction address b. Repeat The instruction before the last instruction of a repeat loop Repeat_Start: inst (1); inst (2); : inst (n-1); the address calculated from BRSR Repeat_End: c. Interrupt The last instruction executed before interrupt The top address of interrupt routine is stored in BRDR. In a repeat loop with instructions less than three, no instruction fetch cycle appears and branch source address is unknown. Therefore, PC trace is disabled. 4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR, longword access should be used. Also, the PC trace has a trace pointer, which initially points to the bottom of the queues. The first pair of branch addresses will be stored at the bottom of the queues, then push up when next pairs come into the queues. The trace pointer will points to the next branch address to be executed, unless it got push out of the queues. When the branch address has been executed, the trace pointer will shift down to next pair of addresses, until it reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. The read pointer stay at the position before PCTE is switched, but the trace pointer restart at the bottom of the queues. inst (n); BRDR Rev. 5.00 Dec 12, 2005 page 226 of 1034 REJ09B0254-0500 Section 8 User Break Controller 8.3.8 Usage Examples Break Condition Specified to a CPU Instruction Fetch Cycle 1. Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00000404, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not included in the condition) No ASID check is included * Channel B Address: Data: H'00008010, Address mask: H'00000006 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) No ASID check is included A user break occurs after an instruction of address H'00000404 is executed or before instructions of adresses H'00008010 to H'00008016 are executed. 2. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode * Channel A Address: * Channel B Address: H'0003722E, Address mask: H'00000000, ASID = H'70 Data: H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read/word Rev. 5.00 Dec 12, 2005 page 227 of 1034 REJ09B0254-0500 H'00037226, Address mask: H'00000000, ASID = H'80 Bus cycle: CPU/instruction fetch (before instruction execution)/read/word Section 8 User Break Controller An instruction with ASID = H'80 and address H'00037226 is executed, and a user break occurs before an instruction with ASID = H'70 and address H'0003722E is executed. 3. Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300000 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00027128, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/write/word No ASID check is included * Channel B Address: Data: H'00031415, Address mask: H'00000000 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) No ASID check is included On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. 4. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode * Channel A Address: * Channel B Address: Data: H'0003722E, Address mask: H'00000000, ASID: H'70 H'00000000, Data mask: H'00000000 H'00037226, Address mask: H'00000000, ASID: H'80 Bus cycle: CPU/instruction fetch (before instruction execution)/write/word Bus cycle: CPU/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequence condition does not match. Therefore, no user break occurs. Rev. 5.00 Dec 12, 2005 page 228 of 1034 REJ09B0254-0500 Section 8 User Break Controller 5. Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: Data: H'00001000, Address mask: H'00000000 H'00000000, Data mask: H'00000000 H'00000500, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) On channel A, a user break occurs before an instruction of address H'00000500 is executed. On channel B, a user break occurs before the fifth instruction execution after instructions of address H'00001000 are executed four times. 6. Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00008404, Address mask: H'00000FFF, ASID: H'80 Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not included in the condition) * Channel B Address: Data: H'00008010, Address mask: H'00000006, ASID: H'70 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with ASID = H'80 and address H'00008000 to H'00008FFE is executed or before instructions with ASID = H'70 and addresses H'00008010 to H'00008016 are executed. Rev. 5.00 Dec 12, 2005 page 229 of 1034 REJ09B0254-0500 Section 8 User Break Controller Break Condition Specified to a CPU Data Access Cycle 1. Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: H'000ABCDE, Address mask: H'000000FF, ASID: H'70 Data: H'0000A512, Data mask: H'00000000 Bus cycle: CPU/data access/write/word On channel A, a user break occurs with ASID = H'80 during longword read to address H'00123454, word read to address H'00123456, or byte read to address H'00123456. On channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. 2. Register specifications BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000, BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000, BRCR = H'00300080 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'01000000, Address mask: H'00000000 Bus cycle: CPU/data access/read/word No ASID check is included * Channel B Y Address: H'0001F000, Address mask: H'FFFF0000 Data: H'00004567, Data mask: H'00000000 Bus cycle: CPU/data access/write/word No ASID check is included On channel A, a user break occurs during word read to address H'01000000 on the memory space. On channel B, a user break occurs when word H'4567 is written in address H'0001F000 Rev. 5.00 Dec 12, 2005 page 230 of 1034 REJ09B0254-0500 H'00123456, Address mask: H'00000000, ASID: H'80 Bus cycle: CPU/data access/read (operand size is not included in the condition) Section 8 User Break Controller on Y memory space. The X/Y-memory space is changed by a mode specification. Break Condition Specified to a DMAC Data Access Cycle 1. Register specifications BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: Data: H'00055555, Address mask: H'00000000, ASID: H'70 H'00000078, Data mask: H'0000000F H'00314156, Address mask: H'00000000, ASID: H'80 Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition) Bus cycle: DMAC/data access/write/byte On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles. On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in address H'00055555. 8.3.9 Usage Notes 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DMAC access in the same channel. 3. Notes in specification of sequential break are described below: (1) A condition match occurs when B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no condition match occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. (2) Since the CPU has a pipeline configuration, the pipeline determines the order of an instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches in the order of bus cycles, a sequential condition is satisfied. (3) When the bus cycle condition for channel A is specified as a break before execution (PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows. A break is issued and condition match flags in BRCR are set to 1, when the bus cycle conditions both for channels A and B match simultaneously. Rev. 5.00 Dec 12, 2005 page 231 of 1034 REJ09B0254-0500 Section 8 User Break Controller 4. The change of a UBC register value is executed in MA (memory access) stage. Therefore, even if the break condition matches in the instruction fetch address following the instruction in which the pre-execution break is specified as the break condition, no break occurs. In order to know the timing UBC register is changed, read the last written register. Instructions after then are valid for the newly written register value. 5. Notes in specifying the instruction during repeat execution with repeat instruction as the break condition are as follows: When the instruction during repeat execution is specified as the break condition, (1) The break is not issued during repeat execution, which has fewer than three instructions. (2) When the execution times break is set, no instruction fetch from memory occurs during repeat execution under three instructions. Therefore, the execution times register BETR is not decreased. 6. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR are read. 7. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as follows: (1) Break and instruction fetch exceptions: Instruction fetch exception occurs first. (2) Break before execution and operand exception: Break before execution occurs first. (3) Break after execution and operand exception: Operand exception occurs first. Rev. 5.00 Dec 12, 2005 page 232 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Section 9 Power-Down Modes and Software Reset 9.1 Overview In the power-down modes, all CPU and some on-chip supporting module functions are halted. This lowers power consumption. In particular, the X/Y memory can be stopped to significantly reduce power consumption. Software reset function enables each module to reset itself. 9.1.1 Power-Down Modes The SH7727 has three power-down modes: 1. Sleep mode 2. Standby mode 3. Module standby function (TMU, RTC, SCI, X/Y memory, UBC, DMAC, DAC, ADC, SCIF, LCDC, PCC, USBH, USBF, AFEIF, and SIOF on-chip supporting modules) 4. Hardware standby mode Table 9.1 shows the transition conditions for entering any mode from the program execution state, the CPU and supporting module states in each mode, and the procedures for canceling each mode. Rev. 5.00 Dec 12, 2005 page 233 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Table 9.1 Power-Down Modes State On-Chip Supporting Modules Pins Run Held Mode Sleep mode Transition Conditions CPG CPU CPU On-Chip Register Memory Held Held External Memory Refresh Canceling Procedure 1. Interrupt 2. Reset Execute Runs Halts SLEEP instruction with STBY bit cleared to 0 in STBCR*7 Execute Halts Halts SLEEP instruction with STBY bit set to 1 in STBCR*4 *5 Set MSTP bit Runs Runs of STBCR or to 1*6 halts Standby mode Held Held Halt*1 Held Selfrefresh 1. Interrupt 2. Reset Module standby function Held Held *2 Specified module halts Refresh 1. Clear MSTP bit to 0 2. Reset Power-on reset Hardware Drive CA pin Halts Halts standby low mode Held Held Halt*3 Held Selfrefresh Notes: 1. The RTC runs if the START bit in RCR2 is set to 1 (see section 16, Realtime Clock (RTC)). TMU runs when output of the RTC is used as input to its counter (see section 15, Timer (TMU)). 2. Depends on the on-chip supporting module. TMU external pin: Held SCI external pin: Reset 3. The RTC runs if the START bit in RCR2 is set to 1. TMU does not run. 4. USB and LCDC must be stopped before entering standby mode. 1) To stop LCDC, set 0 to DON bit. 2) To stop the USB Host Controller, set USBRESET bit in the HcControl register. 5. For LCDC, refer to the LPS bit in LDPMMR to confirm that power-off sequence has been completed before entering standby-mode. 6. When putting the RTC into module standby mode, first access one or more of registers RTC, SCI, and TMU. Then put the RTC into module standby mode. 7. Do not cause the CPU to transition to sleep mode, or cancel sleep mode, during a transmit or receive operation in which the USB function controller or SIOF uses DMA. Rev. 5.00 Dec 12, 2005 page 234 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.1.2 Pin Configuration Table 9.2 lists the pins used for the power-down modes. Table 9.2 Pin Name Processing state 1 Processing state 0 Pin Configuration Symbol STATUS1 STATUS0 I/O O O Description Indicate operating state of the processor. HH: Reset, HL: Sleep mode, LH: Standby mode, LL: Normal operation Note: H means high level, and L means low level. 9.1.3 Register Configuration Table 9.3 shows the configuration of the control register for the power-down modes. Table 9.3 Name Standby control register Standby control register 2 Standby control register 3 Software reset register Register Configuration Abbreviation R/W STBCR STBCR2 STBCR3 SRSTR R/W R/W R/W R/W Initial Value 1 H'00* 1 H'00* 1 H'00* Address H'FFFFFF82 H'FFFFFF88 Access Size 8 8 H'04000230 8 2 (H'A4000230)* H'04000232 8 2 (H'A4000232)* H'00* 1 Notes: 1. Initialized by power-on resets. Not initialized by manual resets but the contents are held. 2. The addresses in parentheses ( ) should be used when no address translation by the MMU is involved. Rev. 5.00 Dec 12, 2005 page 235 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.2 9.2.1 Register Description Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that sets the powerdown mode. STBCR is initialized to H'00 by a power-on reset. Bit: Initial value: R/W: 7 STBY 0 R/W 6 -- 0 R 5 -- 0 R 4 STBXTL 0 R/W 3 -- 0 R 2 MSTP2 0 R/W 1 MSTP1 0 R/W 0 MSTP0 0 R/W Bit 7--Standby (STBY): Specifies transition to standby mode. Bit 7: STBY 0 1 Description Executing SLEEP instruction puts the chip into sleep mode. Executing SLEEP instruction puts the chip into standby mode. (Initial value) Bits 6, 5, and 3--Reserved: These bits are always read as 0. The write value should always as 0. Bit 4--Standby Crystal (STBXTL): Enables/disables crystal oscillation in standby mode. Bit 4: STBXTL 0 1 Description Crystal oscillation in standby mode disabled Crystal oscillation in standby mode enabled (Initial value) Bit 2--Module Stop 2 (MSTP2): Specifies halting the clock supply to the timer unit (TMU) in the on-chip supporting module. When the MSTP2 bit is set to 1, the clock supply to the TMU is halted. Bit 2: MSTP2 0 1 Description TMU runs. Clock supply to TMU is halted. (Initial value) Rev. 5.00 Dec 12, 2005 page 236 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Bit 1--Module Stop 1 (MSTP1): Specifies halting the clock supply to the realtime clock (RTC) in the on-chip supporting module. When the MSTP1 bit is set to 1, the clock supply to RTC is halted. When the clock halts, all RTC registers cannot be accessed, but the counter keeps running. Bit 1: MSTP1 0 1 Description RTC runs. Clock supply to RTC is halted. (Initial value) Bit 0--Module Stop 0 (MSTP0): Specifies halting the clock supply to the serial communication interface (SCI) in the on-chip supporting module. When the MSTP0 bit is set to 1, the clock supply to the SCI is halted. Bit 0: MSTP0 0 1 Description SCI runs. Clock supply to SCI is halted. (Initial value) 9.2.2 Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is an 8-bit readable/writable register that controls the operation of the peripheral modules in the normal mode and sleep mode. STBCR is initialized to H'00 by a power-on reset. Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 MSTP7 0 R/W 3 MSTP6 0 R/W 2 MSTP5 0 R/W 1 MSTP4 0 R/W 0 -- 0 R MSTP9 MDCHG MSTP8 Bit 7-- Module Stop 9 (MSTP9): Specifies halting the clock supply to the X/Y memory. When the MSTP9 bit is set to 1, the clock supply to the X/Y memory is halted. Halting of the clock supply to the X/Y memory must be controlled by software (any access is not blocked by hardware). Bit 7: MSTP9 0 1 Description X/Y memory runs Clock supply to X/Y memory is halted (Initial value) Rev. 5.00 Dec 12, 2005 page 237 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Bit 6--MD5 to MD0 Pin Control (MDCHG): Specifies whether or not pins MD5 to MD0 are switched in standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when returning from standby mode by means of a reset or interrupt. Bit 6: MDCHG 0 1 Description Pins MD5 to MD0 are not switched in standby mode Pins MD5 to MD0 are switched in standby mode (Initial value) Bit 5-- Module Stop 8 (MSTP8): Specifies halting the clock supply to the user break controller (UBC) in the on-chip supporting module. When the MSTP8 bit is set to 1, the clock supply to the UBC is halted. Bit 5: MSTP8 0 1 Description UBC runs Clock supply to UBC is halted (Initial value) Bit 4--Module Stop 7 (MSTP7): Specifies halting of clock supply to the direct memory access controller (DMAC) in the on-chip supporting module. When the MSTP7 bit is set to 1, the clock supply to the DMAC is halted. Bit 4: MSTP7 0 1 Description DMAC runs Clock supply to DMAC halted (Initial value) Bit 3--Module Stop 6 (MSTP6): Specifies halting of clock supply to the D/A converter (DAC) in the on-chip supporting module. When the MSTP6 bit is set to 1, the clock supply to the DAC is halted. Bit 3: MSTP6 0 1 Description DAC runs Clock supply to DAC halted (Initial value) Bit 2--Module Stop 5 (MSTP5): Specifies halting of clock supply to the A/D converter (ADC) in the on-chip supporting module. When the MSTP5 bit is set to 1, the clock supply to the ADC is halted and all registers are initialized. Rev. 5.00 Dec 12, 2005 page 238 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Bit 2: MSTP5 0 1 Description ADC runs Clock supply to ADC halted, and all registers initialized (Initial value) Bit 1--Module Stop 4 (MSTP4): Specifies halting the clock supply to the serial communication interface SCI (SCIF) with FIFO. When the MSTP4 bit is set to 1, the clock supply to the SCIF is halted Bit 1: MSTP4 0 1 Description SCIF runs Clock supply to SCI2 (SCIF) halted (Initial value) Bit 0-- Reserved: This bit is always read as 0. The write value should always as 0. 9.2.3 Standby Control Register 3 (STBCR3) The standby control register 3 (STBCR3) is an 8-bit readable/writable register that controls standby operation for the on-chip supporting modules. STBCR3 is initialized to H'00 by a poweron reset. Bit: Initial value: R/W: 7 MSTP17 0 R/W 6 -- 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 -- 0 R/W 1 0 R/W 0 0 R/W MSTP15 MSTP14 MSTP13 MSTP11 MSTP10 Bit 7-- Module Stop 17 (MSTP17): Specifies halting the clock supply to the serial IO with FIFO interface (SIOF). When the MSTP17 bit is set to 1, the clock supply to the serial IO with FIFO interface (SIOF) is halted. Bit 7: MSTP17 0 1 Description SIOF runs Clock supply to SIOF halted (Initial value) Bit 6-- Reserved: This bit is always read as 0. The write value should always as 0. Rev. 5.00 Dec 12, 2005 page 239 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Bit 5-- Module Stop 15 (MSTP15): Specifies halting the clock supply to the AFE interface (AFE IF). When the MSTP15 bit is set to 1, the clock supply to the AFE interface is halted. Bit 5: MSTP15 0 1 Description AFE interface runs Clock supply to AFE interface halted (Initial value) Bit 4-- Module Stop 14 (MSTP14): Specifies halting the clock supply to the USB function module (USBF). When the MSTP14 bit is set to 1, the clock supply to the USBF is halted. Bit 4: MSTP14 0 1 Description USBF runs Clock supply to USBF halted (Initial value) Bit 3--Module Stop 13 (MSTP13): Specifies halting the clock supply to the USB host controller (USBH). When the MSTP13 bit is set to 1, the clock supply to the USBH is halted. Bit 3: MSTP13 0 1 Description USBH runs Clock supply to USBH halted (Initial value) Note: This bit should not be set to 1 when MSTP14 (bit 4) is 0. Bit 2----Reserved: This bit is always read as 0. The write value should always as 0. Bit 1-- Module Stop 11 (MSTP11): Specifies halting the clock supply LCD Controller (LCDC). When the MSTP11 bit is set to 1, the clock supply to the LCDC is halted. Bit 1: MSTP11 0 1 Description LCDC runs Clock supply to LCDC halted (Initial value) Bit 0-- Module Stop 10 (MSTP10): Specifies halting the clock supply to PC Card Controller (PCC). When the MSTP10 bit is set to 1, the clock supply to the PCC is halted. Bit 0: MSTP10 0 1 Description PCC runs Clock supply to PCC halted (Initial value) Rev. 5.00 Dec 12, 2005 page 240 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.2.4 Module Software Reset Register (SRSTR) The Software Reset Register (SRSTR) is an 8-bit readable/writable register that controls module reset operation equivalent to power-on reset. SRSTR is initialized to H'00 by a power-on reset. Bit: Initial value: R/W: 7 SIOFR 6 -- 5 AFECR 4 USBFR 3 USBHR 2 LBSCR 1 LCDCR 0 PCCR 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7-- SIOF Reset (SIOFR): When the SIOF bit is set to 1, the serial I/O (SIOF) is reset. 0 should be written after writing 1. Bit 7: SIOFR 0 1 Description Not reset SIOF Resets SIOF (Initial value) Bit 6--Reserved: This bit is always read as 0. The write value should always be 0. Bit 5-- AFEIF Reset (AFECR): When the AFEC bit is set to 1, the AFE interface (AFEIF) is reset. 0 should be written after writing 1. Bit 5: AFECR 0 1 Description Not reset AFEIF Resets AFEIF (Initial value) Bit 4-- USBF Reset (USBFR): When the USBF bit is set to 1, the SUB function module (USBF) is reset. 0 should be written after writing 1. Bit 4: USBFR 0 1 Description Not reset USBF Resets USBF (Initial value) Rev. 5.00 Dec 12, 2005 page 241 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Bit 3-- USBH Reset (USBHR): When the USBH bit is set to 1, the USB host controller is reset. 0 should be written after writing 1. Bit 3: USBHR 0 1 Description Not reset USBH Resets USBH (Initial value) Bit 2-- LBSC Reset (LBSCR): When the LBSC bit is set to 1, the Li bus state controller (LBSC) is reset. 0 should be written after writing 1. Bit 2: LBSCR 0 1 Description Not reset LBSC Resets LBSC (Initial value) Bit 1-- LCDC Reset (LCDCR): When the LCDC bit is set to 1, the LCD controller (LCDC) is reset. 0 should be written after writing 1. Bit 1: LCDCR 0 1 Description Not reset LCDC Resets LCDC (Initial value) Bit 0-- PCC Reset (PCCR): When the PCC bit is set to 1, PC card controller (PCC) is reset. 0 should be written after writing 1. Bit 0: PCCR 0 1 Description Not reset PCC Resets PCC (Initial value) Rev. 5.00 Dec 12, 2005 page 242 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.3 9.3.1 Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers are retained. The on-chip supporting modules continue to run during sleep mode and the clock continues to be output to the CKIO and CKIO2 pins. In sleep mode, the STATUS1 pin is set to high and the STATUS0 pin low. 9.3.2 Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module interrupt, PINT) or reset. Interrupts are accepted during sleep mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction. Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip supporting module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code corresponding to the interrupt source is set in the INTEVT and INTEVT2 registers. Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset. 9.4 9.4.1 Standby Mode Transition to Standby Mode To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip moves from the program execution state to standby mode. In standby mode, not only the CPU, but the clock and on-chip supporting modules are halted. The clock output from the CKIO and CKIO2 pins also halts. The contents of the CPU and cache register are held, but some on-chip supporting modules are initialized. Table 9.4 lists the states of registers in standby mode. Rev. 5.00 Dec 12, 2005 page 243 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Table 9.4 Module Register States in Standby Mode Registers Initialized -- -- -- -- TSTR register -- All registers -- -- -- -- -- -- -- -- Registers Retaining Data All registers All registers All registers All registers Registers other than TSTR All registers -- All registers All registers All registers All registers All registers All registers All registers Registers other than PCC0ISR* Interrupt controller (INTC) On-chip clock pulse generator (OSC) User break controller (UBC) Bus state controller (BSC) Timer unit (TMU) Realtime clock (RTC) A/D converter (ADC) D/A converter (DAC) Li bus state controller (LBSC) LCD controller (LCDC) USB host controller (USBH) USB function module (USBF) AFE interface (AFEIF) Serial IO with FIFO (SIOF) PC card controller (PPC) Note: * PCC0ISR reflects the normal status. The procedure for moving to standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. Set the WDT's timer counter (WTCNT) to 0 and set a value to the CKS2 to CKS0 bits in the WTCSR register to secure the specified oscillation settling time. 2. After the STBY bit in the STBCR register is set to 1, the SLEEP instruction is executed. 3. When the chip enters standby mode and the clocks within the chip are halted, he STATUS1 pin output goes low and the STATUS0 pin output goes high. Rev. 5.00 Dec 12, 2005 page 244 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.4.2 Canceling Standby Mode Standby mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module interrupt or PINT) or a reset. Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRL, IRQ, PINT*1, or on-chip supporting module (except the interval timer)*2 interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low. Interrupt exception handling then begins and a code corresponding to the interrupt source is set in the INTEVT and INTEVT2 registers. After branching to the interrupt processing routine occurs, clear the STBY bit in the STBCR register. The WTCNT stops automatically. If the STBY bit is not cleared, WTCNT continues operation and transits to the standby mode*3 when it reaches H'80. This function prevents the data from being destroyed due to a rising voltage under an unstable power supply. Interrupts are accepted during standby mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction. Immediately after an interrupt is detected, the phase of the clock output of the CKIO and CKIO2 pin may be unstable, until the standby mode is canceled. The canceling condition is that the interrupt request level (IRQ, IRL, or on-chip supporting module interrupt) is higher than the mask level in the I3 to I0 bits in the SR register. Notes: 1. When the RTC is being used, standby mode can be canceled using IRL3 to IRL0, IRQ4 to IRQ0 or PINT0 to PINT5. 2. Standby mode can be canceled with an RTC or TMU (only when running on the RTC clock) interrupt. 3. Use a power-on reset to cancel standby mode. Operation is not guaranteed in the case of a manual reset or interrupt input. Rev. 5.00 Dec 12, 2005 page 245 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Interrupt request Crystal oscillator settling time and PLL synchronization time WTCNT value H'FF WDT overflow and branch to interrupt handling routine Clear bit STBCR.STBY before WTCNT reaches H'80. When STBCR.STBY is cleared, WTCNT halts automatically. H'80 Time Figure 9.1 Canceling Standby Mode with STBCR.STBY Canceling with a Reset: Standby mode can be canceled with a reset (power-on or manual). Keep the RESET or RESETM pin low until the clock oscillation settles. The internal clock will be output continuously to the CKIO pin. 9.4.3 Clock Pause Function In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed. This function is used as follows: 1. Enter standby mode using the procedure for changing to standby mode. 2. When the chip enters standby mode and the clock stopped within the chip, the STATUS1 pin output is low and the STATUS0 pin output is high. 3. When the STATUS1 pin goes low and the STATUS0 pin goes high, the input clock is stopped or the frequency is changed. 4. When the frequency is changed, an NMI, IRL, IRQ, PINT or on-chip supporting module (except the internal timer) interrupt is input after changing the frequency. When the clock is stopped, the same interrupts are input after the clock is applied. 5. After the time set in the WDT has elapsed, the clock starts being applied within the chip, the STATUS1 and STATUS0 pins both go low, operation resumes from the interrupt exception handling. Rev. 5.00 Dec 12, 2005 page 246 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.5 9.5.1 Module Standby Function Transition to Module Standby Function Setting the standby control register STBCR, STBCR2, STBCR3, MSTP17, MSTP15 to MSTP13, MSTP11 to MSTP4, and MSTP 2 to MSTP0 bits to 1 halts the clock supply to the corresponding on-chip supporting modules. By using this function, the power consumption in normal mode and sleep mode can be reduced. In the module standby function, external pins of the on-chip supporting modules are different depending on the on-chip supporting modules. TMU external pins hold their state prior to the halt. SCI external pins go to the reset state. With a few exceptions, all registers hold their values. Rev. 5.00 Dec 12, 2005 page 247 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Bit MSTP17 MSTP15 MSTP14 MSTP13 Value 0 1 0 1 0 1 0 1 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP2 MSTP1 MSTP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description SIOF runs. Clock supply to SIOF halted. AFEIF runs. Clock supply to AFEIF halted. USBF runs. Clock supply to USBF halted. USBH runs. Clock supply to USBH halted. This bit should not be set to 1 when MSTP14 (bit 4) is 0. LCDC runs. Clock supply to LCDC halted. PCC runs. Clock supply to PCC halted. X/Y memory runs. Clock supply to X/Y memory halted. UBC runs. Clock supply to UBC halted. DMAC runs. Clock supply to DMAC halted. DAC runs. Clock supply to DAC halted. ADC runs. Clock supply to ADC halted, and all registers initialized. SCIF runs. Clock supply to SCIF halted. TMU runs. Clock supply to TMU halted.* RTC runs. Clock supply to RTC halted. Register access prohibited.* SCI runs. Clock supply to SCI halted. 2 1 Notes: 1. The initialized registers are the same as in the standby mode (see table 9.4). 2. The counter runs. Rev. 5.00 Dec 12, 2005 page 248 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.5.2 Clearing the Module Standby Function The module standby function can be cleared by clearing the MSTP17, MSTP15 to MSTP13, MSTP11 to MSTP4, and MSTP2 to MSTP0 bits to 0, or by a power-on reset or manual reset. 9.6 Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 pin changes is shown in figures 9.2 to 9.9. The meanings of STATUS are as follows: * Reset: * Sleep: HH (STATUS1 is high, STATUS0 is high) HL (STATUS1 is high, STATUS0 is low) * Standby: LH (STATUS1 is low, STATUS0 is high) * Normal: LL (STATUS1 is low, STATUS0 is low) The meanings of clock units are as follows: * Bcyc: Bus clock cycle * Pcyc: Peripheral clock cycle * Rcyc: 32.768-kHz RTC clock cycle 9.6.1 Timing for Resets Power-On Reset CKIO, CKIO2* PLL settling time RESETP STATUS Normal Reset Normal 0 to 5 Bcyc 0 to 30 Bcyc Note: * CKIO2 can be used at only clock modes 0, 1 and 2. Figure 9.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output Rev. 5.00 Dec 12, 2005 page 249 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Manual Reset CKIO, CKIO*2 RESETM STATUS Normal Reset Normal 0 Bcyc or more*1 0 to 30 Bcyc Notes: 1. During manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end. 2. CKIO2 can be used at only clock modes 0, 1 and 2. Figure 9.3 Manual Reset STATUS Output 9.6.2 Timing for Canceling Standbys Standby to Interrupt Oscillation stops Interrupt request WDT overflow CKIO, CKIO2* WDT count Normal Standby Normal STATUS Note: * CKIO2 can be used at only clock modes 0, 1 and 2. Figure 9.4 Standby to Interrupt STATUS Output Rev. 5.00 Dec 12, 2005 page 250 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Standby to Power-On Reset Oscillation stops Reset CKIO, CKIO2*2 RESETP*1 STATUS Normal Standby *3 Reset 0 to 30 Bcyc Normal 0 to 10 Bcyc Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESETP low during PLL's oscillation settling time. 2. CKIO2 can be used at only clock modes 0, 1 and 2. 3. Undefined Figure 9.5 Standby to Power-On Reset STATUS Output Standby to Manual Reset Oscillation stops Reset CKIO, CKIO2*2 RESETM*1 STATUS Normal Standby Reset 0 to 20 Bcyc Normal Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESETM low during PLL's oscillation settling time. 2. CKIO2 can be used at only clock modes 0, 1 and 2. Figure 9.6 Standby to Manual Reset STATUS Output Rev. 5.00 Dec 12, 2005 page 251 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.6.3 Timing for Canceling Sleep Mode Sleep to Interrupt Interrupt request CKIO, CKIO2* STATUS Normal Sleep Normal Note: * CKIO2 can be used at only clock modes 0, 1 and 2. Figure 9.7 Sleep to Interrupt STATUS Output Sleep to Power-On Reset Reset CKIO, CKIO2*2 RESETP*1 STATUS Normal Sleep *3 Reset 0 to 30 Bcyc Normal 0 to 10 Bcyc Notes: 1. When the PLL's multiplication ratio is changed by a power-on reset, keep RESETP low during PLL's oscillation settling time. 2. CKIO2 can be used at only clock modes 0, 1 and 2. 3. Undefined Figure 9.8 Sleep to Power-On Reset STATUS Output Rev. 5.00 Dec 12, 2005 page 252 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset Sleep to Manual Reset Reset CKIO, CKIO2*2 RESETM*1 STATUS Normal Sleep 0 to 80 Bcyc Reset 0 to 30 Bcyc Normal Notes: 1. Keep RESETM low until the STATUS becomes reset. 2. CKIO2 can be used at only clock modes 0, 1 and 2. Figure 9.9 Sleep to Manual Reset STATUS Output Rev. 5.00 Dec 12, 2005 page 253 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.7 9.7.1 Hardware Standby Mode Transition to Hardware Standby Mode To enter hardware standby mode, set the CA pin low. In hardware standby mode, all modules except for any modules that run with RTC clock are halted as well as in standby mode entered by sleep instruction. Differences between hardware standby mode and standby mode are as follows. 1. Interrupts and manual reset are not accepted in hardware standby mode. 2. The TMU does not run in hardware standby mode. Operation when the CA pin goes low depends on the CPG status. 1. In standby mode The chip enters hardware standby mode, clock remains halted. Interrupts and manual reset are not accepted and the TMU halts. 2. During WDT runs when clearing standby mode with an interrupt The chip enters hardware standby mode after the CPU resumes operation once standby mode is cleared. 3. In sleep mode The chip enters hardware standby mode after the CPU resumes operation once sleep mode is cleared. Note that CA pin must keep low during hardware standby mode. 9.7.2 Clearing the Hardware Standby Mode Hardware standby mode can be cleared only by power-on reset. The clock starts oscillation by setting CA pin high while RESETP pin is low. At this time, keep the RESETP pin low until the clock oscillation settles. Then, the CPU starts power-on reset processing after setting the RESETP pin high. The operation is not guaranteed when an interrupt or manual reset is occurred. Rev. 5.00 Dec 12, 2005 page 254 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset 9.7.3 Timing of Hardware Standby Mode The timings of each pin in hardware standby mode are shown in figures 9.10 and 9.11. CA pin is sampled by EXTAL2 (32.768 kHz). Hardware standby request is detected when two continuous cycles go low in this clock. Keep CA pin low during hardware standby mode. The clock starts oscillation when the CA pin is set high after setting the RESETP pin low. CKIO, CKIO2*6 CA RESETP STATUS Normal*3 Standby*2 *7 Reset*1 0-10Bcyc*4 2 Rcyc or more*5 Notes: 1. 2. 3. 4. 5. 6. 7. Reset: HH (STATUS1 is high, STATUS0 is high) Standby: LH (STATUS1 is low, STATUS0 is high) Normal: LL (STATUS1 is low, STATUS0 is low) Bcyc: Bus clock cycle Rcyc: EXTAL2 (32.768 kHz) clock cycle CKIO2 can be used at only clock modes 0,1 and 2. Undefined Figure 9.10 Hardware Standby Mode Timing (CA = Low in Normal Operation) Rev. 5.00 Dec 12, 2005 page 255 of 1034 REJ09B0254-0500 Section 9 Power-Down Modes and Software Reset CKIO, CKIO2*6 CA RESETP STATUS Standby WDT operation Normal*3 Standby*2 *7 Reset*1 0-10Bcyc*4 2 Rcyc or more*5 Notes: 1. 2. 3. 4. 5. 6. 7. Reset: HH (STATUS1 is high, STATUS0 is high) Standby: LH (STATUS1 is low, STATUS0 is high) Normal: LL (STATUS1 is low, STATUS0 is low) Bcyc: Bus clock cycle Rcyc: EXTAL2 (32.768 kHz) clock cycle CKIO2 can be used at only clock modes 0,1 and 2. Undefined Figure 9.11 Hardware Standby Mode Timing (CA = Low during WDT Operation while Standby Mode is Cleared) Rev. 5.00 Dec 12, 2005 page 256 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits Section 10 On-Chip Oscillation Circuits 10.1 Overview The on-chip oscillation circuits consist of the clock pulse generator (CPG) and watchdog timer (WDT). The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down modes. The watchdog timer (WDT) is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standby, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer. 10.1.1 Features The CPG has the following features: * Four clock modes: Selection of four clock modes for different frequency ranges, power consumption, direct crystal input, and external clock input. * Three clocks generated independently: An internal clock for the CPU, cache, and TLB (I); a peripheral clock (P) for the on-chip supporting modules; and a bus clock (CKIO) for the external bus interface. * Frequency change function: Internal and peripheral clock frequencies can be changed independently using the PLL circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control: The clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. Rev. 5.00 Dec 12, 2005 page 257 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits The WDT has the following features: * Can be used to ensure the clock settling time: Use the WDT to cancel standby mode and the temporary standby which occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. Selection of power-on reset or manual reset. * Generates interrupts in interval timer mode: Internal timer interrupts occur after counter overflow. * Selection of eight counter input clocks. Eight clocks (x1 to x1/4096) can be obtained by dividing the peripheral clock. Rev. 5.00 Dec 12, 2005 page 258 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.2 10.2.1 Overview of the CPG CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 10.1. Clock pulse generator CAP1 CKIO2 PLL circuit 1 (x 1, 2, 3, 4, 6) Divider 1 x1 x 1/2 x 1/3 x1/4 Divider 2 x1 x 1/2 x 1/3 x 1/4 x 1/6 CKIO Cycle = Bcyc CAP2 XTAL EXTAL Crystal oscillator PLL circuit 2 (x 1, 4) Internal clock (I) Cycle = Icyc Peripheral clock (P) Cycle = Pcyc Bus clock (P) Cycle = Bcyc CPG control unit Clock frequency control circuit Standby control circuit Standby control MD2 MD1 MD0 FRQCR STBCR Bus interface Internal bus Legend: FRQCR: Frequency control register STBCR: Standby control register Figure 10.1 Block Diagram of Clock Pulse Generator Rev. 5.00 Dec 12, 2005 page 259 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits The clock pulse generator blocks function as follows: 1. PLL Circuit 1 PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock frequency from the CKIO pin or PLL circuit 2. The multiplication rate is set by the frequency control register. When this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the CKIO pin. 2. PLL Circuit 2 PLL circuit 2 leaves quadruples the frequency of the crystal oscillator or the input clock frequency coming from the EXTAL pin. The multiplication ratio is fixed by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and MD2. See table 10.3 for more information on clock operation modes. 3. Crystal Oscillator This oscillator is used when a crystal oscillator element is connected to the XTAL and EXTAL pins. It operates according to the clock operating mode setting. 4. Divider 1 Divider 1 generates a clock at the operating frequency used by the internal clock. The operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. 5. Divider 2 Divider 2 generates a clock at the operating frequency used by the peripheral clock. The operating frequencies can be 1, 1/2, 1/3,1/4, or 1/6 times the output frequency of PLL Circuit 1 or the clock frequency of the CKIO pin, as long as it stays at or below the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. 6. Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency using the MD pin and the frequency control register. 7. Standby Control Circuit The standby control circuit controls the state of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. Frequency Control Register The frequency control register has control bits assigned for the following functions: clock output/non-output from the CKIO pin, PLL standby, the frequency multiplication ratio of PLL 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. Standby Control Register The standby control register has bits for controlling the power-down modes. See section 9, Power-Down Modes and Software Reset, for more information. Rev. 5.00 Dec 12, 2005 page 260 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.2.2 CPG Pin Configuration Table 10.1 lists the CPG pins and their functions. Table 10.1 Clock Pulse Generator Pins and Functions Pin Name Mode control pins Symbol MD0 MD1 MD2 Crystal I/O pins (clock input pins) XTAL EXTAL CKIO CKIO2 CAP1 CAP2 I/O I I I O I I/O O I I Connects a crystal oscillator. Connects a crystal oscillator. Also used to input an external clock. Inputs or outputs an external clock. Output external clock. Level can be fixed. Only clock modes 0, 1, 2 can be supported for this pin. Connects capacitor for PLL circuit 1 operation (recommended value 470 pF). Connects capacitor for PLL circuit 2 operation (recommended value 470 pF). Description Set the clock operating mode. Clock I/O pin Clock Out pin Capacitor connection pins For PLL 10.2.3 CPG Register Configuration Table 10.2 shows the CPG register configuration. Table 10.2 Register Configuration Register Name Frequency control register CKIO2 Control Register 2 Abbreviation FRQCR CKIO2CR R/W R/W R/W Initial Value H'0102 H'0000 Address H'FFFFFF80 H'0400023A (H'A400023A)* Access Size 16 bits 16 bits Note: * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 261 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.3 Clock Operating Modes Table 10.3 shows the relationship between the mode control pin (MD2 to MD0) combinations and the clock operating modes. Table 10.4 shows the usable frequency ranges in the clock operating modes. Table 10.3 Clock Operating Modes Pin Values Mode 0 MD2 MD1 MD0 0 0 0 Clock I/O Source EXTAL Output CKIO PLL2 On/Off On, multiplication ratio: 1 On, multiplication ratio: 4 On, multiplication ratio: 4 Off PLL1 On/Off On Divider 1 Divider 2 CKIO Input Input Frequency PLL1 output PLL1 (EXTAL) 1 0 0 1 EXTAL CKIO On PLL1 output PLL1 (EXTAL) x 4 2 0 1 0 Crystal CKIO oscillator On PLL1 output PLL1 (Crystal) x 4 7 1 1 1 CKIO -- On PLL1 output PLL1 (CKIO) Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by PLL circuit 2 before being supplied inside this LSI. PLL circuit 1 is constantly on. An input clock frequency of 24 MHz to the maximum frequency of CKIO can be used. For details on the CKIO maximum frequency, see section 32, Electrical Characteristics. Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency external clock to be used. An input clock frequency of 6 MHz to1/4 of the maximum frequency of CKIO can be used. For details on the CKIO maximum frequency, see section 32, Electrical Characteristics. Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by PLL circuit 2 before being supplied inside this LSI, allowing a low crystal frequency to be used. A crystal oscillation frequency of 6 MHz to 1/4 of the maximum frequency of CKIO can be used. For details on the CKIO maximum frequency, see section 32, Electrical Characteristics. Rev. 5.00 Dec 12, 2005 page 262 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to this LSI. In modes 0 to 2, the system clock is generated from the output of this LSI's CKIO pin. Consequently, if a large number of ICs are operating on the clock cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale system. If a large number of ICs are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ICs can operate synchronously by distributing the clocks to each one. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Rev. 5.00 Dec 12, 2005 page 263 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits Table 10.4 Available Combination of Clock Mode and FRQCR Values Clock Mode 0 FRQCR H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 H'A111 1, 2 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 H'A111 PLL1 ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3) ON (x 3) ON (x 3) ON (x 3) ON (x 6) ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3) ON (x 3) ON (x 3) ON (x 3) ON (x 6) PLL2 ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 1) Clock Rate* (I:B:P) 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 3:1:1 3:1:1/2 1:1:1 1:1:1/2 6:1:1 4:4:4 4:4:2 4:4:1 8:4:4 8:4:2 4:4:4 4:4:2 16:4:4 8:4:4 4:4:4 12:4:4 12:4:2 4:4:4 4:4:2 24:4:4 Rev. 5.00 Dec 12, 2005 page 264 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits Clock Mode 7 FRQCR H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 H'A111 Note: * Taking input clock as 1 PLL1 ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3) ON (x 3) ON (x 3) ON (x 3) ON (x 6) PLL2 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Clock Rate* (I:B:P) 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 3:1:1 3:1:1/2 1:1:1 1:1:1/2 6:1:1 Cautions: 1. The frequency ranges of the input clock and crystal oscillator should be set within the specified frequency range based on the clock rate in table 10.4, and section 32.3, AC Characteristics. 2. The input to divider 1 becomes the output of PLL circuit 1 when PLL circuit 1 is on. 3. The input of divider 2 becomes the output of: * PLL circuit 1 4. The frequency of the internal clock (I) becomes: * * * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on. Do not set the internal clock frequency lower than the CKIO pin frequency. Depending on the product, the clock ratio should be set to produce a frequency within one of the ranges indicated below. 100 MHz products: 24 MHz to 100 MHz 160 MHz products: 24 MHz to 160 MHz Rev. 5.00 Dec 12, 2005 page 265 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 5. Bus clock (B) frequency: * Depending on the product, the clock ratio should be set to produce a frequency within one of the ranges indicated below. 100 MHz products: 24 MHz to 50 MHz 160 MHz products: 24 MHz to 66.64 MHz 6. The frequency of the peripheral clock (P) becomes: * * * The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2. For all products, the peripheral clock frequency (P) should be set within the frequency range 6 MHz to 33.34 MHz and no higher than the frequency of the CKIO pin. The peripheral clock frequency (P) should be set to 13 MHz or higher if the USB function module is used. 7. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. 8. x1, x2, x3, x4, or x6 can be used as the multiplication ratio of PLL circuit 1. x1, x1/2, x1/3, and x1/4 can be selected as the division ratio of divider 1. x1, x1/2, x1/3, x1/4, and x1/6 can be selected as the division ratio of divider 2. Set the rate in the frequency control register. The on/off state of PLL circuit 2 is determined by the mode. Rev. 5.00 Dec 12, 2005 page 266 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.4 10.4.1 Register Descriptions Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit read/write register that specify the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. FRQCR is initialized to H'0102 by a power-on reset, but retains its value in a manual reset and in standby mode. Bit: Initial value: R/W: 15 STC2 0 R/W 14 IFC2 0 R/W 13 PFC2 0 R/W 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 1 R Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 STC1 0 R/W 4 STC0 0 R/W 3 IFC1 0 R/W 2 IFC0 0 R/W 1 PFC1 1 R/W 0 PFC0 0 R/W Bits 15, 5 and 4--Frequency Multiplication Ratio (STC2, STC1, STC0): These bits specify the frequency multiplication ratio of PLL circuit 1. Bit 15: STC2 0 0 1 0 1 Bit 5: STC1 0 0 0 1 0 Bit 4: STC0 0 1 0 0 1 Description x1 x2 x3 x4 x6 Reserved (illegal setting) (Initial value) Values other than above Note: Do not set the output frequency of PLL circuit 1 higher than the maximum frequency of the CPU specified in AC Characteristics. Rev. 5.00 Dec 12, 2005 page 267 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits Bits 14, 3 and 2--Internal Clock Frequency Division Ratio (IFC2, IFC1, IFC0): These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. Bit 14: IFC2 0 0 1 0 Bit 3: IFC1 0 0 0 1 Bit 2: IFC0 0 1 0 0 Description x1 x 1/2 x 1/3 x 1/4 Reserved (illegal setting) (Initial value) Values other than above Note: Do not set the internal clock frequency lower than the CKIO frequency. Bits 13, 1 and 0--Peripheral Clock Frequency Division Ratio (PFC2, PFC1, PFC0): These bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO pin. Bit 13: PFC2 0 0 1 0 1 Bit 1: PFC1 0 0 0 1 0 Bit 0: PFC0 0 1 0 0 1 Description x1 x 1/2 x 1/3 x 1/4 x 1/6 Reserved (illegal setting) (Initial value) Values other than above Note: Do not set the peripheral clock frequency higher than the frequency of the CKIO pin. Bits 12 to 9, 7 and 6--Reserved: These bits are always read as 0. The write value should always be 0. Bit 8--Reserved: This bit is always read as 1. The write value should always be 1. Rev. 5.00 Dec 12, 2005 page 268 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.4.2 CKIO2 Control Register (CKIO2CR) CKIO2CR controls CKIO2 pin output. Upper 8 Bits: Initial value: R/W: Lower 8 Bits: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 CKIO2EN 0 R/W Bits 15 to 1--Reserved: These bits always read 0. The write value should always be 0. Bit 0--CKIO2 (CKIO2EN): Selects output or not output (Hi-Z) for CKIO2 clock. Bit 0: CKIO2EN 0 1 Description Output Not output (Hi-Z) (Initial value) Rev. 5.00 Dec 12, 2005 page 269 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.5 Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of these are controlled by software through the frequency control register. The methods are described below. 10.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR register TME bit = 0: WDT stops WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock WTCNT counter: Initial counter value 3. Set the desired value in the STC2, STC1 and STC0 bits. The division ratio can also be set in the IFC2 to IFC0 bits and PFC2 to PFC0 bits. 4. The processor pauses internally and the WDT starts incrementing. In clock modes 0 to 2 and 7, the internal and peripheral clocks both stop. 5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. 10.5.2 Changing the Division Ratio The WDT will not count unless the multiplication rate is changed simultaneously. 1. In the initial state, IFC2 to IFC0 = 000 and PFC2 to PFC0 = 010. 2. Set the IFC2, IFC1, IFC0, PFC2, PFC1, and PFC0 bits to the new division ratio. The values that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, the processor will malfunction. 3. The clock is immediately supplied at the new division ratio. Rev. 5.00 Dec 12, 2005 page 270 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.6 10.6.1 Overview of the WDT Block Diagram of the WDT Figure 10.2 shows a block diagram of the WDT. WDT Standby cancellation Internal reset request Interrupt request Standby control Standby mode Peripheral clock Divider Clock selection Clock selector Interrupt control WTCSR Bus interface Overflow Clock WTCNT Reset control Legend: WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Internal bus Figure 10.2 Block Diagram of the WDT Rev. 5.00 Dec 12, 2005 page 271 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.6.2 Register Configurations The WDT has two registers that select the clock, switch the timer mode, and perform other functions. Table 10.5 shows the WDT register. Table 10.5 Register Configuration Name Watchdog timer counter Watchdog timer control/ status register Abbreviation WTCNT WTCSR R/W R/W* R/W* Initial Value H'00 H'00 Address H'FFFFFF84 H'FFFFFF86 Access Size R: 8; W: 16* R: 8; W: 16* Note: * Write with a word access. Write H'5A and H'A5, respectively, in the upper bytes. Byte or longword writes are not possible. Read with a byte access. 10.7 10.7.1 WDT Registers Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit read/write counter that increments on the selected clock. The WTCNT differs from other registers in that it is more difficult to write to. See section 10.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The WTCNT counter is initialized to H'00 by a power-on reset through the RESETP pin. Use a word access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT. Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Rev. 5.00 Dec 12, 2005 page 272 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.7.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. The WTCSR differs from other registers in that it is more difficult to write to. See section 10.7.3, Notes on Register Access, for details. Its address is H'FFFFFF86. The WTCSR register is initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow causes an internal reset, the WTCSR retains its value. When used to count the clock settling time for canceling a standby, it retains its value after counter overflow. Use a word access to write to the WTCSR counter, with H'A5 in the upper byte. Use a byte access to read WTCSR. Bit: Initial value: R/W: 7 TME 0 R/W 6 WT/IT 0 R/W 5 RSTS 0 R/W 4 WOVF 0 R/W 3 IOVF 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the WDT in standby mode or when changing the clock frequency. Bit 7: TME 0 1 Description Timer disabled: Count-up stops and WTCNT value is retained Timer enabled (Initial value) Bit 6--Timer Mode Select (WT/IT Selects whether to use the WDT as a watchdog timer or an IT): IT interval timer. Bit 6: WT/IT IT 0 1 Description Use as interval timer Use as watchdog timer (Initial value) Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly. Bit 5--Reset Select (RSTS): Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. Bit 5: RSTS 0 1 Description Power-on reset Manual reset (Initial value) Rev. 5.00 Dec 12, 2005 page 273 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits Bit 4--Watchdog Timer Overflow (WOVF): Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. Bit 4: WOVF 0 1 Description No overflow WTCNT has overflowed in watchdog timer mode (Initial value) Bit 3--Interval Timer Overflow (IOVF): Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. Bit 3: IOVF 0 1 Description No overflow WTCNT has overflowed in interval timer mode (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow period in the table is the value when the peripheral clock (P) is 15 MHz. Bit 2: CKS2 0 Bit 1: CKS1 0 1 1 0 1 Bit 0: CKS0 0 1 0 1 0 1 0 1 Clock Division Ratio 1 1/4 1/16 1/32 1/64 1/256 1/1024 1/4096 (Initial value) Overflow Period (when P = 15 MHz) 17 s 68 s 273 s 546 s 1.09 ms 4.36 ms 17.48 ms 69.91 ms Note: If bits CKS2 to CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. Rev. 5.00 Dec 12, 2005 page 274 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.7.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 10.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write 15 Address: H'FFFFFF84 H'5A 8 7 Write data 0 WTCSR write 15 Address: H'FFFFFF86 H'A5 8 7 Write data 0 Figure 10.3 Writing to WTCNT and WTCSR 10.8 10.8.1 Using the WDT Canceling Standby Mode The WDT can be used to cancel standby mode with an NMI or other interrupts. The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RESETP pin low until the clock stabilizes.) 1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. Rev. 5.00 Dec 12, 2005 page 275 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 3. Move to standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting the edge change of the NMI signal or detecting interrupts. 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in the interrupt processing program and this will stop the WDT. When the STBY bit remains 1, the SH7727 again enters the standby mode when the WDT has counted up to H'80. This standby mode can be canceled by power-on resets. 10.8.2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits of WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When the frequency control register (FRQCR) is written, the clock stops and the processor enters standby mode temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 5. The counter stops at the values H'00 to H'01. The stop value depends on the clock ratio. 10.8.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the type of reset specified by the RSTS bit. The counter then resumes counting. Rev. 5.00 Dec 12, 2005 page 276 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits 10.8.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to INTC. The counter then resumes counting. 10.9 Notes on Board Design When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. Avoid crossing signal lines CL1 CL2 R EXTAL XTAL SH7727 Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal oscillator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator Rev. 5.00 Dec 12, 2005 page 277 of 1034 REJ09B0254-0500 Section 10 On-Chip Oscillation Circuits Decoupling Capacitors: Insert a laminated ceramic capacitor of 0.01 to 0.1 F as a passive capacitor for each VSS/VCC pair. Mount the passive capacitors to the SH3 power supply pins, and use components with a frequency characteristic suitable for the SH3 operating frequency, as well as a suitable capacitance value. Digital system VSS/VCC pairs: 35-37, 91-93, 137-139, 155-157, 177-178, 200-202 Digital system VSS Q/VCC Q pairs: 18-20, 29-31, 42-44, 53-55, 64-66, 75-77, 86-88, 100-102, 115117, 132-134, 159-161, 188-190, 207-209 On-chip oscillator VSS/VCC pairs: 1-4 When Using a PLL Oscillator Circuit: Keep the wiring from the PLL VCC and VSS connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. Ground the oscillation stabilization capacitors C1 and C2 to VSS (PLL1) and VSS (PLL2), respectively. Place C1 and C2 close to the CAP1 and CAP2 pins and do not locate a wiring pattern in the vicinity. In clock mode 7, connect the EXTAL pin to VCC or VSS and leave the XTAL pin open. Avoid crossing signal lines VCC (PLL2) Power supply CAP2 VSS (PLL2) VCC (PLL1) VSS CAP1 C1 VSS (PLL1) C2 VCC Reference values C1 = 470 pF C2 = 470 pF Figure 10.5 Points for Attention when Using PLL Oscillator Circuit Notes on using pins CKIO and CKIO2 as the clock outputs: Perform board design so that the sum of pin capacitances of the CPU and socket that are connected to pins are 50 pF or less. Rev. 5.00 Dec 12, 2005 page 278 of 1034 REJ09B0254-0500 Section 11 Extend Clock Pulse Generator for USB (EXCPG) Section 11 Extend Clock Pulse Generator for USB (EXCPG) 11.1 11.1.1 Overview EXCPG The SH7727 has an on-chip USB interface (USB) which requires a fixed 48-MHz clock source. The extend clock pulse generator (EXCPG) generates a divided clock from the internal clock (I), the bus clock (B), or the external clock (UCLK). Because the clock sources, which can be a candidate to be used by EXCPG, vary from CPG setting or external clock source, user of SH7727 must adjust the divided clock, carefully to be 48 MHz. 11.2 11.2.1 Functions Block Diagram Figure 11.1 shows a block diagram of the EXCPG. USB clock (48 MHz) Peripheral clock (P) Select Internal clock (I) Bus clock (B) External clock (UCLK) 1/1 1/2 1/3 USB function USB host Figure 11.1 Block Diagram of EXCPG Rev. 5.00 Dec 12, 2005 page 279 of 1034 REJ09B0254-0500 Section 11 Extend Clock Pulse Generator for USB (EXCPG) 11.2.2 Pin Configuration Table 11.1 shows a pin configuration of the EXCPG. Table 11.1 Pin Configuration Pin Name External clock pin Abbreviation UCLK I/O Input Description USB clock input pin (48-MHz input) Note: UCLK is multiplexed with PTD6. 11.2.3 Register Configuration The EXCPG has the internal registers shown in table 11.2. Table 11.2 Register Configuration Name EXCPG control register Abbreviation EXCPGCR R/W W Initial Value H'00 Address H'A4000236 Access Size 8 11.3 11.3.1 Register Descriptions EXCPG Control Register (EXCPGCR) The EXCPG control register (EXCPGCR) selects the source clock and division ratio for generation of the EXCPG clock. EXCPGR is initialized to H'00 by a power-on reset. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0 USBCKS USBCKS USBCKS USBDIVS USBDIVS USBDIVS EL2 EL1 EL0 EL2 EL1 EL0 0 W 0 W 0 W 0 W 0 W 0 W Bits 7 and 6--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Dec 12, 2005 page 280 of 1034 REJ09B0254-0500 Section 11 Extend Clock Pulse Generator for USB (EXCPG) Bits 5 to 3--Clock Select (USBCKSEL2 to USBCKSEL0): Selects the clock source. Although initialized as peripheral clock (P) after power on reset, the value of USBCKSEL must be changed to adequate value to generate 48 MHz. To prevent malfunction, the USB Host and USB Function must be set in module standby state or module reset state when the value of USBCKSEL is changed. Bits 5 to 3 000 100 101 110 Another value Function (Clock Selection) Peripheral Clock (P) Internal Clock (I) Bus Clock (B) External clock (UCLK) Reserved (setting prohibited) (Initial value) Bits 2 to 0--Divider Select (USBDIVSEL2 to USBDIVSEL0): Selects the dividing ratio of clock source to generate USB clock so that the USB clock is 48 MHz. Bits 2 to 0 000 001 010 1** Function (Dividing Ratio Selection) 1/1 1/2 1/3 Internal clock (I), bus clock (B), external clock (UCLK) halted (Initial value) Note: To reduce power consumption, set USBDIVSEL2 to 1 and halts internal clock (I), bus clock (B), or external clock (UCLK) input. 11.4 Usage Notes By selecting LCLK (LCD clock)/UCLK (USB clock) as the function of the LCLK/UCLK/PTD[6] pin, it is possible to supply the clock input to the pin to both the LCD controller and the USB function controller. However, in this case it is necessary, using the divider select bit (USBDIVSEL[2:0]) in EXCPGCR (EXCPG control register), to set the USB clock so that the final clock frequency is 48 MHz. This means that the input clock frequency will be 48 MHz. If this frequency is not suitable as the operating clock for the LCD controller, consider selecting an internal clock for LCLK. In addition, it may be impossible to maintain the accuracy of the USB standard clock because the CPU clock (I) and bus clock (B) are generated by the internal PLL of the SH7727 by frequency multiplication. Therefore, it is recommended that a dedicated 48 MHz external clock be input to UCLK to ensure the accuracy of the USB standard clock. Rev. 5.00 Dec 12, 2005 page 281 of 1034 REJ09B0254-0500 Section 11 Extend Clock Pulse Generator for USB (EXCPG) Rev. 5.00 Dec 12, 2005 page 282 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Section 12 Bus State Controller (BSC) 12.1 Overview The bus state controller (BSC) divides physical address space and output control signals for various types of memory and bus interface specifications. BSC functions enable this LSI to link directly with synchronous DRAM, SRAM, ROM, and other memory storage devices without an external circuit. The BSC also allows direct connection to PCMCIA interfaces, simplifying system design and allowing high-speed data transfers in a compact system. 12.1.1 Features The BSC has the following features: * Physical address space is divided into six areas A maximum 64 Mbytes for each of the six areas, 0, 2 to 6 Area bus width can be selected by register (area 0 is set by external pin) Wait states can be inserted using the WAIT pin Wait state insertion can be controlled through software. Register settings can be used to specify the insertion of 1-10 cycles independently for each area (1-38 cycles for areas 5 and 6 and the PCMCIA interface only) The type of memory connected can be specified for each area, and Control signals are output for direct memory connection Wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas or writes directly following reads of the same area * Direct interface to synchronous DRAM (except if clock ratio I:B = 1:1) Multiplexes row/column addresses according to synchronous DRAM capacity Supports burst operation Has both auto-refresh and self-refresh functions Controls timing of synchronous DRAM direct-connection control signals according to register setting * Burst ROM interface Insertion of wait states controllable through software Register setting control of burst transfers * PCMCIA direct-connection interface* Insertion of wait states controllable through software Bus sizing function for I/O bus width (only in the little endian mode) Rev. 5.00 Dec 12, 2005 page 283 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) * Refresh function Refresh cycles will be automatically maintained in the sleep mode even after the external bus frequency is reduced to 1/4 of its normal operating frequency * The refresh counter can be used as an interval timer Outputs an interrupt request signal using the compare-matching function Outputs an interrupt request signal when the refresh counter overflows * Automatically disables the output of clock signals to anywhere but the refresh counter, except during execution of external bus cycles Note: * PCMCIA direct interface supported by the BSC is only signals and bus protocols shown in table 12.5. For details on other control signals, refer to section 30, PC Card Controller (PCC) (external circuit and this LSI on-chip card controller. In this BSI, both areas 5 and 6 has PCMICIA direct interface function common to the SH3 Series. The on-chip PC Card Controller supports only area 6. Rev. 5.00 Dec 12, 2005 page 284 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.1.2 Block Diagram Figure 12.1 shows the functional block diagram of the BSC. MD5 to MD3 Mode selection Bus interface WAIT Wait controller WCR1 WCR2 CS0 CS6 to CS2 CE2A to CE2B BS RD RD/WR WE3 to WE0 RAS CAS CKE ICIORD, ICIOWR IOIS16 Peripheral bus Area controller BCR1 BCR2 Module bus MCR Memory controller PCR MR2 RFCR RTCNT Refresh controller Comparator RTCOR RTCSR Interrupt controller BSC Legend: WCR: Wait state contol register BCR: Bus control register MCR: Memory control register PCR: PCMCIS control register RFCR: RTCNT: RTCOR: RTCSR: Refresh count register Refresh timer count register Refresh time constant register Refresh timer control/status register Figure 12.1 Corresponding to Logical Address Space and Physical Address Space Rev. 5.00 Dec 12, 2005 page 285 of 1034 REJ09B0254-0500 Internal bus Section 12 Bus State Controller (BSC) 12.1.3 Pin Configuration Table 12.1 lists the BSC pin configuration. Table 12.1 Pin Configuration Pin Name Address bus Data bus Bus cycle start Chip select 0, 2-4 Chip select 5, 6 Signal A25-A0 D15-D0 D31-D16 BS CS0, CS2-CS4 CS5/CE1A, CS6/CE1B I/O Output I/O I/O Output Output Output Description Address output Data I/O When 32-bit bus width, data I/O Shows start of bus cycle. During burst transfers, asserts every data cycle. Chip select signal to indicate area being accessed. Chip select signal to indicate area being accessed. CS5/CE1A and CS6/CE1B can also be used as CE1A and CE1B of PCMCIA. When PCMCIA is used, CE2A and CE2B Data bus direction indicator signal. PCMCIA write indicator signal. When synchronous DRAM is used in area 3, RAS3 for 64-Mbyte address. When synchronous DRAM is used, CAS signal is used for 64Mbyte address. When memory other than synchronous DRAM is used, selects D7 to D0 write strobe signal. When synchronous DRAM is used, selects D7 to D0. When memory other than synchronous DRAM and PCMCIA is used, selects D15 to D8 write strobe signal. When synchronous DRAM is used, selects D15 to D8. When PCMCIA is used, strobe signal that indicates the write cycle. When memory other than synchronous DRAM and PCMCIA is used, selects D23 to D16 write strobe signal. When synchronous DRAM is used, selects D23 to D16. When PCMCIA is used, strobe signal indicating I/O read. PCMCIA card select Read/write Row address strobe 3 Column address strobe Data enable 0 CE2A, CE2B RD/WR RAS3 CAS WE0/DQMLL Output Output Output Output Output Data enable 1 WE1/DQMLU/ WE Output Data enable 2 WE2/DQMUL/ ICIORD Output Rev. 5.00 Dec 12, 2005 page 286 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Pin Name Data enable 3 Signal WE3/DQMUU/ ICIOWR I/O Output Description When memory other than synchronous DRAM and PCMCIA is used, selects D31 to D24 write strobe signal. When synchronous DRAM is used, selects D31 to D24. When PCMCIA is used, strobe signal indicating I/O write. Strobe signal indicating read cycle Wait state request signal Clock enable control signal of synchronous DRAM Signal indicating PCMCIA 16-bit I/O. Valid only in little-endian mode. Bus release request signal Bus release acknowledge signal Specifies bus width and endian of area 0 Read Wait Clock enable IOIS16 Bus release request Bus release acknowledgment Mode selection RD WAIT CKE IOIS16 BREQ BACK MD5 to MD3 Output Input Output Input Input Output Input 12.1.4 Register Configuration The BSC has 11 registers (table 12.2). The synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states, and refreshes. Rev. 5.00 Dec 12, 2005 page 287 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.2 Register Configuration Name Bus control register 1 Bus control register 2 Wait state control register 1 Wait state control register 2 Individual memory control register PCMCIA control register Refresh timer control/status register Refresh timer counter Refresh time constant register Refresh count register Synchronous DRAM mode register For area 2 For area 3 Abbr. BCR1 BCR2 WCR1 WCR2 MCR PCR RTCSR RTCNT RTCOR RFCR SDMR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Initial Value* Address H'0000 H'3FF0 H'3FF3 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 -- H'FFFFFF60 H'FFFFFF62 H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6C H'FFFFFF6E H'FFFFFF70 H'FFFFFF72 H'FFFFFF74 H'FFFFD000- H'FFFFDFFF H'FFFFE000- H'FFFFEFFF Bus Width 16 16 16 16 16 16 16 16 16 16 8 Notes: For details, see section 12.2.7, Synchronous DRAM Mode Register (SDMR). * Initialized by power-on resets. 12.1.5 Area Overview Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32bit address spaces. The logical space is divided into five areas by the value of the upper bits of the address. The physical space is divided into eight areas. Logical space can be allocated at physical spaces using a memory management unit (MMU). For details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for physical spaces. As listed in table 12.3, this LSI can be connected directly to six areas of memory/PC card interface, and it outputs chip select signals (CS0, CS2 to CS6, CE2A, CE2B) for each of them. CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the corresponding bytes accessed. Rev. 5.00 Dec 12, 2005 page 288 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 P0, U0 Area 0 (CS0) Internal I/O Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) Area 5 (CS5) Area 6 (CS6) Reserved area H'00000000 H'04000000 H'08000000 H'0C000000 H'10000000 H'14000000 H'18000000 Physical address space Logical address space Note: For logical address spaces P0 and P3, when the memory management unit (MMU) is on, it can optionally generate a physical address for the logical address. It can be applied when the MMU is off and when the MMU is on and each physical address for the logical address is equal except for upper three bits. When translating logical addresses to arbitrary physical addresses, refer to table 12.3 "Physical Address Space Map". Figure 12.2 Corresponding to Logical Address Space and Physical Address Space Rev. 5.00 Dec 12, 2005 page 289 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.3 Physical Address Space Map Area 0 Connectable Memory 1 Ordinary memory* , burst ROM Physical Address (A28 to A0) H'00000000 to H'03FFFFFF H'00000000 + H'2000000 x n to H'03FFFFFF + H'2000000 x n Capacity 64 Mbytes Shadow 64 Mbytes Shadow 64 Mbyte Shadow 64 Mbytes Shadow 64 Mbytes Shadow 32 Mbytes 32 Mbytes Shadow 32 Mbytes 32 Mbytes Shadow Access Size 8, 16, 32* 2 (n = 1 to 6) 8, 16, 32* 3 1 Internal I/O registers* 7 H'04000000 to H'07FFFFFF H'04000000 + H'2000000 x n to H'07FFFFFF + H'2000000 x n (n = 1 to 6) 34 8, 16, 32* * 2 1 Ordinary memory* , Synchronous DRAM H'08000000 to H'0BFFFFFF H'08000000 + H'2000000 x n to H'0BFFFFFF + H'2000000 x n H'0C000000 to H'0FFFFFFF H'0C000000 + H'2000000 x n to H'0FFFFFFF + H'2000000 x n H'10000000 to H'13FFFFFF H'10000000 + H'2000000 x n to H'13FFFFFF + H'2000000 x n (n = 1 to 6) 34 8, 16, 32* * 3 Ordinary memory, Synchronous DRAM Ordinary memory (n = 1 to 6) 8, 16, 32* 3 4 (n = 1 to 6) 35 8, 16, 32* * 5 Ordinary memory, PCMCIA, burst ROM H'14000000 to H'15FFFFFF H'16000000 to H'17FFFFFF H'16000000 + H'2000000 x n to H'17FFFFFF + H'2000000 x n (n = 1 to 6) 35 8, 16, 32* * 6 Ordinary memory, PCMCIA, bust ROM H'18000000 to H'19FFFFFF H'1A000000 to H'1BFFFFFF H'1A000000 + H'2000000 x n to H'1BFFFFFF + H'2000000 x n (n = 1 to 6) n = 0-7 7* 6 Reserved area H'1C000000 + H'20000000 x n to H'1FFFFFFF + H'20000000 x n Notes: 1. 2. 3. 4. 5. 6. 7. Memory with interface such as SRAM or ROM. Use external pin to specify memory bus width. Use register to specify memory bus width. With synchronous DRAM interfaces, bus width must be 16 or 32 bits. With PCMCIA interface, bus width must be 8 or 16 bits. The access to reserved area is prohibited. When the control register in area 1 is not used for address translation by the MMU, set the top three bits of the logical address to 101 to allocate in the P2 space. Rev. 5.00 Dec 12, 2005 page 290 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Area 0: H'00000000 Area 1: H'04000000 Area 2: H'08000000 Area 3: H'0C000000 Area 4: H'10000000 Ordinary memory/ burst ROM Internal I/O Ordinary memory/ synchronous DRAM Ordinary memory/ synchronous DRAM Ordinary memory Area 5: H'14000000 Area 6: H'18000000 Ordinary memory/ burst ROM/PCMCIA Ordinary memory/ burst ROM/PCMCIA The PCMCIA interface is shared by the memory and I/O card The PCMCIA interface is shared by the memory and I/O card Figure 12.3 Physical Space Allocation Memory Bus Width: The memory bus width in this LSI can be set for each area. In area 0, an external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset as setting of MD4 and MD3 as below table . Table 12.4 Correspondence between External Pins (MD4 and MD3) and Memory bus width in area0 MD4 0 1 MD3 0 1 0 1 Memory Size Reserved (Setting prohibited) 8 bits 16 bits 32 bits For areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used. When the PCMCIA interface is used, set the bus width to byte or word. When synchronous DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When using the port function, set each of the bus widths to byte or word for all areas. For more information, see section 12.2.2, Bus Control Register 2 (BCR2). Rev. 5.00 Dec 12, 2005 page 291 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space obtained by adding to it H'20000000 x n (n = 1 to 6). The address range for area 7, which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 + H'20000000 x n to H'1FFFFFFF + H'20000000 x n (n = 0 to 7) corresponding to the area 7 shadow space is reserved, so do not use it. 12.1.6 PC Card Support The Bus Controller of this LSI supports protocol signals of PCMCIA standard interface specifications in physical space areas 5 and 6 as another SH3 Series. PC Card Bus signal (CEIA,CE2A,CE1B,CE2B,IOIS16) are supported for PC Card Bus Protocol as same as SH7708/SH7709/SH7729 series. Dynamic bus sizing of I/O bus width is supported only in the little endian made. Table 12.5 SH7727 and PCMCIA Pins SH7727 CE1A CE1B CE2A CE2B WE RD IOIS16 ICIORD ICIOWR A25-A0 D15-D0 PCMCIA CE1 CE1 CE2 CE2 WE/PGM OE WP/IOIS16 IORD IOWR A25-A0 D15-D0 Rev. 5.00 Dec 12, 2005 page 292 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2 12.2.1 BSC Registers Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle state for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by standby mode. Do not access external memory outside area 0 until BCR1 register initialization is complete. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PULA PULD Initial value: R/W: 0 R/W 0 R/W HIZ HIZ ENDI A0 A0 A5 A5 A6 A6 DRAM DRAM DRAM A5 A6 MEM CNT AN BST1 BST0 BST1 BST0 BST1 BST0 TP2 TP1 TP0 PCM PCM 0 R/W 0 R/W 0/1* R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * Samples the value of the external pin (MD5) designating endian at power-on reset. Bit 15--Pins A25 to A0 Pull-Up (PULA): Specifies whether or not pins A25 to A0 are pulled up for 4 cycles immediately after BACK is asserted. Bit 15: PULA 0 1 Description Not pulled up Pulled up (Initial value) Bit 14--Pins D31 to D0 Pull-Up (PULD): Specifies whether or not pins D31 to D0 are pulled up when not in use. Bit 14: PULD 0 1 Description Not pulled up (Initial value) Pulled up Bit 13--Hi-Z memory control (HIZMEM): Specifies the state of A25 to A0, BS, CS, RD/WR, WE/DQM, RD, CE2A, CE2B and DRAK0 in standby mode. Bit 13: HIZMEM 0 1 Description High-impedance state in standby mode. High in standby mode. (Initial value) Rev. 5.00 Dec 12, 2005 page 293 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bit 12--High-Z Control (HIZCNT): Specifies the state of the RAS and the CAS signals at standby and bus right release. Bit 12: HIZCNT 0 1 Description The RAS and the CAS signals are high-impedance state (High-Z) at standby and bus right release. (Initial value) The RAS and the CAS signals are driven at standby and bus right release. Bit 11--Endian Flag (ENDIAN): Samples the value of the external pin designating endian upon a power-on reset. Endian for all physical spaces is decided by this bit, which is read-only. Bit 11: ENDIAN 0 1 Description (On reset) Endian setting external pin (MD5) is low. Indicates this LSI is set as big endian. (On reset) Endian setting external pin (MD5) is high. Indicates this LSI is set as little endian. Bits 10 and 9--Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst ROM in physical space area 0. When burst ROM is used, set the number of burst transfers. Bit 10: A0BST1 0 Bit 9: A0BST0 0 1 1 0 1 Description Access area 0 as ordinary memory (Initial value) Access area 0 as burst ROM (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Access area 0 as burst ROM (8 consecutive accesses). Can be used when bus width is 8 or 16. Access area 0 as burst ROM (16 consecutive accesses). Can be used only when bus width is 8. Rev. 5.00 Dec 12, 2005 page 294 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 8 and 7--Area 5 Burst Enable (A5BST1, A5BST0): Specify whether to use burst ROM and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode are used, set the number of burst transfers. Bit 8: A5BST1 0 Bit 7: A5BST0 0 1 1 0 1 Description Access area 5 as ordinary memory (Initial value) Burst access of area 5 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 5 (8 consecutive accesses). Can be used when bus width is 8 or 16. Burst access of area 5 (16 consecutive accesses). Can be used only when bus width is 8. Bits 6 and 5--Area 6 Burst Enable (A6BST1, A6BST0): Specify whether to use burst ROM and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode are used, set the number of burst transfers. Bit 6: A6BST1 0 Bit 5: A6BST0 0 1 1 0 1 Description Access area 6 as ordinary memory (Initial value) Burst access of area 6 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 6 (8 consecutive accesses). Can be used when bus width is 8 or 16. Burst access of area 6 (16 consecutive accesses). Can be used only when bus width is 8. Rev. 5.00 Dec 12, 2005 page 295 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 4 to 2--Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Designate the types of memory connected to physical space areas 2 and 3. Ordinary memory, such as ROM, SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly connected. Bit 4: DRAMTP2 0 Bit 3: DRAMTP1 0 Bit 2: DRAMTP0 0 1 1 0 1 1 0 1 0 1 0 1 Description Areas 2 and 3 are ordinary memory (Initial value) Reserved (Setting disabled) Area 2: ordinary memory; 1 Area 3: synchronous DRAM* Areas 2 and 3 are synchronous 12 DRAM* * Reserved (Setting disabled) Reserved (Setting disabled) Reserved (Setting disabled) Reserved (Setting disabled) Notes: 1. When selecting this mode, set the same bus width for area 2 and area 3. 2. If clock rate is specified as 1 : Bus clock = 1:1 , synchronous DRAM cannot be accessed. Bit 1--Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as PCMCIA space. Bit 1: A5PCM 0 1 Description Access physical space area 5 as ordinary memory Access physical space area 5 as PCMCIA space (Initial value) Bit 0--Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as PCMCIA space. Bit 0: A6PCM 0 1 Description Access physical space area 6 as ordinary memory Access physical space area 6 as PCMCIA space (Initial value) Rev. 5.00 Dec 12, 2005 page 296 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2.2 Bus Control Register 2 (BCR2) The bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus-size width of each area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or by standby mode. Do not access external memory outside area 0 until BCR2 register initialization is complete. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 A6 SZ1 1 R/W 12 A6 SZ0 1 R/W 11 A5 SZ1 1 R/W 10 A5 SZ0 1 R/W 9 A4 SZ1 1 R/W 8 A4 SZ0 1 R/W 7 A3 SZ1 1 R/W 6 A3 SZ0 1 R/W 5 A2 SZ1 1 R/W 4 A2 SZ0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R Bits 15, 14, 3, 2, 1, and 0--Reserved: These bits are always read as 0. The write value should always be 0. Bits 2n + 1, 2n--Area n (2 to 6) Bus Size Specification (AnSZ1, AnSZ0): Specify the bus sizes of physical space area n (n = 2 to 6). Bit 2n + 1: AnSZ1 0 1 0 1 Bit 2n: AnSZ0 0 1 0 1 0 1 0 1 Used Port A / B Unused Description Reserved (Setting disabled) Byte (8-bit) size Word (16-bit) size Longword (32-bit) size Reserved (Setting disabled) Byte (8-bit) size Word (16-bit) size Reserved (Setting disabled) Rev. 5.00 Dec 12, 2005 page 297 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2.3 Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. This can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. This LSI automatically inserts idle states equal to the number set in WCR1 in those cases. WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by standby mode. Bit: 15 WAIT SEL Initial value: R/W: 0 R/W 14 -- 0 R 13 A6 IW1 1 R/W 12 A6 IW0 1 R/W 11 A5 IW1 1 R/W 10 A5 IW0 1 R/W 9 A4 IW1 1 R/W 8 A4 IW0 1 R/W 7 A3 IW1 1 R/W 6 A3 IW0 1 R/W 5 A2 IW1 1 R/W 4 A2 IW0 1 R/W 3 -- 0 R 2 -- 0 R 1 A0 IW1 1 R/W 0 A0 IW0 1 R/W Bit 15--WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling timing. Bit 15: WAITSEL 0 1 Description Set to 1 when WAIT signal is used.* Sampled at the falling edge of CKIO. (Initial value) Note: * If low level is input to the WAIT by setting the WAITSEL bit, the LSI operation cannot be guaranteed. Bits 14, 3, and 2 --Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Dec 12, 2005 page 298 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 2n + 1, 2n--Area n (6 to 2, 0) Intercycle Idle Specification (AnIW1, AnIW0): Specify the number of idles inserted between bus cycles when switching between physical space area n (6 to 2, 0) to another space or between a read access to a write access in the same physical space. Bit 2n + 1: AnIW1 0 1 Bit 2n: AnIW0 0 1 0 1 Description 1 idle cycle inserted 1 idle cycle inserted 2 idle cycles inserted 3 idle cycles inserted (Initial value) 12.2.4 Wait State Control Register 2 (WCR2) Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory accesses. This allows direct connection of even low-speed memories without an external circuit. WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by standby mode. Bit: 15 A6 W2 Initial value: R/W: 1 R/W 14 A6 W1 1 R/W 13 A6 W0 1 R/W 12 A5 W2 1 R/W 11 A5 W1 1 R/W 10 A5 W0 1 R/W 9 A4 W2 1 R/W 8 A4 W1 1 R/W 7 A4 W0 1 R/W 6 A3 W1 1 R/W 5 A3 W0 1 R/W 4 A2 W1 1 R/W 3 A2 W0 1 R/W 2 A0 W2 1 R/W 1 A0 W1 1 R/W 0 A0 W0 1 R/W Rev. 5.00 Dec 12, 2005 page 299 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 15 to 13--Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states inserted into physical space area 6. Also specify the burst pitch for burst transfer. Description First Cycle Bit 15: Bit 14: A6W2 A6W1 0 0 1 1 0 1 Bit 13: A6W0 0 1 0 1 0 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 10 (Initial value) WAIT Pin Disable Enable Enable Enable Enable Enable Enable Enable Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enable Enable Enable Enable Enable Enable Enable Enable Bits 12 to 10--Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states inserted into physical space area 5. Also specify the burst pitch for burst transfer. Description First Cycle Bit 12: A5W2 0 Bit 11: A5W1 0 1 1 0 1 Bit 10: A5W0 0 1 0 1 0 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 10 (Initial value) WAIT Pin Disable Enable Enable Enable Enable Enable Enable Enable Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enable Enable Enable Enable Enable Enable Enable Enable Rev. 5.00 Dec 12, 2005 page 300 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 9 to 7--Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states inserted into physical space area 4. Description Bit 9: A4W2 0 Bit 8: A4W1 0 1 1 0 1 Bit 7: A4W0 0 1 0 1 0 1 0 1 Inserted Wait State 0 1 2 3 4 6 8 10 WAIT Pin Ignored Enable Enable Enable Enable Enable Enable Enable (Initial value) Bits 6 and 5--Area 3 Wait Control (A3W1, A3W0): Specify the number of wait states inserted into physical space area 3. * For Ordinary memory Description Bit 6: A3W1 0 1 Bit 5: A3W0 0 1 0 1 Inserted Wait States 0 1 2 3 WAIT Pin Ignored Enable Enable Enable (Initial value) * For Synchronous SDRAM Description Bit 6: A3W1 0 1 Bit 5: A3W0 0 1 0 1 Synchronous SDRAM: CAS Latency 1 1 2 3 (Initial value) Rev. 5.00 Dec 12, 2005 page 301 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 4 and 3--Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted into physical space area 2. * For Ordinary memory Description Bit 4: A2W0 0 1 Bit 3: A2W0 0 1 0 1 Inserted Wait States 0 1 2 3 WAIT Pin Ignored Enable Enable Enable (Initial value) * For Synchronous SDRAM Description Bit 4: A2W1 0 1 Bit 3: A2W0 0 1 0 1 Synchronous DRAM: CAS Latency 1 1 2 3 (Initial value) Bits 2 to 0--Area 0 Wait Control (A0W2, A0W1, A0W0): Specify the number of wait states inserted into physical space area 0. Also specify the burst pitch for burst transfer. Description First Cycle Bit 2: A0W2 0 Bit 1: A0W1 0 1 1 0 1 Bit 0: A0W0 0 1 0 1 0 1 0 1 Inserted Wait States 0 1 2 3 4 6 8 10 (Initial value) WAIT Pin Ignored Enable Enable Enable Enable Enable Enable Enable Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enable Enable Enable Enable Enable Enable Enable Enable Rev. 5.00 Dec 12, 2005 page 302 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2.5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without external circuits. The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or standby mode. The bits TPC1 to TPC0, RCD1 to RCD0, TRWL1 to TRWL0, TRAS1 to TRAS0, AMX3 to AMX0, and are written to at the initialization after a power-on reset and are not then modified again. When RFSH and RMODE are written to, write the same values to the other bits. When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized. Bit: 15 14 13 12 11 10 9 8 7 -- 0 R/W 6 5 4 3 2 1 0 -- 0 R/W TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS 1 0 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W AMX3 AMX2 AMX1 AMX0 RFSH RMO DE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 and 14--RAS Precharge Time (TPC1, TPC0): These bits set the minimum number of cycles until output of the next bank-active command after precharge, when the synchronous DRAM interface is selected for external memory. However, the number of cycles inserted immediately after the precharge all banks (PALL) command is issued when performing autorefresh is one fewer than the number of cycles during normal operation. Description Bit 15: TPC1 0 1 Bit 14: TPC0 0 1 0 1 Normal Operation 1 cycle 2 cycles 3 cycles 4 cycles (Initial value) Immediately After Precharge Command* 0 cycle 1 cycle 2 cycles 3 cycles (Initial value) Immediately After Self-refresh 2 cycles 5 cycles 8 cycles 11 cycles (Initial value) Note: * Immediately after the precharge all banks (PALL) command is issued when performing auto-refresh. Rev. 5.00 Dec 12, 2005 page 303 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 13 and 12--RAS-CAS Delay (RCD1, RCD0): When synchronous DRAM interface is selected, sets the bank active read/write command delay time. Bit 13: RCD1 0 1 Bit 12: RCD0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles 4 cycles (Initial value) Bits 11 and 10--Write-Precharge Delay (TRWL1, TRWL0): The TRWL bits set the synchronous DRAM write-precharge delay time. This designates the time between the end of a write cycle and the next bank-active command. This is valid only when synchronous DRAM is connected. After the write cycle, the next bank-active command is not issued for the period TPC + TRWL. Bit 11: TRWL1 0 1 Bit 10: TRWL0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles Reserved (Setting disabled) (Initial value) Bits 9 and 8--CAS CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): When CAS RAS synchronous DRAM interface is selected, no bank-active command is issues during the period TPC + TRAS after an auto-refresh command. Bit 9: TRAS1 0 1 Bit 8: TRAS0 0 1 0 1 Description 2 cycles 3 cycles 4 cycles 5 cycles (Initial value) Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Bits 6 to 3--Address Multiplex (AMX3 , AMX2, AMX1, AMX0): The AMX bits specify address multiplexing for synchronous DRAM. The actual address shift value differs between synchronous DRAM interface. Rev. 5.00 Dec 12, 2005 page 304 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) For Synchronous DRAM Interface: (see table 12.12) Bit6: AMX3 1 Bit5: AMX2 1 Bit 4: AMX1 0 Bit 3: AMX0 1 Description The row address begins with A10 when bus width is 16 bit. The row address begins with A11 when bus width is 32 bit. (The A10 value is output at A1 when the row address is output. 4M x 16-bit x 4-bank products) 1 0 The row address begins with A11 when bus width is 16 bit. (The A11 value is output at A1 when the row address is 1 output. 8M x 16-bit x 4-bank products)* 0 1 0 0 The row address begins with A9 when bus width is 16 bit. The row address begins with A10 when bus width is 32 bit. (The A9 value is output at A1 when the row address is output. 1M x 16-bit x 4-bank products) 1 The row address begins with A10 when bus width is 16 bit. The row address begins with A11 when bus width is 32 bit. (The A10 value is output at A1 when the row address is output. 2M x 16-bit x 4-bank products) 1 0 The row address begins with A11 when bus width is 32 bit.* (The A11 value is output at A1 when the row address is output. 2M x 16-bit x 4-bank products) 1 The row address begins with A9 when bus width is 16 bit. The row address begins with A10 when bus width is 32 bit. (The A9 value is output at A1 when the row address is output. 512K x 32-bit x 4-bank products) 0 0 0 Reserved. AMX3 to AMX0 must be set to *1*** before accessing synchronous DRAM memory. (Initial value) Reserved (illegal setting) 2 Values other than above Notes: 1. Can only be set when using a 16-bit bus width. 2. Can only be set when using a 32-bit bus width. Rev. 5.00 Dec 12, 2005 page 305 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bit 2--Refresh Control (RFSH): The RFSH bit determines whether or not the refresh operation of the synchronous DRAM is performed. The timer for generation of the refresh request frequency can also be used as an interval timer. Bit 2: RFSH 0 1 Description No refresh Refresh (Initial value) Bit 1--Refresh Mode (RMODE): The RMODE bit selects whether to perform an ordinary refresh or a self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, a CASbefore-RAS refresh or an auto-refresh is performed on synchronous DRAM at the period set by the refresh-related registers RTCNT, RTCOR and RTCSR. When a refresh request occurs during an external bus cycle, the bus cycle will be ended and the refresh cycle performed. When the RFSH bit is 1 and this bit is also 1, the synchronous DRAM will wait for the end of any executing external bus cycle before going into a self-refresh. All refresh requests to memory that is in the self-refresh state are ignored. Bit 1: RMODE 0 1 Description CAS-before-RAS refresh (RFSH must be 1) Self-refresh (RFSH must be 1) (Initial value) Bit 0--Reserved: This bit is always read as 0. The write value should always be 0. 12.2.6 PCMCIA Control Register (PCR) The PCMCIA control register (RCR) specifies the assert/negate timing of the OE and WE signals (RD and WE1 pins of this LSI) for the PCMCIA interface connected to areas 5 and 6. Note that the assertion widths of OE and WE are set using the wait control bits of the WCR2 register. The PCR register is a 16-bit read/write register. It is initialized at a power-on reset to H'0000. However, the register is not initialized and the contents remain unchanged at a manual reset and when in standby mode. Bit: 15 A6 W3 Initial value: R/W: 0 R/W 14 A5 W3 0 R/W 13 -- 0 R/W 12 -- 0 R/W 11 10 9 8 7 6 5 4 3 2 1 0 A5 A6 A5 A6 A5 A5 A6 A6 A5 A5 A6 A6 TED2 TED2 TEH2 TEH2 TED1 TED0 TED1 TED0 TEH1 TEH0 TEH1 TEH0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 5.00 Dec 12, 2005 page 306 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bit 15--Area 6 Wait Control (A6W3): The A6W3 bit specifies the number of inserted wait states for area 6 combined with bits A6W2 to A6W0 in WCR2. It also specifies the number of transfer states in burst transfer. Set this bit to 0 when area 6 is not set to PCMCIA. Top Cycle Burst Cycle Number of States per One-data Transfer 2 2 3 4 5 7 9 11 13 15 19 23 27 31 35 39 A6W3 0 A6W2 0 A6W1 0 1 A6W0 0 1 0 1 0 1 0 1 Inserted Wait State 0 1 2 3 4 6 8 10 (Initial value) 12 14 18 22 26 30 34 38 WAIT Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled WAIT Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 Bit 14--Area 5 Wait Control (A5W3): The A5W3 bit specifies the number of inserted wait states for area 5 combined with bits A5W2 to A5W0 in WCR2. It also specifies the number of transfer states in burst transfer. Set this bit to 0 when area 5 is not set to PCMCIA. The relationship between the setting value and the number of waits is the same as A6W3. Bits 13 and 12--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Dec 12, 2005 page 307 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 11, 7, and 6--Area 5 Address OE WE Assert Delay (A5TED2, A5TED1, and A5TED0): OE/WE The A5TED bits specify the address to OE/WE assert delay time for the PCMCIA interface connected to area 5. Bit 11: A5TED2 0 Bit 7: A5TED1 0 1 1 0 1 Bit 6: A5TED0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Bits 10, 5 and 4--Area 6 Address OE WE Assert Delay (A6TED2, A6TED1, and A6TED0): OE/WE The A6TED bits specify the address to OE/WE assert delay time for the PCMCIA interface connected to area 6. Bit 10: A6TED2 0 Bit 5: A6TED1 0 1 1 0 1 Bit 4: A6TED0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Rev. 5.00 Dec 12, 2005 page 308 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 9, 3, and 2--Area 5 OE WE Negate Address Delay(A5TEH2, A5TEH1, and A5TEH0): OE/WE The A5TEH bits specify the OE/WE negate address delay time for the PCMCIA interface connected area 5. Bit 9: A5TEH2 0 Bit 3: A5TEH1 0 1 1 0 1 Bit 2: A5TEH0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Bits 8, 1, and 0--Area6 OE WE Negate Address Delay (A6TEH2, A6TEH1, and A6TEH0): OE/WE The A6TEH bits specify the OE/WE negate address delay time for the PCMCIA interface connected to area 6. Bit 8: A6TEH2 0 Bit 1: A6TEH1 0 1 1 0 1 Bit 0: A6TEH0 0 1 0 1 0 1 0 1 Description 0.5-cycle delay 1.5-cycle delay 2.5-cycle delay 3.5-cycle delay 4.5-cycle delay 5.5-cycle delay 6.5-cycle delay 7.5-cycle delay (Initial value) Rev. 5.00 Dec 12, 2005 page 309 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2.7 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address bus and is an 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3. SDMR is undefined after a power-on reset. The register contents are not initialized by a manual reset or standby mode; values remain unchanged. Bit: 31 ...................... SDMR address Initial value: R/W: -- -- ...................... ...................... -- -- 12 11 -- -- W* 10 -- -- W* 9 -- -- W 8 -- -- W 7 -- -- W 6 -- -- W 5 -- -- W 4 -- -- W 3 -- -- W 2 -- -- W 1 -- -- -- 0 -- -- -- Note: * Depending on the type of synchronous DRAM. Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If the value to be set is X and the SDMR address is Y, the value X is written in the synchronous DRAM mode register by writing in address X + Y. Since, with a 32-bit bus width, A0 of the synchronous DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is connected to A3 of the chip, the value actually written to the synchronous DRAM is the X value shifted two bits right. With a 16-bit bus width, the value written is the X value shifted one bit right. For example, with a 32-bit bus width, when H'0230 is written to the SDMR register of area 2, random data is written to the address H'FFFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is written to the SDMR register. The range for value X is H'0000 to H'0FFC. When H'0230 is written to the SDMR register of area 3, random data is written to the address H'FFFFE000 (address Y) + H'08C0 (value X), or H'FFFFE8C0. As a result, H'0230 is written to the SDMR register. The range for value X is H'0000 to H'0FFC. Rev. 5.00 Dec 12, 2005 page 310 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2.8 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit read/write register that specifies the refresh cycle, whether to generate an interrupt, and that interrupt's cycle. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or standby mode. Before specifying the CKS2 to CKS0 of RTCST, the RTCOR must be specified. Note: Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not rewritten incorrectly. Use the word-transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions on Accessing Refresh Control Related Registers. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. Bit 7--Compare Match Flag (CMF): The CMF status flag indicates that the values of RTCNT and RTCOR match. Bit 7: CMF 0 Description The values of RTCNT and RTCOR do not match. Clear condition: When a refresh is performed After 0 has been written in CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh). (Initial value) The values of RTCNT and RTCOR match. Set condition: RTCNT = RTCOR* 1 Note: * Contents do not change when 1 is written to CMF. Bit 6--Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused when the CMF of RTCSR is set to 1. Do not set this bit to 1 when using CAS-before-RAS refresh or auto-refresh. Bit 6: CMIE 0 1 Description Disables an interrupt request caused by CMF Enables an interrupt request caused by CMF (Initial value) Rev. 5.00 Dec 12, 2005 page 311 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bits 5 to 3--Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source clock is the external bus clock (BCLK). The RTCNT count clock is CKIO divided by the specified ratio. The specified ratios are shown below in the normal external bus clock. Before specifying the CKS2 to CKS0 of RTCST, the RTCOR must be specified. Description Bit 5: CKS2 0 Bit 4: CKS1 0 1 1 0 1 Bit 3: CKS0 0 1 0 1 0 1 0 1 Normal external bus clock Disables clock input Bus clock (CKIO)/4 CKIO/16 CKIO/64 CKIO/256 CKIO/1024 CKIO/2048 CKIO/4096 (Initial value) Bit 2--Refresh Count Overflow Flag (OVF): The OVF status flag indicates when the number of refresh requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit of RTCSR. Bit 2: OVF 0 1 Description RFCR has not exceeded the count limit value set in LMTS Clear Conditions: When 0 is written to OVF (Initial value) RFCR has exceeded the count limit value set in LMTS Set Conditions: When the RFCR value has exceeded the count limit value set in LMTS* Note: * Contents don't change when 1 is written to OVF. Bit 1--Refresh Count Overflow Interrupt Enable (OVIE): OVIE selects whether to suppress generation of interrupt requests by OVF when the OVF bit of RTCSR is set to 1. Bit 1: OVIE 0 1 Description Disables interrupt requests from the OVF Enables interrupt requests from the OVF (Initial value) Rev. 5.00 Dec 12, 2005 page 312 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Bit 0--Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (RFCR). When the value RFCR overflows the value specified by LMTS, the OVF flag is set. Bit 0: LMTS 0 1 Description Count limit value is 1024 Count limit value is 512 (Initial value) 12.2.9 Refresh Timer Counter (RTCNT) RTCNT is a 16-bit read/write register. RTCNT is an 8-bit counter that counts up with input clocks. The clock select bits (CKS2 to CKS0) of RTCSR select the input clock. When RTCNT matches RTCOR, the CMF bit of TCSR is set and RTCNT is cleared. RTCNT is initialized to H'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized by standby mode and holds its values unchanged. Note: Writing to the RTCNT differs from that to general registers to ensure the RTCNT is not rewritten incorrectly. Use the word-transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions on Accessing Refresh Control Related Registers. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 5.00 Dec 12, 2005 page 313 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2.10 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a 16-bit read/write register. The values of RTCOR and RTCNT (bottom 8 bits) are constantly compared. When the values match, the compare match flag (CMF) of RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) of the individual memory control register (MCR) is set to 1 and the refresh mode is set to CAS-beforeRAS refresh, a memory refresh cycle occurs when the CMF bit is set. RTCOR is initialized to H'00 by a power-on reset. It is not initialized by a manual reset or standby mode, but holds its contents. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR. Note: Writing to the RTCOR differs from that to general registers to ensure the RTCOR is not rewritten incorrectly. Use the word-transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions on Accessing Refresh Control Related Registers. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 12.2.11 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 16-bit read/write register. It is a 10-bit counter that increments every time RTCOR and RTCNT match. When RFCR exceeds the count limit value set in the LMTS of RTCSR, RTCSR's OVF bit is set and RFCR clears. RFCR is initialized to H'0000 when a power-on reset is performed. It is not initialized by a manual reset or standby mode, but holds its contents. Note: Writing to the RFCR differs from that to general registers to ensure the RFCR is not rewritten incorrectly. Use the word-transfer instruction to set the MSB and followed six bits of upper bytes as B'101001 and remaining bits as the write data. For details, see section 12.2.12, Cautions on Accessing Refresh Control Related Registers. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 5.00 Dec 12, 2005 page 314 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.2.12 Cautions on Accessing Refresh Control Related Registers RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 12.4). Perform reads and writes using the following methods: 1. Writing to RFCR, RTCSR, RTCNT, and RTCOR When writing to RFCR, RTCSR, RTCNT, and RTCOR, use only word transfer instructions. You cannot write with byte transfer instructions. When writing to RTCNT, RTCSR, or RTCOR, place B'10100101 in the upper byte and the write data in the lower byte. When writing to RFCR, place B'101001 in the top 6 bits and the write data in the remaining bits, as shown in figure 12.4. 2. Reading from RFCR, RTCSR, RTCNT, and RTCOR When reading from RFCR, RTCSR, RTCNT, and RTCOR, carry out reads with 16-bit width. 0 is read out from undefined bit sections. 15 RTCSR, RTCNT, RTCOR RFCR 1 15 1 0 1 0 0 0 1 0 0 1 0 8 1 7 Write data 0 Write data 0 10 9 1 Figure 12.4 Writing to RFCR, RTCSR, RTCNT, and RTCOR Rev. 5.00 Dec 12, 2005 page 315 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.3 12.3.1 BSC Operation Endian/Access Size and Data Alignment This LSI supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. This switchover is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-on reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high. Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus widths (word and long word) for synchronous DRAM. For the PCMCIA interface, choose from byte and word. This means data alignment is done by matching the device's data width and endian. The access unit must also be matched to the device's bus width. This also means that when longword data is read from a byte-width device, the read operation must happen 4 times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit. Table 12.6 32-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D24 Data 7 to 0 -- -- -- D23 to D16 -- Data 7 to 0 -- -- Data 7 to 0 -- Data 23 to 16 D15 to D8 -- -- Data 7 to 0 -- -- Data 15 to 8 Data 15 to 8 D7 to D0 -- -- -- Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert WE3, WE3 DQMUU Assert Assert Assert Assert Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU WE0, WE0 DQMLL Word access Data at 0 15 to 8 Word access -- at 2 Longword access at 0 Data 31 to 24 Rev. 5.00 Dec 12, 2005 page 316 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.7 16-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 D31 to D23 to D15 to D24 D16 D8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 -- Data 7 to 0 -- Data 15 to 8 Data 15 to 8 D7 to D0 -- Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert WE3, WE3 DQMUU Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU Assert WE0, WE0 DQMLL -- Assert -- Assert Assert Assert Assert Assert Longword 1st -- access time at 0 at 0 2nd -- time at 2 Data Data 31 to 24 23 to 16 Data 15 to 8 Data 7 to 0 Rev. 5.00 Dec 12, 2005 page 317 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.8 8-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D23 to D15 to D7 to D24 D16 D8 D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Strobe Signals WE3, WE2, WE3 WE2 DQMUU DQMUL WE1, WE0, WE1 WE0 DQMLU DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Word 1st time -- access at 0 at 0 2nd time -- at 1 Word 1st time -- access at 2 at 2 2nd time -- at 3 Longword 1st time -- access at 0 at 0 2nd time -- at 1 3rd time -- at 2 4th time -- at 3 Rev. 5.00 Dec 12, 2005 page 318 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.9 32-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D24 -- -- -- Data 7 to 0 D23 to D16 -- -- Data 7 to 0 -- -- Data 7 to 0 Data 23 to 16 D15 to D8 -- Data 7 to 0 -- -- Data 15 to 8 -- Data 15 to 8 D7 to D0 Data 7 to 0 -- -- -- Data 7 to 0 -- Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert WE3, WE3 DQMUU Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU WE0, WE0 DQMLL Assert Word access -- at 0 Word access Data at 2 15 to 8 Longword access at 0 Data 31 to 24 Rev. 5.00 Dec 12, 2005 page 319 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.10 16-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 D31 to D23 to D15 to D24 D16 D8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 -- Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 15 to 8 D7 to D0 Data 7 to 0 -- Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert WE3, WE3 DQMUU Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU WE0, WE0 DQMLL Assert Longword 1st -- access at time at 0 0 2nd -- time at 2 Data Data 31 to 24 23 to 16 Rev. 5.00 Dec 12, 2005 page 320 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D23 to D15 to D7 to D24 D16 D8 D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24 Strobe Signals WE3, WE2, WE1, WE0, WE3 WE2 WE1 WE0 DQMUU DQMUL DQMLU DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Word 1st time -- access at 0 at 0 2nd time -- at 1 Word 1st time -- access at 2 at 2 2nd time -- at 3 Longword 1st time -- access at 0 at 0 2nd time -- at 1 3rd time -- at 2 4th time -- at 3 Rev. 5.00 Dec 12, 2005 page 321 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.3.2 Description of Areas Area 0: Area 0 physical addresses A28 to A26 are 0'0. Addresses A31 to A29 are ignored and the address range is H'00000000 + H'20000000 x n - H'03FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using external pins MD3 and MD4. When the area 0 space is accessed, a CS0 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A0W2 to A0W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 10 according to the number of waits. Area 1: Area 1 physical addresses A28 to A26 are 001. Addresses A31 to A29 are ignored and the address range is H'04000000 + H'20000000 x n - H'07FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Area 1 is the area specifically for the internal peripheral modules. The external memories cannot be connected. Control registers of peripheral modules shown below are mapped to this area 1. Their addresses are physical address, to which logical addresses can be mapped with the MMU enabled: DMAC, PORT, SCIF, ADC, DAC, LCDC, PCC, SIOF, AFEIF, USBF, USBH, INTC (except INTEVT, IPRA, IPRB) Those registers must be set not to be cached. Area 2: Area 2 physical addresses A28 to A26 are 010. Addresses A31 to A29 are ignored and the address range is H'08000000 + H'20000000 x n - H'0BFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to this space. Byte, word, or longword can be selected as the bus width using the A2SZ1 to A2SZ0 bits of BCR2 for ordinary memory. When the area 2 space is accessed, a CS2 signal is asserted. When ordinary memories are connected, an RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the A2W1 to A2W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT) only when the ordinary memories are connected. Rev. 5.00 Dec 12, 2005 page 322 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) When synchronous DRAM is connected, the RAS3 signal, CAS signal, RD/WR signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of RAS3, CAS, data timing, and address multiplexing is set with MCR. Area 3: Area 3 physical addresses A28 to A26 are 011. Addresses A31 to A29 are ignored and the address range is H'0C000000 + H'20000000 x n to H'0FFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to this space. Byte, word or longword can be selected as the bus width using the A3SZ1 to A3SZ0 bits of BCR2 for ordinary memory. When area 3 space is accessed, CS3 is asserted. When ordinary memories are connected, an RD signal that can be used as OE and the WE0 to WE3 signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the A3W1 to A3W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT).only when the ordinary memories are connected. When synchronous DRAM is connected, the RAS3 signal, CAS signal, RD/WR signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Area 4: Area 4 physical addresses A28 to A26 are 1'0. AddressesA31 to A29 are ignored and the address range is H'10000000 + H'20000000 x n - H'13FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Only ordinary memories like SRAM and ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using the A4SZ1 to A4SZ0 bits of BCR2. When the area 4 space is accessed, a CS4 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A4W2 to A4W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). Area 5: Area 5 physical addresses A28 to A26 are 101. Addresses A31 to A29 are ignored and the address range is the 64 Mbytes at H'14000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. When the PCMCIA interface is used, the IC memory card interface address range-comprises the 32 Mbytes at H'14000000 + H'20000000 x n to H'15FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces), and the I/O card interface address range-comprises the 32 Mbytes at H'16000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Rev. 5.00 Dec 12, 2005 page 323 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width using the A5SZ1 to A5SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be selected as the bus width using the A5SZ1 to A5SZ0 bits of BCR2. When the area 5 space is accessed and ordinary memory is connected, a CS5 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and WE, ICIORD, ICIOWR signal are asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2 to A5W0 bits of WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A5W2 to A5W0 bits of WCR2 and the A5W3 bit of PCR. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 11 (2 to 39 for the PCMCIA interface) according to the number of waits. The setup and hold times of address/CS5 for the read/write strobe signal can be set in the range 0.5 to 7.5 cycles using A5TED2 to A5TED0 and A5TEH2 to A5TEH0 bits of the PCR register. (Single-cycle units) Area 6: Area 6 physical addresses A28 to A26 are 110. Address A31 to A29 are ignored and the address range is the 64 Mbytes at H'18000000 + H'20000000 x n to H'1BFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. When the PCMCIA interface is used, the IC memory card interface address range is 32 Mbytes at H'18000000 + H'20000000 x n to H'19FFFFFF + H'2000'000 x n and 'he I/O card interface address range is 32 Mbytes at H'1A000000 + H'20000000 x n to H'1BFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width using the A6SZ1 to A6SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be selected as the bus width using the A6SZ1 to A6SZ0 bits of BCR2. When the area 6 space is accessed and ordinary memory is connected, a CS6 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CI1B signal, CE2B signal, RD signal as OE signal, and WE, ICIORD, and ICIOWR signals are asserted. The number of bus cycles is selected between 0 to 10 wait cycles using the A6W2 to A6W0 bits of WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A6W2 to A6W0 bits of WCR2 and the A6W3 bit of PCR. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). The bus cycle pitch of the burst cycle Rev. 5.00 Dec 12, 2005 page 324 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) is determined within a range of 2 to 11 (2 to 39 for the PCMCIA interface) according to the number of waits. The setup and hold times of address/CS6 for the read/write strobe signals can be set in the range 0.5 to 7.5 cycles using A6TED2 to A6TED0 and A6TEH2 to A6TEH0 bits of the PCR register. (Single-cycle units) 12.3.3 Basic Interface Basic Timing: The basic interface of this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. Figure 12.5 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2 clock falling edge to secure the negation period. Therefore, in case of access at minimum pitch, there is a halfcycle negation period. There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WE signal for the byte to be written is asserted. For details, see section 12.3.1, Endian/Access Size and Data Alignment. Read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes continuously. The bus is not released during this transfer. For cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by longword accesses on the chip-external interface. Write-through-area write access and noncacheable read/write access are based on the actual address size. Rev. 5.00 Dec 12, 2005 page 325 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS Figure 12.5 Basic Timing of Basic Interface Rev. 5.00 Dec 12, 2005 page 326 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Figures 12.6, 12.7, and 12.8 show examples of connection to 32, 16, and 8-bit data-width static RAM, respectively. 128k x 8 bit SRAM A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 * * * * * * * * * * * * * * * * * * * * * * * * * * * * SH7727 A16 A0 CS OE I/O7 I/O0 WE * * * * * * * * * * * * * * * * * * * * * * * * A16 A0 CS OE I/O7 I/O0 WE A16 A0 CS OE I/O7 I/O0 WE * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A16 A0 CS OE I/O7 I/O0 WE * * * * * * * * * * * * Figure 12.6 Example of 32-Bit Data-Width Static RAM Connection Rev. 5.00 Dec 12, 2005 page 327 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) SH7727 A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 * * * * * * * * * * * * * * * * * * * * 128k x 8 bit SRAM A16 A0 CS OE I/O7 I/O0 WE * * * * * * * * * * * * * * * * * * * * A16 A0 CS OE I/O7 I/O0 WE * * * * * * * * * * * * Figure 12.7 Example of 16-Bit Data-Width Static RAM Connection 128k x 8 bit SRAM A16 A0 CSn RD D7 D0 WE0 * * * * * * * * * * * * * * * * SH7727 A16 A0 CS OE I/O7 I/O0 WE * * * * * * * * * * * * * * * * Figure 12.8 Example of 8-Bit Data-Width Static RAM Connection Rev. 5.00 Dec 12, 2005 page 328 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 12.2.4, Wait State Control Register 2 (WCR2). The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 12.9. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS Figure 12.9 Basic Interface Wait Timing (Software Wait Only) When software wait insertion is specified by WCR2, the external wait input WAIT signal is also sampled. TO input low level signal to WAIT, set the WAITSEL bit of the WCR1 register to 1. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software wait. Rev. 5.00 Dec 12, 2005 page 329 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT signal has no effect if asserted in the T1 cycle or the first Tw cycle. The WAIT signal is sampled at the falling edge of the clock. If the setup time and hold times with respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge is used.. However, the WAIT signal is ignored in the following three cases: * When writing to an external address area using DMA 16-byte transfer in dual address mode * When transferring data from a DACK-equipped external device to an external address area using DMA 16-byte transfer in dual address mode * During cache write-back access Wait states inserted by WAIT signal T1 Tw Tw Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 WAIT BS Figure 12.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1) Rev. 5.00 Dec 12, 2005 page 330 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.3.4 Synchronous DRAM Interface Synchronous DRAM Direct Connection: Since synchronous DRAM can be selected by the CS signal, physical space areas 2 and 3 can be connected using RAS and other control signals in common. If the memory type bits (DRAMTP2 to DRAMTP0) in BCR1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both synchronous DRAM space. With this LSI, burst length 1 burst read/single write mode is supported as the synchronous DRAM operating mode. A data bus width of 16 or 32 bits can be selected. A 16-bit burst transfer is performed in a cache fill/write-back cycle, and only one access is performed in a write-through area write or a non-cacheable area read/write. The control signals for direct connection of synchronous DRAM are RAS3, CAS, RD/WR, CS2 or CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid and fetched to the synchronous DRAM only when CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in parallel to a number of areas. CKE is negated (low) only when self-refreshing is performed, and is always asserted (high) at other times. Commands for synchronous DRAM are specified by RAS3, CAS, RD/WR, and special address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register write (MRS). Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In littleendian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to address 4n. Figures 12.11 and 12.12 show examples of the connection of two 1M x 16-bit x 4-bank synchronous DRAMs and one 1M x 16-bit x 4-bank synchronous DRAM, respectively. CKIO and CKIO2 are the clock signals that can be input to the synchronous DRAM. When using multiple synchronous DRAMs, use either CKIO or CKIO2, but not both. Also to prevent big signal delays due to overloading, design the board so that the load capacity is 50 pF or less. Aim to ensure wiring lengths are equal and avoid chaining the clock wiring to the synchronous DRAMs. Rev. 5.00 Dec 12, 2005 page 331 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) CKIO has higher drive capacity than CKIO2. CKIO is suitable for driving heavy load, while CKIO2 offers higher resistance to EMI noise and reflection. However, as the degree of these characteristics vary depending on applications, their usage is not specified. 64M synchronous DRAM (1M x 16-bit x 4-bank) A15 A14 A13 A2 CKIO, CKIO2 CKE CSn RAS3 CAS RD/WR D31 * * * * * * * * * * * * SH7727 A13 A12 A11 * * * * A0 CLK CKE CS RAS CAS WE DQ15 * * * * * * * * * * * * * * * * D16 DQMUU DQMUL D15 D0 DQMLU DQMLL * * * * * * * * DQ0 DQMU DQML A13 A12 A11 * * * * * * * * A0 CLK CKE CS RAS CAS WE DQ15 * * * * * * * * DQ0 DQMU DQML Figure 12.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width) Rev. 5.00 Dec 12, 2005 page 332 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) SH7727 A14 A13 A12 * * * * * * 64M synchronous DRAM (1M x 16-bit x 4-bank) A13 A12 A11 * * * A1 CKIO, CKIO2 CKE CSn RAS3 CAS RD/WR D15 * * * * * * A0 CLK CKE CS RAS CAS WE DQ15 * * * * * * * * * D0 DQMLU DQMLL DQ0 DQMU DQML Figure 12.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMX3 to AMX0 in MCR. Table 12.12 shows the relationship between the address multiplex specification bits and the bits output at the address pins. Table 12.13 shows the relationship between LSI address pins and synchronous DRAM address pins. A25 to A17 and A0 are not multiplexed; the original values are always output at these pins. When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it performs longword address specification. Connection should therefore be made in the following order: with a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to pin A1 of this LSI, then connect pin A1 and pin A2. Rev. 5.00 Dec 12, 2005 page 333 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.12 Relationship between Synchronous DRAM type, bus width and AMX Setting External Address Pin Output Timing A1 to A8 A9 A10 A11 A12 A13 A14 A15 A16 AMX3 AMX2 AMX1 0 32 bits 256 Mbits 4M x 16-bit x 4-bank* 1 1 AMX0 1 Bus Width Memory Type Column address Row address A1-A8 A10-A17 A1-A8 A9-A16 A1-A8 A10-A17 A1-A8 A11-A18 A1-A8 A9-A16 A1-A8 A10-A17 A1-A8 A11-A18 A1-A8 A9-A16 A1-A8 A11-A18 A1-A8 A10-A17 A1-A8 A11-A18 A1-A8 A10-A17 A1-A8 A9-A16 A1-A8 A10-A17 A9 A10 A11 L/H A13 A23 A24 A25 A18 A19 A20 A21 A22 A23 A24 A25 A9 A10 A11 L/H A13 A22 A23 A16 128 Mbits 1M x 32-bit x 4-bank* 0 1 0 0 Column address Row address A17 A18 A19 A20 A21 A22 A23 A16 A9 A10 A11 L/H A13 A23 A24 A16 2M x 16-bit x 4-bank* 0 1 0 1 Column address Row address A18 A19 A20 A21 A22 A23 A24 A16 A9 A10 A11 L/H A13 A24 A25 A16 4M x 8-bit x 4-bank* 0 1 1 0 Column address Row address A19 A20 A21 A22 A23 A24 A25 A16 A9 A10 A11 L/H A13 A22 A23 A16 64 Mbits 1M x 16-bit x 4-bank* 0 1 0 0 Column address Row address A17 A18 A19 A20 A21 A22 A23 A16 A9 A10 A11 L/H A13 A23 A24 A16 2M x 8-bit x 4-bank* 0 1 0 1 Column address Row address A18 A19 A20 A21 A22 A23 A24 A16 A9 A10 A11 L/H A13 A24 A25 A16 4M x 4-bit x 4-bank* 0 1 1 0 Column address Row address A19 A20 A21 A22 A23 A24 A25 A16 A9 A10 A11 L/H A21 A22 A15 A16 512K x 32-bit x 4-bank 0 1 1 1 Column address Row address A17 A18 A19 A20 A21 A22 A23 A16 A9 A10 L/H A12 A13 A24 A25 A16 16 bits 512 Mbits 8M x 16-bit x 4-bank* 1 1 1 0 Column address Row address A19 A20 A21 A22 A23 A24 A25 A16 A9 A10 L/H A12 A22 A23 A24 A16 256 Mbits 4M x 16-bit x 4-bank 1 1 0 1 Column address Row address A18 A19 A20 A21 A22 A23 A24 A16 A9 A10 L/H A12 A23 A24 A25 A16 8M x 8-bit x 4-bank* 1 1 1 0 Column address Row address A19 A20 A21 A22 A23 A24 A25 A16 A9 A10 L/H A12 A22 A23 A24 A16 128 Mbits 2M x 16-bit x 4-bank 0 1 0 1 Column address Row address A18 A19 A20 A21 A22 A23 A24 A16 A9 A10 L/H A12 A21 A22 A15 A16 64 Mbits 1M x 16-bit x 4-bank 0 1 0 0 Column address Row address A17 A18 A19 A20 A21 A22 A23 A16 A9 A10 L/H A12 A22 A23 A15 A16 2M x 8-bit x 4-bank 0 1 0 1 Column address Row address A18 A19 A20 A21 A22 A23 A24 A16 Notes: * L/H is a bit used to specify commands. It is fixed to L or H by the access mode. : Bank address Rev. 5.00 Dec 12, 2005 page 334 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Table 12.13 Relationship between LSI Address Pins and Synchronous DRAM Address Pins SH7727 Address Pin A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS Cycle A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A0 CAS Cycle A16 A23 A22 A13 L/H A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDRAM Address Pin A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Unused Address Address precharge specification Address Function Address BANK select bank address Burst Read: In the example in figure 12.13 it is assumed that four 2M x 8-bit synchronous DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command in the Tc4 cycle, and the read data is accepted on the rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle, but access to synchronous DRAM for another area is possible. In this LSI, the number of Tpc cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the same synchronous DRAM during this interval. To connect low-speed synchronous DRAM, the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the RCD bit in MCR, with a values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or more cycles, a Trw cycle, in which an NOP command is Rev. 5.00 Dec 12, 2005 page 335 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ and READA command output cycles Tc1 to Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of A2W1 and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tr CKIO, CKIO2 A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3 CAS RD/WR DQMxx D31 to D0 BS Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Tpc Figure 12.13 Basic Timing for Synchronous DRAM Burst Read Figure 12.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle. When a burst read is performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16 bytes, address updating is performed for A3 and A2 only. The order of access is as follows: in a Rev. 5.00 Dec 12, 2005 page 336 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode. Tr CKIO, CKIO2 A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3 CAS RD/WR DQMxx Trw Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 Tpc D31 to D0 BS Figure 12.14 Synchronous DRAM Burst Read Wait Specification Timing Single Read: Figure 12.15 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Rev. 5.00 Dec 12, 2005 page 337 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tr CKIO, CKIO2 A25 to A16, A13 A12 A15, A14, A11 to A0 CS2 or CS3 RAS3 Tc1 Td1 Tpc CAS RD/WR DQMxx D31 to D0 BS Figure 12.15 Basic Timing for Synchronous DRAM Single Read Burst Write: The timing chart for a burst write is shown in figure 12.16. In this LSI, a burst write occurs only in the event of cache write-back. In a burst write operation, following the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto-precharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as the write command. In case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR. Rev. 5.00 Dec 12, 2005 page 338 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tr CKIO, CKIO2 Tc1 Tc2 Tc3 Tc4 (Tpc) (Tpc) Address upper bits A12, A11, A10 or A9 Address lower bits CSn RD/WR RAS3 CAS DQMxx D31 to D0 (read) BS Figure 12.16 Basic Timing for Synchronous DRAM Burst Write Rev. 5.00 Dec 12, 2005 page 339 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Single Write: The basic timing chart for write access is shown in figure 12.17. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command. In case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR. Rev. 5.00 Dec 12, 2005 page 340 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tr Tc1 (Trwl) (Tpc) CKIO, CKIO2 Address upper bits A12 or A10 Address lower bits CSn RD/WR RAS3 CAS DQMxx D31 to D0 BS CKE Figure 12.17 Basic Timing for Synchronous DRAM Single Write Rev. 5.00 Dec 12, 2005 page 341 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retain is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. 1. Auto-Refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2 to CKS0 setting. When the clock is selected by CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 12.18 shows the autorefresh cycle timing. All-bank precharging is performed in the Tp cycle, then an REF command is issued in the TRr cycle following the interval specified by the TPC bits in MCR. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by the TRAS bits in MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS and TPC bits must be set so as to satisfy the synchronous DRAM refresh cycle time stipulation (active/active command delay time). Auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset. RTCNT cleared to 0 when RTCNT = RTCOR RTCOR value RTCNT H'00000000 RTCSR.CKS(2-0) CMF CMF flag cleared by start of refresh cycle External bus Auto-refresh cycle = 000 000 Time Figure 12.18 Auto-Refresh Operation Rev. 5.00 Dec 12, 2005 page 342 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tp TRr TRrw TRrw (Tpc) CKIO, CKIO2 CKE CSn RAS3 CAS RD/WR Figure 12.19 Synchronous DRAM Auto-Refresh Timing 2. Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the TPC bits in MCR. Self-refresh timing is shown in figure 12.20. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of selfRev. 5.00 Dec 12, 2005 page 343 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using this LSI's standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a manual reset. In addition, halt USB and LCDC before entering standby mode. When the synchronous DRAM is used, self-refreshing is initiated in the following procedure. 1. Clear the refresh control bit to 0. 2. Write H'00 to RTCNT 3. Set the refresh control bit and refresh mode bit to 1. Tp TRs1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO, CKIO2 CKE CSn RAS3 CAS RD/WR Figure 12.20 Synchronous DRAM Self-Refresh Timing Rev. 5.00 Dec 12, 2005 page 344 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'FFFFD000 + X for area 2 synchronous DRAM, and to address H'FFFFE000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 1 to 3, wrap type = sequential, and burst length 1 supported by this LSI, arbitrary data is written in a bytesize access to the following addresses. With 32-bit bus width: CAS latency 1 CAS latency 2 CAS latency 3 With 16-bit bus width: CAS latency 1 CAS latency 2 CAS latency 3 Area 2 FFFFD420 FFFFD440 FFFFD460 Area 3 FFFFE420 FFFFE440 FFFFE460 Area 2 FFFFD840 FFFFD880 FFFFD8C0 Area 3 FFFFE840 FFFFE880 FFFFE8C0 Mode register setting timing is shown in figure 12.21. As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks (PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued in the TMw1 cycle. Address signals, when the mode-register write command is issued, are as follows: A15 to A9 = 0000100 (burst read and single write) A8 to A6 = CAS latency A5 = 0 (burst type = sequential) A4 to A2 = 000 (burst length 1) Before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is usually achieved automatically while various kinds of initialization are being Rev. 5.00 Dec 12, 2005 page 345 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) performed after auto-refresh setting, but a way of carrying this out more dependably is to set a short refresh request generation interval just while these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for autorefreshing is not initialized, and so the cycle must always be an auto-refresh cycle. TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO, CKIO2 A15 to A13 or A15 to A12 A11 A12 or A10 A9 to A2 CSn RD/WR RAS3 CAS D31 to D0 CKE (High) Figure 12.21 Synchronous DRAM Mode Write Timing Rev. 5.00 Dec 12, 2005 page 346 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.3.5 Burst ROM Interface Setting bits A0BST (1, 0), A5BST (1, 0), and A6BST (1, 0) in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a nibble access function. The timing for nibble access to burst ROM is shown in figure 12.22. Two wait cycles are set. Basically, access is performed in the same way as for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address is changed before the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1, 0), A5BST (1, 0), or A6BST (1, 0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is connected, only 4 can be set. WAIT pin sampling is performed in the first access if one or more wait states are set, and is always performed in the second and subsequent accesses. Even if no wait state insertion is specified in burst ROM interface settings, two wait cycles are automatically inserted in the second and subsequent accesses as shown in figure 12.23. However, the WAIT signal is ignored in the following three cases: * * * When writing to an external address area using DMA 16-byte transfer in dual address mode When transferring data from a DACK-equipped external device to an external address area using DMA 16-byte transfer in single address mode During cache write-back access Rev. 5.00 Dec 12, 2005 page 347 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) T1 CKIO TW TW TB2 TB1 TW TB2 TB1 T2 A25 to A4 A3 to A0 CSn RD/WE RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 12.22 Burst ROM Wait Access Timing Rev. 5.00 Dec 12, 2005 page 348 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO A25 to A4 A3 to A0 CSn RD/WE RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 12.23 Burst ROM Basic Access Timing Rev. 5.00 Dec 12, 2005 page 349 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.3.6 PCMCIA Interface In this LSI, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2. When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and A5SZ0, or A6SZ1 and A6SZ0, in BCR2. Figure 12.24 shows an example of PCMCIA card connection to this LSI. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between this LSI's bus interface and the PCMCIA cards. As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications, the PCMCIA interface for this LSI in big-endian mode is stipulated independently. However, the WAIT signal is ignored in the following three cases: * * * When writing to an external address area using DMA 16-byte transfer in dual address mode When transferring data from a DACK-equipped external device to an external address area using DMA 16-byte transfer in single address mode During cache write-back access Rev. 5.00 Dec 12, 2005 page 350 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) A24 to A0 D15 to D0 RD/WR CE1B/(CS6) CE1A/(CS5)/(PTK[3]) CE2B/(PTE[5]) CE2A/(PTE[4]) D7 to D0 G DIR D15 to D8 G DIR G A25 to A0 D15 to D0 PC card (memory/IO) SH7727 RD WE/(WE1)/(DQMLU) ICIORD/(WE2)/ (DQMUL)/(PTK[6]) ICIOWR/(WE3)/ (DQMUU)/(PTK[7]) WAIT IOIS16/(PTG[7]) CE1 CE2 OE WE/PGM (IORD) G (IOWR) WAIT (IOIS16) Card detection circuit Output port D7 to D0 G DIR D15 to D8 G DIR D15 to D0 CD1, CD2 A25 to A0 G PC card (memory/IO) G CE1 CE2 OE WE/PGM WAIT Card detection circuit CD1, CD2 Figure 12.24 Example of PCMCIA Interface (If Internal PC Card Controller is not used.) Rev. 5.00 Dec 12, 2005 page 351 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Memory Card Interface Basic Timing: Figure 12.25 shows the basic timing for the PCMCIA IC memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically performed as IC memory card interface accesses. With a high external bus frequency (CKIO), the setup and hold times for the address (A24 to A0), card enable (CS5, CE2A, CS6, CE2B), and write data (D15 to D0) in a write cycle, become insufficient with respect to RD and WR (the WE pin in this LSI). This LSI provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register. Also, software waits by means of a WCR2 register setting and hardware waits by means of the WAIT pin can be inserted in the same way as for the basic interface. Figure 12.26 shows the PCMCIA memory bus wait timing. Rev. 5.00 Dec 12, 2005 page 352 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tpcm1 Tpcm2 CKIO A25 to A0 CExx RD/WR RD (read) D15 to D0 (read) WE (write) D15 to D0 (read) BS Figure 12.25 Basic Timing for PCMCIA Memory Card Interface Rev. 5.00 Dec 12, 2005 page 353 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tpcm0 CKIO Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w A25 to A0 CExx RD/WR RD (read) D15 to D0 (read) WE (write) D15 to D0 (write) BS WAIT Figure 12.26 Wait Timing for PCMCIA Memory Card Interface Rev. 5.00 Dec 12, 2005 page 354 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Memory Card Interface Burst Timing: In this LSI, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area 6. This burst access mode is not stipulated in JEIDA version 4.2 (PCMCIA2.1), but allows highspeed data access using ROM provided with a burst mode, etc. Burst access mode timing is shown in figures 12.27 and 12.28. Tpcm1 CKIO Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 A25 to A4 A3 to A0 CExx RD/WR RD (read) D15 to D0 (read) BS Figure 12.27 Basic Timing for PCMCIA Memory Card Interface Burst Access Rev. 5.00 Dec 12, 2005 page 355 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A4 A3 to A0 CExx RD/WR RD (read) D15 to D0 (read) BS WAIT Figure 12.28 Wait Timing for PCMCIA Memory Card Interface Burst Access Rev. 5.00 Dec 12, 2005 page 356 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) When the IC memory card interface uses entire 32-Mbyte memory space, the REG signal to switch common memory and attribute memory can be generated by a port. If the IC card memory interface uses memory area of 16 Mbytes or less, 32-Mbyte memory space can be used as 16Mbyte common memory space and 16-Mbyte attribute memory space as shown in figure 12.29. In this case, A24 pin can be used as the REG signal. IC memory interface = 32 Mbytes (I/O port is used for REG) Area 5: H'14000000 Area 5: H'16000000 Area 6: H'18000000 Area 6: H'1A000000 Common/Attribute memory I/O space Common/Attriute memory I/O space IC memory interface = 16 Mbytes or less (A24 is used for REG) Area 5: H'14000000 Area 5: H'15000000 Area 5: H'16000000 H'17000000 Area 6: H'18000000 Area 6: H'19000000 Area 6: H'1A000000 H'1B000000 Attribute memory Common memory I/O space Attribute memory Common memory I/O space Figure 12.29 PCMCIA Space Assignment Rev. 5.00 Dec 12, 2005 page 357 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) I/O Card Interface Timing: Figures 12.30 and 12.31 show the timing for the PCMCIA I/O card interface. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designed for physical space area 5, the bus access is automatically performed as an I/O card interface access when a physical address from H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6, the bus access is automatically performed as an I/O card interface access when a physical address from H'1A000000 to H'1BFFFFFF is accessed. When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU. When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for area 5 or area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits. Figure 12.32 shows the basic timing for dynamic bus sizing. In big-endian mode, the IOIS16 signal is not supported. In big-endian mode, the IOIS16 signal should be fixed low. Rev. 5.00 Dec 12, 2005 page 358 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tpci1 Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS Figure 12.30 Basic Timing for PCMCIA I/O Card Interface Rev. 5.00 Dec 12, 2005 page 359 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tpci0 CKIO Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Figure 12.31 Wait Timing for PCMCIA I/O Card Interface Rev. 5.00 Dec 12, 2005 page 360 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Tpci0 CKIO Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w A25 to A1 A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) BS WAIT IOIS16 Figure 12.32 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev. 5.00 Dec 12, 2005 page 361 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.3.7 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. This results in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write. If there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. There are two cases in which a wait cycle is inserted: when an access is followed by an access to a different area, and when a read access is followed by a write access from this LSI. When this LSI performs consecutive write cycles, the data transfer direction is fixed (from this LSI to other memory) and there is no problem. With read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertion is not performed. Bits AnIW1 and AnIW0 (n = 0, 2 to 6) in WCR1 specify the number of idle cycles to be inserted between access cycles when a physical space area access is followed by an access to another area, or when this LSI performs a write access after a read access to physical space area n. If there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. Waits are not inserted between accesses when bus arbitration is performed, since empty cycles are inserted for arbitration purposes. Rev. 5.00 Dec 12, 2005 page 362 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) T1 CKIO A25 to A0 CSm CSn BS RD/WR RD D31 to D0 T2 Twait T1 T2 Twait T1 T2 Area m read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 12.33 Waits between Access Cycles 12.3.8 Bus Arbitration When a bus release request (BREQ) is received from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not released during burst transfers for cache fills or TAS instruction execution between the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when longword access is executed for the 8-bit memory. At the negation of BREQ, BACK is negated and bus use is restarted. See Appendix A.1, Pin Functions, for the pin state when the bus is released. Rev. 5.00 Dec 12, 2005 page 363 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) 12.3.9 Bus Pull-Up With this LSI, address pin pull-up can be performed when the bus is released by setting the PULA bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted. Figure 12.34 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed by setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data bus is not in use. The data pin pull-up timing for a read cycle is shown in figure 12.35, and the timing for a write cycle in figure 12.36. CKIO A25 to A0 Pull-up Hi-Z BACK Figure 12.34 Pins A25 to A0 Pull-Up Timing CKIO D31 to D0 Pull-up Pull-up RD CSn Figure 12.35 Pins D31 to D0 Pull-Up Timing (Read Cycle) Rev. 5.00 Dec 12, 2005 page 364 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) CKIO D31 to D0 Pull-up Pull-up WEn CSn Figure 12.36 Pins D31 to D0 Pull-Up Timing (Write Cycle) Rev. 5.00 Dec 12, 2005 page 365 of 1034 REJ09B0254-0500 Section 12 Bus State Controller (BSC) Rev. 5.00 Dec 12, 2005 page 366 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) Section 13 Li Bus State Controller (LBSC) 13.1 Overview The Li bus state controller (LBSC) functions enable LCD controller and Open HCI compliant USB Host controller to link directly with synchronous DRAM. LBSC is a slave bus state controller of BSC. 13.1.1 Features The LBSC has the following features: * Direct interface to synchronous DRAM Physical address space is specified only to area 3 A maximum 64 Mbytes Multiplexes row/column addresses according to synchronous DRAM capacity Supports burst operation with various burst length; selectable from 1 to 32 Controls timing of synchronous DRAM direct-connection control signals according to register setting 16-bit or 32-bit bus width according to register setting 13.1.2 Register Configuration The LBSC does not have any register inside, but refers BSC registers shown in table 13.1. Table 13.1 Register Configuration Name Bus control register 1 Bus control register 2 Wait state control register 1 Wait state control register 2 Individual memory control register Abbr. BCR1 BCR2 WCR1 WCR2 MCR R/W R/W R/W R/W R/W R/W Initial Value* H'0000 H'3FF0 H'3FF3 H'FFFF H'0000 Address H'FFFFFF60 H'FFFFFF62 H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 Bus Width 16 16 16 16 16 Note: * Initialized by power-on resets. Rev. 5.00 Dec 12, 2005 page 367 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) 13.1.3 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle state for each area. It is initialized to H'0000 by a power-on reset, but it is not initialized by a manual reset or in standby mode. Do not access external memory except area 0 until BCR1 register initialization is complete. Bit: Initial value: R/W: Bit: 15 PULA 0 R/W 7 14 PULD 0 R/W 6 13 0 R/W 5 12 0 R/W 4 DRAM TP2 0 R/W 11 0/1* R 3 DRAM TP1 0 R/W 10 0 R/W 2 DRAM TP0 0 R/W 9 0 R/W 1 8 0 R/W 0 HIZMEM HIZCNT ENDIAN A0BST1 A0BST0 A5BST1 A5BST0 A6BST1 A6BST0 Initial value: R/W: 0 R/W 0 R/W 0 R/W A5PCM A6PCM 0 R/W 0 R/W Note: * Samples the value of the external pin (MD5) designating endian at power-on reset. Bits 15 to 12--Not referenced Bit 11--Endian Flag (ENDIAN): Samples a value at the external pin which designates endian (MD5) at a power-on reset. Endian for all physical spaces is decided by this bit. This bit is readonly. Bit 11: ENDIAN 0 1 Description At a reset, the endian setting external pin (MD5) is low, which indicates that the SH7727 is set as big endian. At a reset, the endian setting external pin (MD5) is high, which indicates that the SH7727 is set as little endian. Bits 10 to 5--Not referenced Rev. 5.00 Dec 12, 2005 page 368 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) Bits 4 to 2--Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Specifies the type of memory connected to the physical space areas 2 and 3. Before using LCDC and USB, set area 3 to synchronous DRAM (DRAMTP2 to DRAMTP0 equal to 010 or 011). Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description 0 0 0 1 1 0 1 1 0 1 0 1 0 1 Ordinary memory for areas 2 and 3 (Initial value) Reserved (Setting disabled) Ordinary memory for area 2 and 1 synchronous DRAM for area 3* 12 Synchronous DRAM for areas 2 and 3* * Reserved Reserved Reserved (Setting disabled) Reserved (Setting disabled) Notes: 1. It is not possible to access synchronous DRAM if clock ratio I:bus clock = 1:1. 2. When selecting this mode, set the same bus width for area 2 and area 3. Bits 1 and 0 --Not referenced Rev. 5.00 Dec 12, 2005 page 369 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) 13.1.4 Bus Control Register 2 (BCR2) The bus control register 2 (BCR2) is a 16-bit read/write register that sets the bus-size width of each area and selects whether an 8-bit port is used or not. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or by standby mode. Do not access external memory outside area 0 until BCR2 register initialization is complete. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 A3SZ1 1 R/W 14 -- 0 R 6 A3SZ0 1 R/W 13 A6SZ1 1 R/W 5 A2SZ1 1 R/W 12 A6SZ0 1 R/W 4 A2SZ0 1 R/W 11 A5SZ1 1 R/W 3 -- 0 R 10 A5SZ0 1 R/W 2 -- 0 R 9 A4SZ1 1 R/W 1 -- 0 R 8 A4SZ0 1 R/W 0 -- 0 R Bits 15 to 8 and 5 to 0 --Not referenced Bits 7 and 6--Area 3 Bus Size Specification (A3SZ1, A3SZ0): Specifies the bus sizes of physical space area 3. Bit 7: A3SZ1 0 1 0 1 Bit 6: A3SZ0 0 1 0 1 0 1 0 1 Used Port A/B Unused Description Reserved (Setting disabled) Reserved (Setting disabled) 16-bit bus width 32-bit bus width Reserved (Setting disabled) Reserved (Setting disabled) 16-bit bus width Reserved (Setting disabled) Rev. 5.00 Dec 12, 2005 page 370 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) 13.1.5 Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. This can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. This LSI automatically inserts idle states equal to the number set in WCR1 in those cases. WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by standby mode. Bit: 15 WAIT SEL Initial value: R/W: Bit: Initial value: R/W: 0 R/W 7 A3IW1 1 R/W 14 -- 0 R 6 A3IW0 1 R/W 13 A6IW1 1 R/W 5 A2IW1 1 R/W 12 A6IW0 1 R/W 4 A2IW0 1 R/W 11 A5IW1 1 R/W 3 -- 0 R 10 A5IW0 1 R/W 2 -- 0 R 9 A4IW1 1 R/W 1 A0IW1 1 R/W 8 A4IW0 1 R/W 0 A0IW0 1 R/W Bits 15 to 8 and 5 to 0 --Not referenced Bits 7 and 6-- Area 3 Idle Setting between Cycles (A3IW1, A3IW0): Specifies the number of idle state cycles to insert between bus cycles when switching from a read address in area 3 of the physical space to a write address in another space or within the same space. Bit 7: A3IW1 0 1 Bit 6: A3IW0 0 1 0 1 Description 1 idle state cycle inserted 1 idle state cycle inserted 2 idle state cycle inserted 3 idle state cycle inserted (Initial value) Rev. 5.00 Dec 12, 2005 page 371 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) 13.1.6 Wait State Control Register 2 (WCR2) Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory accesses. This allows direct connection of even low-speed memories without an external circuit. WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 A6W2 1 R/W 7 A4W0 1 R/W 14 A6W1 1 R/W 6 A3W1 1 R/W 13 A6W0 1 R/W 5 A3W0 1 R/W 12 A5W2 1 R/W 4 A2W1 1 R/W 11 A5W1 1 R/W 3 A2W0 1 R/W 10 A5W0 1 R/W 2 A0W2 1 R/W 9 A4W2 1 R/W 1 A0W1 1 R/W 8 A4W1 1 R/W 0 A0W0 1 R/W Bits 15 to 7 and 4 to 0 --Not referenced Bits 6 and 5-- Area 3 Wait Control (A3W1, A3W0): Specifies the CAS latency for the SDRAM of area 3 of the physical space. Bit 6: A3W1 0 1 Bit 5: A3W0 0 1 0 1 Description SDRAM CAS Latency 1 1 2 3 (Initial value) Rev. 5.00 Dec 12, 2005 page 372 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) 13.1.7 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without external circuits. The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or standby mode. The bits TPC1 to TPC0, RCD1 to RCD0, TRWL1 to TRWL0, TRAS1 to TRAS0, and AMX3 to AMX0 are written to at the initialization after a power-on reset and should not be modified again. When RFSH and RMODE are written to, write the same values to the other bits. When using synchronous DRAM, do not access areas 2 and 3 until this register initialization is complete. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TPC1 0 R/W 7 -- 0 R/W 14 TPC0 0 R/W 6 AMX3 0 R/W 13 RCD1 0 R/W 5 AMX2 0 R/W 12 RCD0 0 R/W 4 AMX1 0 R/W 11 TRWL1 0 R/W 3 AMX0 0 R/W 10 TRWL0 0 R/W 2 RFSH 0 R/W 9 TRAS1 0 R/W 1 RMODE 0 R/W 8 TRAS0 0 R/W 0 -- 0 R/W Bits 15 and 14--RAS Precharge Time (TPC1, TPC0): When synchronous DRAM interface is selected, these bits set the minimum number of cycles until output of the next bank-active command after precharge. Bit 15: TPC1 0 1 Bit 14: TPC0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles 4 cycles (Initial value) Rev. 5.00 Dec 12, 2005 page 373 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) Bits 13 and 12--RAS-CAS Delay (RCD1, RCD0): When synchronous DRAM interface is selected, these bits set the bank active read/write command delay time. Bit 13: RCD1 0 1 Bit 12: RCD0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles 4 cycles (Initial value) Bits 11 and 10--Write-Precharge Delay (TRWL1, TRWL0): The TRWL bits set the synchronous DRAM write-precharge delay time. This designates the time between the end of a write cycle and the automatic precharge activation. After the write cycle, the next bank-active command is not issued for the period TPC + TRWL. Bit 11: TRWL1 0 1 Bit 10: TRWL0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles Reserved (Setting disabled) (Initial value) Bits 9 and 8--CAS CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): When CAS RAS synchronous DRAM interface is selected, no bank-active command is issues during the period TPC + TRAS after an auto-refresh command. Bit 9: TRAS1 0 1 Bit 8: TRAS0 0 1 0 1 Description 2 cycles 3 cycles 4 cycles 5 cycles (Initial value) Bit 7--Reserved: This bit is always read as 0 and should only be written with 0. Rev. 5.00 Dec 12, 2005 page 374 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) Bits 6 to 3--Address Multiplex (AMX3 , AMX2, AMX1, AMX0): The AMX bits specify address multiplexing for synchronous DRAM. Bit6: AMX3 1 Bit5: AMX2 1 Bit 4: AMX1 0 Bit 3: AMX0 1 Description When using a 16-bit bus width, the row address begins with A10. When using a 32-bit bus width, it begins with A11. (The A10 value is output at A1 when the row address is output. 4M x 16-bit x 4-bank products) When using a 16-bit bus width, the row address begins with A11. (The A11 value is output at A1 when the row address is 1 output. 8M x 16-bit x 4-bank products)* When using a 16-bit bus width, the row address begins with A9. When using a 32-bit bus width, it begins with A10. (The A9 value is output at A1 when the row address is output. 1M x 16-bit x 4-bank products) When using a 16-bit bus width, the row address begins with A10. When using a 32-bit bus width, it begins with A11. (The A10 value is output at A1 when the row address is output. 2M x 8-bit products) The row address begins with A11 when bus width is 32 bit. * (The A11 value is output at A1 when the row address is output. 4M x 8-bit x 4-bank products) 1 1 When using a 16-bit bus width, the row address begins with A9. When using a 32-bit bus width, it begins with A10. (The A9 value is output at A1 when the row address is output. 2 512K x 32-bit x 4-bank products) * Reserved. AMX3 to AMX0 must be set to *1*** before accessing synchronous DRAM memory. (Initial value) Reserved (Illegal setting) 2 1 0 0 1 0 0 1 0 0 Other values 0 0 Notes: 1. Can be set only when using a 16-bit bus width. 2. Can be set only when using a 32-bit bus width. Bits 2 and 1--Not referenced Bit 0--Reserved: This bit is always read as 0 and should only be written with 0. Rev. 5.00 Dec 12, 2005 page 375 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) 13.2 13.2.1 LBSC Operation Bus Sharing Architecture LCDC and USB Host Controller can share the system memory with CPU and DMA Controller, so these bus masters are able to work without any independent external memory and have huge available memory space up to 64 Mbyte at area 3. Since each LCDC, USB Host Controller, CPU, and DMA Controller can access area 3 individually. Set addresses for each controller to avoid address sharing. 13.2.2 Usable System Memory LBSC works at below memories. Memory area Memory type Bus width Burst length Area3 Synchronous DRAM 16 or 32 bits 1 to 4 burst (USBH) 4 to 32 burst (LCDC) with 32-bit bus width, 8 to 64 burst (LCDC) with 16-bit bus width 13.2.3 Bus Arbitration LBSC accepts a request that comes from LCDC or USB Host at a same time without any prioritization to each module. LBSC tries to get bus right from BSC at any time when it get a request from LCDC or USB Host. Once BSC gives LBSC a right, LCDC or BSC can access external memory directly. The arbiter of LBSC gives a bus right to LCDC or USB Host as even. 13.2.4 LCDC Li Bus Access While displaying images, the LCDC continuously reads data from the system memory with a 32 burst length. The LCDC burst length is specified by a register in the LCDC. If the data length is shorter than 32 burst length, such as the case for the edge of LCD panel, the LCDC uses a shorter burst length. Rev. 5.00 Dec 12, 2005 page 376 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) 13.2.5 USBH Li Bus Access USB Host issues 1 to 4 burst request to LBSC as normal read or write action. Since the burst length issued by USB Host is occasionally changed as FIFO pointer rises up or falls, it is not supposed as 4 burst exactly. BSC SH7727 Bus arbitration Synchronous DRAM (Area 3) USBH LBSC Li bus LCDC Bus Figure 13.1 Block Diagram of Li Bus Architecture 13.2.6 Setting of DMA Transfer with Bus Arbitration of Other Module This LSI has five types of bus master: CPU, DMAC and Refresh (BSC system), and LCDC and USBH (LBSC system). The following priority order is set for these buses. 1. The BSC and LBSC systems are the same in priority level. 2. In the BSC system, Refresh has the highest priority. 3. Between CPU and DMAC, DMAC is higher in priority when DMA burst setting is made. In cycle steal, CPU and DMAC are the same in priority level. 4. LCDC and USBH are the same priority level in the LBSC system. In cycle steal, the priority level of DMA transfer is very low. Therefore, if the DMAC transfer speed may cause problems, it is recommended to use the level-input burst transfer setting for DMAC, especially when DREQ signals from an external device can be negated. Rev. 5.00 Dec 12, 2005 page 377 of 1034 REJ09B0254-0500 Section 13 Li Bus State Controller (LBSC) Rev. 5.00 Dec 12, 2005 page 378 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Section 14 Direct Memory Access Controller (DMAC) 14.1 Overview This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip supporting modules (SIOF, SCIF, USB function, and A/D converter). Using the DMAC reduces the burden on the CPU and increases overall operating efficiency. 14.1.1 Features The DMAC has the following features. * Four channels * 4-GB physical address space * Selectable data transfer length: 8-bit, 16-bit, 32-bit, or 16-byte transfer (In 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit writes.) * Maximum of 16 M times of transfers (16777216 times) * Address mode: Dual address mode and single address mode are supported. In addition, direct address transfer mode or indirect address transfer mode can be selected. Dual address mode transfer: Both the transfer source and transfer destination are accessed by address. Dual address mode has direct address transfer mode and indirect address transfer mode. Direct address transfer mode: The values specified in the DMAC registers indicates the transfer source and transfer destination. Two bus cycles are required for one data transfer. Indirect address transfer mode: Data is transferred with the address stored prior to the address specified in the transfer source address in the DMAC. Other operations are the same as those of direct address transfer mode. This function is only valid in channel 3. Four bus cycles are requested for one data transfer. Single address mode transfer: Either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. One transfer unit of data is transferred in one bus cycle. * Channel functions: Transfer mode that can be specified is different in each channel. Channel 0: Can accept requests from peripheral modules and external requests. Channel 1: Can accept requests from peripheral modules. Channel 2: Can accept requests from peripheral modules. This channel has a source address reload function, which reloads a source address for each 4 transfers. Rev. 5.00 Dec 12, 2005 page 379 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Channel 3: Can accept requests from peripheral modules. Direct address transfer mode or indirect address transfer mode can be specified. * Reload function: The value that was specified in the source address register can be automatically reloaded every 4 DMA transfers. This function is only valid in channel 2. * Three types of transfer requests External requests (From two DREQ pins (channels 0 only). DREQ can be detected either by falling edge or by low level) On-chip module requests (Requests from on-chip supporting modules such as serial communications interface (SIOF, SCIF), A/D converter (A/D) and a timer (CMT) . This request can be accepted in all the channels) Auto requests (the transfer request is generated automatically within the DMAC) * Selectable bus modes: Cycle-steal mode or burst mode * Selectable channel priority levels: Fixed mode: The channel priority is fixed. Round-robin mode: The priority of the channel in which the execution request was accepted is made the lowest. * Interrupt request: An interrupt request can be generated to the CPU after the specified number of times of transfers. Rev. 5.00 Dec 12, 2005 page 380 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.1.2 Block Diagram Figure 14.1 is a block diagram of the DMAC. DMAC module Interation control X/Y memory Peripheral bus SARn Register control Internal bus DARn On-chip supporting module USBF SIOF Selector Ch0 to Ch3 CHRAR DMATCRn Start-up control CHCRn DMAOR DREQ0 SCIF A/D converter CMT DEIn DACK0, DRAK0 Request priority control External ROM External RAM Bus interface Legend: External I/O (memory mapped) External I/O (with acknowledge) Bus state controller DMAOR: DMAC operation register DMAC source address register SARn: DMAC destination address register DARn: DMATCRn: DMAC transfer count register CHCRn: DMAC channel control register CHRAR: DMA channel assign register DMA transfer-end interrupt request to DEIn: CPU 0 to 3 n: Figure 14.1 DMAC Block Diagram Rev. 5.00 Dec 12, 2005 page 381 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.1.3 Pin Configuration Table 14.1 shows the DMAC pins. Table 14.1 Pin Configuration Channel 0 Name DMA transfer request DREQ acknowledge Symbol DREQ0 DACK0 I/O Input Output Function DMA transfer request input from external device to channel 0 Strobe output to an external I/O at DMA transfer request from external device to channel 0 Output showing that DREQ0 has been accepted DMA request acknowledge DRAK0 Output 14.1.4 Register Configuration Table 14.2 summarizes the DMAC registers. DMAC has a total of 18 registers, four registers for each channel and two registers for controlling all channels. Table 14.2 DMAC Registers Channel 0 Name DMA source address register 0 Abbreviation SAR0 R/W R/W R/W Initial Value Undefined Undefined Undefined Address Register Access Size Size 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 H'04000020 32 bits (H'A4000020)*4 H'04000024 32 bits (H'A4000024)*4 H'04000028 24 bits (H'A4000028)*4 DMA destination address DAR0 register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMATCR0 R/W CHCR0 SAR1 R/W*1 H'00000000 H'0400002C 32 bits (H'A400002C)*4 R/W R/W Undefined Undefined Undefined H'04000030 32 bits (H'A4000030)*4 H'04000034 32 bits (H'A4000034)*4 H'04000038 24 bits (H'A4000038)*4 DMA destination address DAR1 register 1 DMA transfer count register 1 DMA channel control register 1 DMATCR1 R/W CHCR1 R/W*1 H'00000000 H'0400003C 32 bits (H'A400003C)*4 Rev. 5.00 Dec 12, 2005 page 382 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Abbreviation SAR2 Initial Value Undefined Undefined Undefined Register Access Size Size 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 16, 32*2 16, 32*2 16, 32*3 8, 16, 32*2 8, 16*2 16 Channel 2 Name DMA source address register 2 R/W R/W R/W Address H'04000040 32 bits (H'A4000040)*4 H'04000044 32 bits (H'A4000044)*4 H'04000048 24 bits (H'A4000048)*4 DMA destination address DAR2 register 2 DMA transfer count register 2 DMA channel control register 2 3 DMA source address register 3 DMATCR2 R/W CHCR2 SAR3 R/W*1 H'00000000 H'0400004C 32 bits (H'A400004C)*4 R/W R/W Undefined Undefined Undefined H'04000050 32 bits (H'A4000050)*4 H'04000054 32 bits (H'A4000054)*4 H'04000058 24 bits (H'A4000058)*4 DMA destination address DAR3 register 3 DMA transfer count register 3 DMA channel control register 3 Shared DMA operation register DMA channel assign register DMATCR3 R/W CHCR3 DMAOR CHRAR R/W*1 H'00000000 H'0400005C 32 bits (H'A400005C)*4 R/W *1 H'0000 R/W H'0000 H'04000060 16 bits (H'A4000060)*4 H'0400022A 16 bits (H'A400022A)*4 Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Only a write of 0 after a read of 1 to clear a flag is enabled for bit 1 in CHCR0 to CHCR3 and bits 1 and 2 in DMAOR. 2. If SAR0 to SAR3, DAR0 to DAR3, and CHCR0 to CHCR3 are accessed in 16 bits, the 16 bit values that were not accessed are held. 3. DMATCR comprises the 24 bits from bit 0 to bit 23. The upper 8 bits, bits 24 to 31, cannot be written with 1 and are always read as 0. 4. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 383 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.2 14.2.1 Register Descriptions DMA Source Address Registers 0 to 3 (SAR0 to SAR3) Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 23 -- R/W 30 -- R/W 22 -- R/W 29 -- R/W 21 -- R/W 28 -- R/W 20 -- R/W 27 -- R/W 26 -- R/W ... ... ... ... -- R/W 25 -- R/W 24 -- R/W 0 The DMA source address registers 0 to 3 (SAR0 to SAR3) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. If any other address is specified, correct operation is not guaranteed. Initial values are undefined after a reset. The previous values are held in standby mode. Rev. 5.00 Dec 12, 2005 page 384 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3) Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R/W 23 -- R/W 30 -- R/W 22 -- R/W 29 -- R/W 21 -- R/W 28 -- R/W 20 -- R/W 27 -- R/W 26 -- R/W ... ... ... ... -- R/W 25 -- R/W 24 -- R/W 0 The DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit read/write registers that specify the destination address of a DMA transfer. These registers include count functions, and during a DMA transfer, these registers indicate the next destination address. To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary. When transferring data in 16-byte units, always set a value at a 16-byte boundary (16n address) as the destination address. If any other address is specified, correct operation is not guaranteed. Initial values are undefined after a reset. The previous value is held in standby mode. Rev. 5.00 Dec 12, 2005 page 385 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- R 23 -- R/W 30 -- R 22 -- R/W 29 -- R 21 -- R/W 28 -- R 20 -- R/W 27 -- R 26 -- R ... ... ... ... -- R/W 25 -- R 24 -- R 0 The DMA transfer count registers 0 to 3 (DMATCR0 to DMATCR3) are 24-bit read/write registers that specify the DMA transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is H'000001, and 16777216 (the maximum) when H'000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The upper eight bits in DMATCR are always read as 0 and should only be written with 0. Initial values are undefined after a reset. The previous value is held in standby mode. Rev. 5.00 Dec 12, 2005 page 386 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3) Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 -- 0 R 15 DM1 0 R/W 7 -- 0 R ... ... ... ... 14 DM0 0 R/W 6 DS 0 2 (R/W)* 21 -- 0 R 13 SM1 0 R/W 5 TM 0 R/W 20 DI 0 (R/W) 12 SM0 0 R/W 4 TS1 0 R/W *2 19 RO 0 (R/W) 11 RS3 0 R/W 3 TS0 0 R/W *2 18 RL 0 (R/W) 10 RS2 0 R/W 2 IE 0 R/W *2 17 AM 0 (R/W) 9 RS1 0 R/W 1 TE 0 1 R/(W)* 16 AL 0 *2 (R/W)* 8 RS0 0 R/W 0 DE 0 R/W 2 Notes: 1. Only a write of 0 after a read of 1 is enabled for the TE bit. 2. DI, RO, RL, AM, AL, and DS bits are not included in some channels. The DMA channel control registers 0 to 3 (CHCR0 to CHCR3) are 32-bit read/write registers that specify operation mode, transfer method, or others in each channel. Writing to bits 31 to 21 and 7 in this register is invalid, and these bits are always read as 0. Bit 20 is only used in CHCR3. It is not used in CHCR0 to CHCR2. Consequently, writing to this bit is invalid in CHCR0 to CHCR2, and this bit is always read as 0. Bit 19 is only used in CHCR2. It is not used in CHCR0, CHCR1, and CHCR3. Consequently, writing to this bit is invalid in CHCR0, CHCR1, and CHCR3, and this bit is always read as 0. Bits 6 and 16 to 18 are only used in CHCR0 and CHCR1. They are not used in CHCR2 and CHCR3. Consequently, writing to these bits is invalid in CHCR2 and CHCR3, and these bits are always read as 0. These registers are initialized to 0 after a power-on reset. The previous values are held in standby mode. Bits 31 to 21--Reserved: These bits are always read as 0 and should only be written with 0. Rev. 5.00 Dec 12, 2005 page 387 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bit 20--Direct/Indirect Selection (DI): DI selects direct address mode operation or indirect address mode operation for a channel 3 source address. This bit is only valid in CHCR3. This bit in CHCR0 to CHCR2 is always read as 0 and should only be written with 0. When using 16-byte transfer, direct address mode must be specified. Operation is not guaranteed if indirect address mode is specified. Bit 20: DI 0 1 Description Direct address mode Indirect address mode (Initial value) Bit 19--Source Address Reload (RO): RO selects whether the source address initial value is reloaded in channel 2. This bit is only valid in CHCR2. This bit in CHCR0, CHCR1, and CHCR3 is always read as 0 and should only be written with 0. When using 16-byte transfer, this bit must be cleared to 0, specifying non-reloading. Operation is not guaranteed if reloading is specified. Bit 19: RO 0 1 Description A source address is not reloaded A source address is reloaded (Initial value) Bit 18--Request Check Level (RL): RL specifies the DRAK (acknowledge of DREQ) signal output is high active or low active. This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and should only be written with 0. Bit 18: RL 0 1 Description Low-active output of DRAK High-active output of DRAK (Initial value) Rev. 5.00 Dec 12, 2005 page 388 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bit 17--Acknowledge Mode (AM): AM specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of this bit specification. This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and should only be written with 0. Bit 17: AM 0 1 Description DACK output in read cycle DACK output in write cycle (Initial value) Bit 16--Acknowledge Level (AL): AL specifies the DACK (acknowledge) signal output is high active or low active. This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and should only be written with 0. Bit 16: AL 0 1 Description Low-active output of DACK High-active output of DACK (Initial value) Bits 15 and 14--Destination Address Mode 1, 0 (DM1 and DM0): DM1 and DM0 select whether the DMA destination address is incremented, decremented, or fixed. Bit 15: DM1 0 Bit 14: DM0 0 1 1 0 Description Fixed destination address* (Initial value) Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) Destination address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) Reserved (illegal setting) 1 Note: * This setting cannot be used to perform 16-byte transfers with a destination in X/Y memory. Rev. 5.00 Dec 12, 2005 page 389 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bits 13 and 12--Source Address Mode 1, 0 (SM1 and SM0): SM1 and SM0 select whether the DMA source address is incremented, decremented, or fixed. Bit 13: SM1 0 Bit 12: SM0 0 1 1 0 Description Fixed source address* (Initial value) Source address is incremented (+1 in 8-bit transfer, +2 in 16bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) Source address is decremented (-1 in 8-bit transfer, -2 in 16bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) Reserved (illegal setting) 1 Note: * This setting cannot be used to perform 16-byte transfers with a destination in X/Y memory. If the transfer source is specified in indirect address, specify the address (indirect address) where the address of data to be transferred is stored as data, in source address register 3 (SAR3). Specification of SAR3 increment or decrement in indirect address mode depends on SM1 and SM0 settings. In this case, however, the SAR3 increment or decrement value is +4, -4, or fixed to 0 regardless of the transfer data size specified in TS1 and TS0. Rev. 5.00 Dec 12, 2005 page 390 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bits 11 to 8--Resource 3 to 0 (RS3 to RS0): RS3 to RS0 specify which transfer requests will be sent to the DMAC. Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 0 0 0 1 Bit 8: RS0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description External request* , dual address mode 1 (Initial value) Illegal setting External request* /Single address mode 1 External address space external device with DACK External request* /Single address mode 1 External device with DACK external address space Auto request Illegal setting Illegal setting Illegal setting Select DMA request expansion* Illegal setting Illegal setting Illegal setting SCIF transmission* 2 SCIF reception* Internal A/D* 2 CMT* 2 2 3 Notes: 1. External request specification is valid only for channels 0. None of the request sources can be selected for channels 1, 2 and 3. 2. When using 16-byte transfer, the following settings must not be made: 1100 SCIF transmission 1101 SCIF reception 1110 A/D converter 1111 CMT Operation is not guaranteed if these settings are made. 3. When DMA transfer is provided with the USB function controller or SIOF, set RS3 to RS0 to 1000 and select a desired module with the CHRAR register. Rev. 5.00 Dec 12, 2005 page 391 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bit 6--DREQ Select (DS): DS selects the sampling method of the DREQ pin that is used in DREQ external request mode is detection in low level or at the falling edge. This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and should only be written with 0. Also, it should be cleared to 0 (low-level detection) if an on-chip supporting module is specified as a transfer request source in channel 0. Bit 6: DS 0 1 Description DREQ detected in low level DREQ detected at falling edge (Initial value) Bit 5--Transmit Mode (TM): TM specifies the bus mode when transferring data. Bit 5: TM 0 1 Description Cycle steal mode Burst mode (Initial value) Bits 4 and 3--Transmit Size 1, 0 (TS1 and TS0): TS1 and TS0 specify the size of data to be transferred. Bit 4: TS1 0 0 1 1 Bit 3: TS0 0 1 0 1 Description Byte size (8 bits) Word size (16 bits) Longword size (32 bits) 16-byte unit (4 longword transfers) (Initial value) Bit 2--Interrupt Enable (IE): Setting this bit to 1 generates an interrupt request when the number of times of data transfers specified with DMATCR has completed (TE = 1). Bit 2: IE 0 1 Description Interrupt request is not generated even when data transfer ends by the specified count (Initial value) Interrupt request is generated when data transfer ends by the specified count Rev. 5.00 Dec 12, 2005 page 392 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bit 1--Transfer End (TE): TE is set to 1 when data transfer ends by the count specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. Before this bit is set to 1, if data transfer ends due to an NMI interrupt, a DMAC address error, or clearing the DE bit or the DME bit in DMAOR, this bit is not set to 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. Bit 1: TE 0 1 Description Data transfer does not end by the count specified in DMATCR Data transfer ends by the specified count (Initial value) Clear condition: Writing 0 after TE = 1 read at power-on reset or manual reset Bit 0--DMAC Enable (DE): DE enables channel operation. Bit 0: DE 0 1 Description Disables channel operation Enables channel operation (Initial value) If the auto request is specified in RS3 to RS0, transfer starts when this bit is set to 1. For an external request or an on-chip module request, transfer starts if a transfer request is generated after this bit is set to 1. Clearing this bit during transfer can terminate transfer. Even if the DE bit is set, transfer is not enabled when the TE bit is 1, the DME bit in DMAOR is 0, or the NMIF bit or AE bit in DMAOR is 1. Rev. 5.00 Dec 12, 2005 page 393 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.2.5 DMA Channel Request Assign Register (CHRAR ) The DMA channel request assign register (CHRAR) is a 16-bit read/write registers that assign requests from USBF or SIOF to each DMA channel, to each expanded DMA. It is initialized to 0 at power-on reset, or in hardware standby mode or software standby mode. These register values are initialized to 0s after a power-on reset. The previous value is held in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15,14,13,12 CH3RID3 to CH0RID0 0 R/W 7,6,5,4 CH1RID3 to CH1RID0 0 R/W 11,10,9,8 CH2RID3 to CH2RID0 0 R/W 3,2,1,0 CH0RID3 to CH0RID0 0 R/W Bits 15 to 12 --DMA Channel 3 Request Assign 3 to 0 (CH3RID3 to CH3RID0): These bits select DMA requests from DMA channel 3. Bits 15 to 12: CH3RID3 to CH3RID0 0000 0001 0010 1001 1010 Description Unused (Initial value) USBF (USB function) reception requests to the DMA are selected from channel 3 USBF (USB function) transmission requests to the DMA are selected from channel 3 SIOF reception requests to the DMA are selected from channel 3 SIOF transmission requests to the DMA are selected from channel 3 Rev. 5.00 Dec 12, 2005 page 394 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bits 11 to 8 -- DMA Channel 2 Request Assign 3 to 0 (CH2RID3 to CH2RID0): These bits select DMA requests from DMA channel 2. Bits 11 to 8: CH2RID3 to CH2RID0 0000 0001 0010 1001 1010 Description Unused (Initial value) USBF (USB function) reception requests to the DMA are selected from channel 2 USBF (USB function) transmission requests to the DMA are selected from channel 2 SIOF reception requests to the DMA are selected from channel 2 SIOF transmission requests to the DMA are selected from channel 2 Bits 7 to 4-- DMA Channel 1 Request Assign 3 to 0 (CH1RID3 to CH1RID0): These bits select DMA requests from DMA channel 1. Bits 7 to 4: CH1RID3 to CH1RID0 0000 0001 0010 1001 1010 Description Unused (Initial value) USBF (USB function) reception requests to the DMA are selected from channel 1 USBF (USB function) transmission requests to the DMA are selected from channel 1 SIOF reception requests to the DMA are selected from channel 1 SIOF transmission requests to the DMA are selected from channel 1 Bits 3 to 0-- DMA Channel 0 Request Assign 3 to 0 (CH0RID3 to CH0RID0): These bits select DMA requests from DMA channel 0. Bits 3 to 0: CH0RID3 to CH0RID0 0000 0001 0010 1001 1010 Description Unused (Initial value) USBF (USB function) reception requests to the DMA are selected from channel 0 USBF (USB function) transmission requests to the DMA are selected from channel 0 SIOF reception requests to the DMA are selected from channel 0 SIOF transmission requests to the DMA are selected from channel 0 Rev. 5.00 Dec 12, 2005 page 395 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.2.6 DMA Operation Register (DMAOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 AE 0 R/(W)* 9 PR1 0 R/W 1 NMIF 0 R/(W)* 8 PR0 0 R/W 0 DME 0 R/W Note: * Only a write of 0 after a read of 1 is enabled for the AE and NMIF bits. The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMAC transfer mode. This register is initialized to 0 by a power-on reset. The previous values are held in standby mode. Bits 15 to 10--Reserved: These bits are always read as 0 and should only be written with 0. Bits 9 and 8--Priority Mode 1, 0 (PR1 and PR0): PR1 and PR0 select the priority level between channels when transfer requests are generated for multiple channels simultaneously. Bit 9: PR1 0 1 Bit 8: PR0 0 1 0 1 Description CH0 > CH1 > CH2 > CH3 CH0 > CH2 > CH3 > CH1 CH2 > CH0 > CH1 > CH3 Round-robin (Initial value) Bits 7 to 3--Reserved: These bits are always read as 0 and should only be written with 0. Rev. 5.00 Dec 12, 2005 page 396 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bit 2--Address Error Flag (AE): AE indicates that an address error occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing of 0 after reading of 1. Bit 2: AE 0 Description No DMAC address error. DMA transfer is enabled. By a power-on reset By a manual reset 1 DMAC address error. DMA transfer is disabled. Setting condition: When a DMAC address error occurred (Initial value) Clear conditions: When this bit is written with 0 after it is read as 1 Bit 1--NMI Flag (NMIF): NMIF indicates that an NMI interrupt occurred. This bit is set both in operating state and in halt state. The CPU cannot write 1 to this bit. This bit can only be cleared by writing of 0 after reading of 1. Bit 1: NMIF 0 Description No NMI input. DMA transfer is enabled. By a power-on reset By a manual reset 1 NMI input. DMA transfer is disabled. Setting condition: When an NMI interrupt is generated (Initial value) Clear conditions: When this bit is written with 0 after it is read as 1 Bit 0--DMA Master Enable (DME): DME enables or disables DMA transfer for all channels. If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is enabled in the corresponding channel. If this bit is cleared during transfer, transfer in all the channels can be terminated. Even if the DME bit is set, transfer is not enabled when the TE bit is 1 or the DE bit is 0 in CHCR, or the NMIF bit is 1 in DMAOR. Bit 0: DME 0 1 Description Disable DMA transfer for all channels Enable DMA transfer for all channels (Initial value) Rev. 5.00 Dec 12, 2005 page 397 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.3 Operation When a DMA transfer request is generated, the DMAC starts the transfer according to the predetermined channel priority order. When a transfer end condition is satisfied, it ends the transfer. Three types of transfer requests can be, auto request, external request, and on-chip module request. For the dual address mode, the direct address transfer mode and indirect address transfer mode are supported. For the bus mode, the burst mode or the cycle steal mode can be selected. 14.3.1 DMA Transfer Flow When transfer conditions have been set to the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR), the DMAC transfers data according to the following procedure: 1. Checks that transfer is enabled (DE = 1, DME = 1, AE = 0, TE = 0, NMIF = 0) 2. When transfer is enabled and a transfer request is generated, the DMAC transfers 1 transfer unit of data (set with the TS0 and TS1 bits). In auto request mode, the transfer operation begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented on each transfer. The actual transfer flows vary according to the address mode and bus mode. 3. When the specified number of transfers have been completed (when DMATCR reaches 0), the transfer operation ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an NMI interrupt is generated, the transfer operation is aborted. The transfer operation is also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0. Figure 14.2 shows a flowchart of this procedure. Rev. 5.00 Dec 12, 2005 page 398 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and AE, NMIF, TE = 0? Yes Transfer request occurs?*1 Yes No No *2 *3 Transfer (1 transfer unit); DMATCRD1 DMATCR, SAR and DAR updated Bus mode, transfer request mode, DREQ detection selection system DMATCR = 0? Yes No Does AE = 1 or NMIF = 1 or DE = 0 or DME = 0? Yes Transfer aborted No DEI interrupt request (when IE = 1) Does AE = 1 or NMIF = 1 or DE = 0 or DME = 0? Yes Transfer end No Normal end Notes: 1. In auto-request mode, transfer begins when AE, NMIF and TE are all 0 and the DE and DME bits are set to 1. 2. DREQ = level detection in burst mode (external request) or cycle-steal mode. 3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode. Figure 14.2 DMAC Transfer Flowchart Rev. 5.00 Dec 12, 2005 page 399 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip supporting modules that are neither the source nor the destination. There are three types of transfer requests, an auto request, an external request and an on-chip module request. The request mode is selected with the RS3 to RS0 bits in the DMA channel control registers 0 to 3 (CHCR0 to CHCR3). Auto-Request Mode: When no transfer request signal is input from an external source, such as transfer between memories or between memory and an on-chip supporting module on which a transfer request is disabled, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR0 to CHCR3 and the DME bit in DMAOR are set to 1, a transfer is started. At this time, the TE bits in CHCR0 to CHCR3 and the NMIF bit in DMAOR should be all 0. External Request Mode: A transfer is started by the transfer request signal (DREQ) from an external device. Choose one of the modes shown in table 14.3 according to the application system. If DREQ is input when the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0), a DMA transfer starts. Select whether DREQ is detected on the falling edge or low level with the DS bit in CHCR0 (level detection when DS = 0, edge detection when DS = 1). The source of the transfer request does not have to be the data transfer source or destination. Table 14.3 Selecting External Request Modes with the RS Bits RS3 0 RS2 0 RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Source Arbitrary* External memory, memory-mapped external device External device with DACK Destination Arbitrary* External device with DACK External memory, memory-mapped external device 1 Note: * External memory, memory-mapped external device, on-chip memory, on-chip supporting module (excluding DMAC, UBC, and BSC) On-Chip Module Request Mode: A transfer is started by the transfer request signal (interrupt request signal) from an on-chip supporting module. This mode cannot be set in case of 16-byte transfer. There are eight types of transfer request signals, a receive data full interrupt (RXI) and a transmit data empty interrupt (TXI) from the serial communication interface (SCIF), an A/D conversion end interrupt (ADI) from the A/D converter, an compare-match timer interrupt (CMI) Rev. 5.00 Dec 12, 2005 page 400 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) from CMT, a transmit request (TDREQ) and a receive request (RDREQ) from SIOR, and a transmit request (DREQN1) and a receive request (DREQN0) from USBF. TDREQ, RDREQ, DREQN1, and DREQN0 are supported for expansion. When the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, and NMIF = 0) in this mode, a transfer is started by the transfer request signal input. The source of the transfer request does not have to be the data transfer source or destination. When RXI2 is set as a transfer request, however, the transfer source must be the SCIF's receive data register (RDR2). Likewise, when TXI2 is set as a transfer request, the transfer source must be the SCIF's transmit data register (TDR2). In addition, when the transfer requester is the A/D converter, the data transfer source must be the A/D data register (ADDR). Table 14.4 Selection of On-Chip Module Request Modes Using RS3 to RS0 Bits RS3 1 RS2 0 RS1 0 RS0 0 DMA Transfer Request Source Expansion USBF receiver USBF transmitter SIOF receiver SIOF transmitter 1 0 0 SCIF transmitter DMA Transfer Request Signal DREQN[0] (DMA transfer request output) DREQN[1] (DMA transfer request output) RDREQ (receive-data transfer request) TDRQ (transmit-data transfer request) Source EPDR1 Destination Bus Mode Arbitrary* Cycle steal Arbitrary* EPDR2 Cycle steal SIRDR Arbitrary* Cycle steal Arbitrary* SITDR Cycle steal TXI2 Arbitrary* TDR2 (SCIF transmit data empty interrupt) RXI2 (SCIF receive data full interrupt) ADI (A/D conversion end interrupt) CMI (Compare-match timer interrupt) RDR2 Arbitrary* Cycle steal 0 1 SCIF receiver Cycle steal 1 0 A/D converter ADDR Arbitrary* Cycle steal 1 1 CMT Arbitrary* Arbitrary* Burst/ cycle steal Note: * External memory, memory-mapped external device, on-chip supporting module (excluding DMAC, BSC, UBC) Rev. 5.00 Dec 12, 2005 page 401 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) In order to output a transfer request from an on-chip supporting module, set the corresponding interrupt enable bit for outputting the interrupt signal. When the interrupt request signal from an on-chip supporting module is used as a DMA transfer request signal, an interrupt is not generated to the CPU. The DMA transfer request signals shown in table 14.4 are automatically canceled when the corresponding DMA transfer is completed. This operation is provided at the first transfer in cycle steal mode, and at the last transfer in burst mode. 14.3.3 Channel Priority When the DMAC receives multiple transfer requests simultaneously, it provides transfer operation according to a specified priority order. The fixed mode or round-robin mode can be selected for the channel priority with the PR1 and PR0 bit in the DMA operation register (DMAOR). Fixed Mode: The channel priority is fixed. There are three kinds of orders as follows: CH0 > CH1 > CH2 > CH3 CH0 > CH2 > CH3 > CH1 CH2 > CH0 > CH1 > CH3 The priority is selected by the PR1 and PR0 bits in the DMA operation register (DMAOR). Round-Robin Mode: The priority order is rotated each time one transfer unit (word, byte, or longword) of data has been transferred. The channel on which the transfer was just finished is located at the lowest in priority. The round-robin mode operation is shown in figure 14.3. The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after a reset. Rev. 5.00 Dec 12, 2005 page 402 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 Channel 0 becomes bottom priority Priority order afrer transfer CH1 > CH2 > CH3 > CH0 (2) When channel 1 transfers Channel 0 becomes bottom priority. The priority of channel 0, which was higher than channel 3, is also shifted. Initial priority order CH0 > CH1 > CH2 > CH3 Priority order afrer transfer CH2 > CH3 > CH0 > CH1 (3) When channel 2 transfers Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately Priority order CH3 > CH0 > CH1 > CH2 after there is a request to transfer afrer transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 0 and 3, which were Post-transfer priority order higher than channel 1, are also when there is an CH2 > CH3 > CH0 > CH1 shifted. immediate transfer request to channel 1 only CH0 > CH1 > CH2 > CH3 Initial priority order (4) When channel 3 transfers Priority order afrer transfer Priority order afrer transfer Initial priority order CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3 Figure 14.3 Operation in Round-Robin Mode Rev. 5.00 Dec 12, 2005 page 403 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Figure 14.4 shows how the priority order changes when transfer requests for channel 0 and channel 3 are generated simultaneously and a transfer request for channel 1 is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously for channels 0 and 3. 2. Channel 0 has the higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 has the lowest priority. 5. At this time, channel 1 has the higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 has the lowest priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority order so that channel 3 has the lowest priority. Transfer request Waiting channel(s) DMAC operation Channel priority (1) Channels 0 and 3 (3) Channel 1 3 (2) Channel 0 transfer start Priority order changes 0>1>2>3 1,3 (4) Channel 0 transfer ends (5) Channel 1 transfer starts 1>2>3>0 3 (6) Channel 1 transfer ends Priority order changes 2>3>0>1 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 0>1>2>3 Figure 14.4 Channel Priority Order in Round-Robin Mode Rev. 5.00 Dec 12, 2005 page 404 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 14.5. The dual address mode comprises the direct address mode and indirect address mode. In the direct address mode, an output address value is the data transfer target address. In the indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address. The data transfer timing differs depending on the bus mode. The bus mode comprises the cycle steal mode and burst mode. Table 14.5 DMA Transfers Destination External Device with DACK MemoryMapped External Device Dual, single Dual Dual Dual Dual On-Chip Supporting Module Source External device with DACK External memory Memory-mapped external device On-chip supporting module X/Y memory External Memory XY Memory Not available Dual, single Dual, single Dual, single Dual Dual Not available Not available Dual Dual Dual Dual Dual Dual Dual Dual Not available Dual Not available Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. The dual address mode includes the direct address mode and the indirect address mode. 4. 16-byte transfer is not available for on-chip supporting modules. Address Mode: * Dual Address Mode In the dual address mode, the transfer source and destination are accessed by addresses. Both external and internal addresses can be used for the transfer source or destination. The dual address mode consists of the direct address transfer mode (1) and indirect address transfer mode (2). Rev. 5.00 Dec 12, 2005 page 405 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) (1) Direct address transfer mode DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 14.5, data is read from one external memory to the DMAC in a data read cycle, and then that data is written to the other external memory in a write cycle. Figures 14.6 to 14.8 show examples of this operation timing DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer Data is read from the transfer source module using the SAR value as the address, and the read data is stored in the DMAC temporarily. First bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The value stored in the DMAC is written to the transfer destination module using the DAR value as the address. Second bus cycle Figure 14.5 Operation in Direct Address Mode Rev. 5.00 Dec 12, 2005 page 406 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) CKIO Transfer source address A25 to A0 Transfer destination address CSn D31 to D0 RD WEn DACKn Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: When DACK is output in a read cycle during transfer between external memories, the output timing is the same as that of CSn. Figure 14.6 Example of DMA Transfer Timing in the Direct Address Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) Rev. 5.00 Dec 12, 2005 page 407 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) CKIO A25 to A0 CSn D31 to D0 RD WEm DACK Data read cycle Transfer +4 source address +8 +12 Transfer +4 destination address +8 +12 (1st cycle) (2nd cycle) Note: When DACK is output in a read cycle during transfer between external memories, the output timing is the same as that of CSn. Figure 14.7 Example of DMA Transfer Timing in the Direct Address Mode (16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) CKIO A25 to A0 CSn D31 to D0 RAS CAS RD/WR DACK Data read cycle (1st cycle) Data write cycle (2nd cycle) Transfer source address Transfer destination address +4 +8 +12 Note: When DACK is output in a read cycle during transfer between external memories, the output timing is the same as that of CSn. Figure 14.8 Example of DMA Transfer Timing in the Direct Address Mode (16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary Memory) Rev. 5.00 Dec 12, 2005 page 408 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) (2) In the indirect address transfer mode The address of the memory in which data to be transferred is stored is specified in the transfer source address register (SAR3) in the DMAC. 16-byte transfer is not provided in this mode. The address value specified in the transfer source address register in the DMAC is read first, and this value is temporarily stored in the DMAC. Next, the read value is output as an address, and data on that address is stored in in the DMAC again. Then, the value read afterwards is written to the address specified by the transfer destination address register; thus one DMA transfer is completed. Figure 14.9 shows an example of this operation. In this example, the transfer destination, transfer source, and storage destination of the indirect address are all in external memories, and the transfer data size is 16 or 8 bits. Figure 14.10 shows an example of the transfer timing. In this mode, one NOP cycle (CK1 cycle shown in figure 14.10) is required to output data which was read as an indirect address to an address bus. For a 32-bit data transfer, third and fourth bus cycles shown in figure 14.10 are required twice for each; a total of six bus cycles and one NOP cycle are required. Rev. 5.00 Dec 12, 2005 page 409 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) SAR3 Address bus Memory D M A C DAR3 Temporary buffer Data buffer Data bus Transfer source module Transfer destination module Data is read from memory using the SAR3 value as the data address, and the read data is stored in the temporary buffer. The read data must be a 32-bit value because it is used as an address. Two bus cycles are required if a 16-bit data bus is used to connect to an external device. First and second bus cycles SAR3 Memory Address bus D M A C DAR3 Temporary buffer Data buffer Data bus Transfer source module Transfer destination module Data is read from the source module using the temporary buffer value as the address, and the read data is transferred to the data buffer. Third bus cycle SAR3 D M A C Memory Address bus DAR3 Temporary buffer Data buffer Data bus Transfer source module Transfer destination module The data buffer value is written to the destination module using the DAR3 value as the destination address. Fourth bus cycle Note: The above description uses the memory, transfer source module, or transfer destination module; in practice, any module can be connected in the addressing space. Figure 14.9 Operation in Indirect Address Mode (When the External Memory Space is Set to 16-bit Width) Rev. 5.00 Dec 12, 2005 page 410 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) CK A25 to A0 Transfer source address (H) Transfer source address (L) NOP Indirect address Transfer destination address CSn D31 to D0 Indirect address (H) Indirect address (L) Transfer data Indirect address Transfer data Internal address bus Transfer source address*1 NOP Internal data bus DMAC indirect address buffer Transfer source address*2 Transfer data Transfer data Indirect address DMAC data buffer Transfer data RD WEn Address read cycle (1st) (2nd) NOP cycle Data read cycle (3rd) Data write cycle (4th) Notes: 1. The internal address bus value does not change, and controlled by the port. 2. The DMAC does not fetch the value until 32-bit data is output to the internal data bus. Transfer between external memories (external memories is 16-bit bus width) Figure 14.10 Example of Transfer Timing in Indirect Address Mode (Transfer between External Memories, External Memory with 16-bit Width) Rev. 5.00 Dec 12, 2005 page 411 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) * Single Address Mode The single address mode is used when transfer is performed between external devices including external memories, one of which is accessed (selected) by the DACK signal and the other of which is accessed by address. In this mode, the DMAC outputs the transfer request acknowledge signal DACK to one external device, and simultaneously outputs an address to the other device; thus DMA transfer is performed in one bus cycle. An example of transfer between an external memory and an external device with DACK is shown in figure 14.11. The external device outputs data to a data bus and the data is written to the external memory in a single bus cycle. External address bus SH7727 DMAC External memory External data bus External device with DACK DACK DREQ Data flow Figure 14.11 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and an external memory. In both cases, only the external request signal (DREQ) is used as a transfer request. Figures 14.12 and 14.13 show examples of the DMA transfer timing in single address mode. Rev. 5.00 Dec 12, 2005 page 412 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) CK A25 to A0 CSn WE D31 to D0 DACKn BS (a) External device with DACK CK A25 to A0 CSn RD D31 to D0 DACKn BS Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK Address output to external memory space external memory space (ordinary memory) Write strobe signal to external memory space Address output to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (b) External memory space external device with DACK (active-low) Figure 14.12 Example of DMA Transfer Timing in Single Address Mode Rev. 5.00 Dec 12, 2005 page 413 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) CKIO A25 to A0 CSn D31 to D0 RD WEn Transfer source address +4 +8 +12 DACKn Figure 14.13 Example of DMA Transfer Timing in Single Address Mode (External Memory Space (Ordinary Memory) External Device with DACK) Bus Modes: There are two types of bus modes, cycle steal mode and burst mode. Select the mode in the TM bits in CHCR0 to CHCR3. * Cycle-Steal Mode In the cycle-steal mode, the bus right is moved to another bus master after one transfer unit (byte, word, longword, or 16-byte unit) of DMA transfer. If another transfer request occurs after the bus right moving, the bus right are re-moved to the DMAC. Then, the DMAC performs transfer for one transfer unit and releases the bus right again. This operation is repeated until the transfer end condition is satisfied. In the cycle-steal mode, transfer areas are not affected by settings of the transfer request source, transfer source, and transfer destination. Figure 14.14 shows an example of the DMA transfer timing in the cycle steal mode. In this example, the following conditions are set: * * Dual address mode DREQ level detection Rev. 5.00 Dec 12, 2005 page 414 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) DREQ Bus right returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC CPU Read Write CPU Figure 14.14 Transfer Example in Cycle-Steal Mode * Burst Mode Once the DMAC obtains the bus right, the transfer is continued until the transfer end condition is satisfied. However, when the DREQ pin is driven high in the external request mode with low level detection of the DREQ pin, the bus right is passed to the other bus master after the DMA transfer request that has already been accepted ends, even if the transfer end condition has not been satisfied. The burst mode cannot be used when the transfer request source is set to the serial communications interface with FIFO (SCIF). Figure 14.15 shows a timing of the DMA transfer operation in the burst mode. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read Write Read Write Read Write CPU Figure 14.15 Example of Transfer in Burst Mode Relationship between Request Mode and Bus Mode: Table 14.6 shows the relationship between request mode and bus mode for each combination of DMA transfer areas. Rev. 5.00 Dec 12, 2005 page 415 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Table 14.6 Relationship of Request Modes and Bus Modes Address Mode Transfer Areas Dual External device with DACK and external memory External device with DACK and memory-mapped external device External memory and external memory External memory and memorymapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip supporting module Memory-mapped external device and on-chip supporting module On-chip supporting module and onchip supporting module X/Y memory and X/Y memory X/Y memory and memory-mapped external device X/Y memory and on-chip supporting module X/Y memory and external memory Single External device with DACK and external memory External device with DACK and memory-mapped external device Request Mode External External All* All* All* All* All* All* All All* All* All External External 1 1 Bus Mode B/C B/C B/C B/C B/C B/C* B/C* B/C* B/C B/C B/C* B/C B/C B/C 3 3 Transfer Size (bits) 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32* 8/16/32* 8/16/32* 4 Usable Channels 0 0 0-3* 0-3* 0-3* 0-3* 0-3* 0-3* 0-3 0-3 0-3 0-3 0 0 5 1 5 1 5 2 5 2 3 4 5 2 3 4 5 8/16/32/128 8/16/32/128 8/16/32 8/16/32/128 8/16/32/128 8/16/32/128 2 B: Burst C: Cycle steal Notes: 1. External requests, auto requests and on-chip supporting module (CMT) requests are all available. 2. External requests, auto requests and on-chip supporting module requests are all available. When the SIOF, USBF, SCIF, or A/D converter is the transfer request source, the transfer destination or transfer source must be also the SIOF, USBF, SCIF, or A/D converter, respectively. 3. The SIOF, USBF, SCIF, or A/D converter can be specified for the transfer request source in the cycle-steal mode only. 4. The access size permitted when the transfer destination or source is an on-chip supporting module register. 5. If the transfer request is an external request, only channel 0 is available. Rev. 5.00 Dec 12, 2005 page 416 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority Order: For example, when channel 1 provides transfer operation in burst mode and then a transfer request to channel 0 with the higher priority is generated, the transfer of channel 0 will begin immediately. At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will be continued after the channel 0 transfer has completely finished, even if channel 0 is set to the cycle steal mode or burst mode. If the round-robin mode is selected, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, even if channel 0 is set to the cycle steal mode or burst mode. The bus is moved between the two in the order channel 1, channel 0, channel 1, channel 0. Even if the fixed mode or in the round-robin mode is selected, the bus is not passed to the CPU since channel 1 is in the burst mode. Figure 14.16 shows an example of operation in the roundrobin mode. CPU DMAC CH1 DMAC CH1 DMAC CH0 CH0 DMAC CH1 CH1 DMAC CH0 CH0 DMAC CH1 DMAC CH1 CPU CPU DMAC CH1 Burst mode Round-robin mode in DMAC CH0 and CH1 DMAC CH1 Burst mode CPU Priority: Round-robin mode CH0: Cycle-steal mode CH1: Burst mode Figure 14.16 Bus State in Multiple Channel Operation Rev. 5.00 Dec 12, 2005 page 417 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 12, Bus State Controller (BSC). DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled with the clock pulse (CKIO) falling edge detection or low level detection. When a DREQ input is detected, a DMAC bus cycle is generated and DMA transfer starts three or more states later. The second and subsequent DREQ sampling operations are started two cycles after the first sample. Operation * Cycle-Steal Mode In cycle-steal mode, the DREQ sampling timing does not change according to the DREQ detection method, the level detection or edge detection. For example, as shown in figure 14.17 (cycle-steal mode, level detection), DMA transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. If DREQ is not detected at this time, sampling is performed in each subsequent cycle. Thus, DREQ sampling is performed one step in advance. The third sampling operation is not performed until the idle cycle following the end of the first DMA transfer. The above operation is performed continuously for the desired CPU transfer cycles or DMA transfer cycles, as shown in figures 14.18 and 14.19. Figures 14.17 and 14.18 show examples in which DACK is output in a read and in a write, respectively. In both cases, DACK is output for the same period as CSn. Figure 14.20 shows an example in which sampling is executed in all subsequent cycles when DREQ cannot be detected. Figure 14.21 shows an example of operation in cycle steal mode with the edge detection. Rev. 5.00 Dec 12, 2005 page 418 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) * Burst Mode, Level Detection In the case of burst mode with level detection, the DREQ sampling timing is the same as in the cycle-steal mode. For example, as shown in figure 14.22, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. Subsequent sampling operations are performed in the idle cycle following the end of the DMA transfer cycle. In the burst mode, also, the DACK output period is the same as that in the cycle-steal mode. * Burst Mode, Edge Detection In the case of burst mode with edge detection, DREQ sampling is performed only once. For example, as shown in figure 14.23, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. After this, DMAC transfer is executed continuously until the number of data transfers set in the DMATCR register have been completed. DREQ is not sampled during this operation. To restart DMA transfer after it has been suspended by an NMI, first clear NMIF, then input an edge request again. In the burst mode, also, the DACK output period is the same as that in the cycle-steal mode. Rev. 5.00 Dec 12, 2005 page 419 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 3rd sampling 2nd sampling 1st sampling Bus cycle CKIO DREQ DRAK CPU DACK Figure 14.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) Rev. 5.00 Dec 12, 2005 page 420 of 1034 REJ09B0254-0500 DMAC(R) DMAC(W) CPU DMAC(R) DMAC(W) Section 14 Direct Memory Access Controller (DMAC) 3rd sampling 2nd sampling 1st sampling CKIO DREQ DRAK CPU Bus cycle DMAC(R) DMAC(W) CPU DMAC(R) Figure 14.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) Rev. 5.00 Dec 12, 2005 page 421 of 1034 REJ09B0254-0500 DACK Section 14 Direct Memory Access Controller (DMAC) 3rd sampling 1st sampling 2nd sampling CKIO DREQ Bus cycle CPU DRAK (High output) DACK (RD output) Figure 14.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) Rev. 5.00 Dec 12, 2005 page 422 of 1034 REJ09B0254-0500 DMAC(R) DMAC(W) CPU DMAC(W) 2nd sampling is performed, but since DREQ is high, per-cycle sampling starts 3rd sampling is performed, but since DREQ is high, per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling CKIO DREQ DRAK Bus cycle CPU DMAC(R) DMAC(W) CPU DMAC(R) DMAC(W) CPU Figure 14.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) Section 14 Direct Memory Access Controller (DMAC) Rev. 5.00 Dec 12, 2005 page 423 of 1034 REJ09B0254-0500 DACK (RD output) 3rd sampling is performed, but since there is no DREQ falling edge, per-cycle sampling starts 2nd sampling is performed, but since there is no DREQ falling edge, per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling Rev. 5.00 Dec 12, 2005 page 424 of 1034 REJ09B0254-0500 High High High High DMAC(R) DMAC(W) CPU DMAC(R) DMAC(W) CPU CKIO DREQ Section 14 Direct Memory Access Controller (DMAC) DRAK Bus cycle CPU DACK (RD output) Figure 14.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) Note: When a DREQ falling edge is detected, DREQ must be high for at least one cycle before the sampling point. Section 14 Direct Memory Access Controller (DMAC) 3rd sampling 1st sampling 2nd sampling Bus cycle CKIO DREQ DRAK CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) Figure 14.22 Burst Mode, Level Input Rev. 5.00 Dec 12, 2005 page 425 of 1034 REJ09B0254-0500 DACK Section 14 Direct Memory Access Controller (DMAC) 1st sampling CKIO DREQ DRAK CPU Bus cycle DACK Figure 14.23 Burst Mode, Edge Input Rev. 5.00 Dec 12, 2005 page 426 of 1034 REJ09B0254-0500 DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) Section 14 Direct Memory Access Controller (DMAC) 14.3.6 Source Address Reload Function Channel 2 includes a reload function, in which the value set in the source address register (SAR2) is restored every four transfers when the RO bit in CHCR2 is set to 1. This function cannot be used with the 16-byte transfer. Figure 14.24 shows this operation. Figure 14.25 shows a timing chart of the source address reload function with the following conditions: burst mode, auto request, 16-bit transfer data size, SAR2 count-up, DAR2 fixed, reload function on, and usage of only channel 2. DMAC DMAC control RO bit = 1 CHCR2 Reload control Reload signal SAR2 (initial value) Reload signal 4 time count SAR2 Figure 14.24 Source Address Reload Function Diagram Rev. 5.00 Dec 12, 2005 page 427 of 1034 REJ09B0254-0500 Address bus Transfer request Count signal DMATCR2 Section 14 Direct Memory Access Controller (DMAC) CK Internal address bus Internal data bus SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2 SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data First transfer of channel 2 SAR2 output DAR2 output Second transfer SAR2+2 output DAR2 output Third transfer SAR2+4 output DAR2 output Fourth transfer SAR2+6 output DAR2 output Fifth transfer SAR2 reload SAR2 output DAR2 output Figure 14.25 Timing Chart of Source Address Reload Function The reload function can be used for the 8-, 16- and 32-bit data transfer. DMATCR2, which specifies a transfer count, is incremented by 1 each time a transfer ends regardless of the reload function setting. Consequently, be sure to specify the value multiple of four in DMATCR2 when the reload function is on. If other values are specified, correct operation is not guaranteed. The counters that count transfers of four times for the reload function are reset by clearing the DME bit in DMAOR or the DE bit in CHCR2, by setting the transfer end flag (TE bit in CHCR2), by inputting an NMI, besides by a reset or in standby mode. However, the SAR2, DAR2, DMATCR2 registers are not reset. Therefore, the above reset source is generated, some counters are initialized but some are not in the DMAC, which may cause a malfunction when the DMAC is restarted. To avoid this problem, if a reset source except the TE bit setting is generated when the reload function is used, set SAR2, DAR2, and DMATCR2 again. Rev. 5.00 Dec 12, 2005 page 428 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.3.7 DMA Transfer Ending DMA transfer ending conditions to terminate transfer differ according to the ending types, individual channel ending and all channel ending. At a transfer end, the following conditions are applied except the case when the DMA transfer count register (DMATCR) value reaches 0. (a) Cycle-steal mode (external request, internal request, and auto request) When a transfer ending condition is satisfied, DMAC transfer request acceptance is suspended. The DMAC stops operation after completing the number of transfers that has accepted before the ending conditions are satisfied. In the cycle-steal mode, the same operation is provided regardless of the transfer request detection method; the level detection or the edge detection. (b) Burst mode, edge detection (external request, internal request, and auto request) The timing of DMAC operation ending after an ending condition is satisfied differs from that in cycle steal mode. In the edge detection in the burst mode, though only one transfer request is generated at the DMAC start-up, a stop request sampling is performed in the same timing as a transfer request sampling in the cycle-steal mode. As a result, the period when a stop request is not sampled is regarded as the period when a transfer request is generated, and after performing the DMA transfer for this period, the DMAC stops operation. (c) Burst mode, level detection (external request) Same as described in (a). (d) Bus timing when transfers are suspended Transfer is suspended when one transfer ends. Even if a transfer ending condition is satisfied during a read with the direct address transfer in the dual address mode, the subsequent write process is executed, and after the transfer in (a) to (c) above has been executed, DMAC operation suspends. Rev. 5.00 Dec 12, 2005 page 429 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Conditions for Individual-Channel Ending: When one of the following conditions is satisfied, transfer in the corresponding channel ends. When the value in the DMA transfer count register (DMATCR) is 0 When the DE bit in CHCR is cleared to 0. * When DMATCR is 0: When the DMATCR value reaches 0, the DMA transfer in the corresponding channel ends and the transfer end flag bit (TE) in CHCR is set. If the IE (interrupt enable) bit is set at this time, a DMAC interrupt (DEI) is requested to the CPU. The conditions described in (a) to (d) above are not applied for this transfer ending. * When DE in CHCR is 0: When the DE bit in CHCR is cleared, the DMA transfer in the corresponding channel stops. The conditions described in (a) to (d) above are not applied for this transfer ending. Conditions for All-Channel Ending: When one of the following conditions is satisfied, transfer in all channels end simultaneously. When the NMIF (NMI flag) bit in DMAOR is set to 1 When the DME bit in DMAOR is cleared to 0. * When the NMIF bit in DMAOR is set to 1: When an NMI interrupt occurs, the NMIF bit in DMAOR is set to 1 and all channels stop their transfers according to the conditions in (a) to (d) described above, and pass the bus right to another bus master. Consequently, even if the NMI bit is set to 1 during transfer, the SAR, DAR, DMATCR are updated. Then the TE bit is not set. To resume the transfer after the NMI interrupt exception handling, clear the NMIF bit to 0. At this time, for the channels that should not be restarted, clear the corresponding DE bit in CHCR. * When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR forcibly aborts the transfers on all channels. Then the TE bit is not set. All channels abort their transfers according to the conditions (a) to (d) described in section 14.3.7, DMAC Transfer Ending, in the same way as that at the generation of an address error by the DMAC or NMI interrupt generation. In this case, the values in SAR, DAR, and DMATCR are also updated. Rev. 5.00 Dec 12, 2005 page 430 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.4 14.4.1 Compare-Match Timer (CMT) Overview The DMAC has an on-chip compare-match timer (CMT) to generate DMA transfer requests. The CMT is 16-bit counter. Features The CMT has the following features: * Four types of counter input clocks can be selected One of four internal clocks (P/4, P/8, P/16, and P/64) can be selected. * Generates a DMA transfer request when a compare-match occurs. Block Diagram Figure 14.26 shows a CMT block diagram. P/4 P/8 P/16 P/64 CMT Control circuit Clock selection Comparator CMCOR0 CMCSR0 CMCNT0 CMSTR Module bus Bus interface Internal bus CMSTR: CMCSR0: CMCOR0: CMCNT0: Compare match timer start register Compare match timer control/status register 0 Compare match timer constant register 0 Compare match timer counter 0 Figure 14.26 CMT Block Diagram Rev. 5.00 Dec 12, 2005 page 431 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Register Configuration Table 14.7 summarizes the CMT register configuration. Table 14.7 Register Configuration Name Compare-match timer start register Compare-match timer control/status register 0 Compare-match counter 0 Compare-match constant register Abbreviation CMSTR CMCSR0 CMCNT0 CMCOR0 R/W R/(W) R/(W)* R/W R/W 1 Initial Value H'0000 H'0000 H'0000 H'FFFF Address Access Size (Bits) 8, 16, 32 H'04000070 2 (H'A4000070)* H'04000072 8, 16, 32 2 (H'A4000072)* H'04000074 8, 16, 32 2 (H'A4000074)* H'04000076 8, 16, 32 2 (H'A4000076)* Notes: 1. Only a 0 can be written to CMF bits in CMCSR0, to clear the flag. 2. When the address conversion by the MMU is not provided, use the address in parentheses. 14.4.2 Register Descriptions Compare-Match Timer Start Register (CMSTR) The compare-match timer start register (CMSTR) is a 16-bit register that selects whether comparematch counter 0 (CMCNT0) is operated or halted. CMSTR is initialized to H'0000 by a reset, but it retains its previous values in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R/W 8 -- 0 R 0 STR0 0 R/W Bits 15 to 2--Reserved: These bits are always read as 0 and should only be written with 0. Rev. 5.00 Dec 12, 2005 page 432 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bit 1--Reserved: This is a readable/writable bit, but the write value should be always be 0. Bit 0--Count start 0 (STR0): Selects whether the compare-match timer counter 0 is operated or halted. Bit 0: STR0 0 1 Description CMCNT0 count operation is halted CMCNT0 count operation is provided (Initial value) Compare-Match Timer Control/Status Register 0 (CMCSR0) The compare-match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates a compare-match occurrence and sets the incrementation clock. CMCSR0 is initialized to H'0000 by a reset, but it retains its previous values in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 CMF 0 R/(W)* 14 -- 0 R 6 -- 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 CKS1 0 R/W 8 -- 0 R 0 CKS0 0 R/W Note: * Only a 0 can be written, to clear the flag. Bits 15 to 8 and 5 to 2--Reserved: These bits are always read as 0and should only be written with 0. Bit 7--Compare-Match Flag (CMF): This flag indicates that a compare-match of the comparematch timer counter 0 (CMCNT0) and compare-match constant register 0 (CMCOR0) occurred. Bit 7: CMF 0 1 Description CMCNT0 and CMCOR0 have not matched Clear condition: Write 0 to CMF after reading CMF = 1 A compare-match of CMCNT0 and CMCOR0 occurred (Initial value) Bit 6--Reserved: This is a readable/writable bit, but the write value should be always be 0. Rev. 5.00 Dec 12, 2005 page 433 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Bits 1 and 0--Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to CMCNT from four clocks which are divided from the peripheral clock (P). When the STR0 bit in CMSTR is set to 1, the CMCNT0 starts incrementation with the clock selected by CKS1 and CKS0. Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Description P/4 P/8 P/16 P/64 (Initial value) Compare-Match Counter 0 (CMCNT0) The compare-match counter 0 (CMCNT0) is a 16-bit register that is used as an up-counter. When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in CMSTR is set to 1, CMCNT0 starts incrementation with the selected clock. When the CMCNT0 value matches that in the compare-match constant register 0 (CMCOR0), the CMCNT0 is cleared to H'0000 and the CMF flag in CMCSR0 is set to 1. CMCNT0 is initialized to H'0000 by a reset, but it retains its previous values in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W Rev. 5.00 Dec 12, 2005 page 434 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Compare-Match Constant Register 0 (CMCOR0) The compare-match constant register 0 (CMCOR0) is a 16-bit register that sets the period until a compare-match of CMCNT0 and CMCOR0 occurs. The CMCOR0 is initialized to H'FFFF by a reset, but it retains its previous values in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 1 R/W 7 1 R/W 14 1 R/W 6 1 R/W 13 1 R/W 5 1 R/W 12 1 R/W 4 1 R/W 11 1 R/W 3 1 R/W 10 1 R/W 2 1 R/W 9 1 R/W 1 1 R/W 8 1 R/W 0 1 R/W 14.4.3 Operation Period Count Operation When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in CMSTR is set to 1, the CMCNT0 starts incrementation with the selected clock. When the CMCNT value matches that in CMCOR0, CMCNT0 is cleared to H'0000 and the CMF flag in CMCSR0 is set to 1. The CMCNT0 counter starts incrementation again from H'0000. Figure 14.27 shows the compare-match counter operation. CMCNT0 value CMCOR0 Counter cleared by CMCOR0 compare match H'0000 Time Figure 14.27 Counter Operation Rev. 5.00 Dec 12, 2005 page 435 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) CMCNT0 Count Timing One of four peripheral clocks (P/4, P/8, P/16, P/64) which are divided from the clock (P) can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 14.28 shows the timing. Peripheral clock (P) CMT clock CMCNT0 input clock CMCNT0 N-1 N N+1 Figure 14.28 Count Timing 14.4.4 Compare-Match Compare-Match Flag Set Timing When the CMCOR0 register and the CMCNT0 counter match, a compare-match signal is generated and the CMF bit in the CMCSR0 register is set to 1. The compare-match signal is generated upon the final state of the match (timing at which the CMCNT0 counter value is updated). Consequently, after the CMCOR0 register and the CMCNT0 counter match, a comparematch signal will not be generated until a CMCNT0 counter input clock occurs. Figure 14.29 shows a timing of the CMF bit setting. Rev. 5.00 Dec 12, 2005 page 436 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Peripheral clock (P) CMCNT0 input clock CMCNT0 N 0 CMCOR0 N Compare match signal CMF CMI Figure 14.29 Timing of CMF Setting Compare-Match Flag Clear Timing The CMF bit in the CMCSR0 register is cleared by writing 0 to the bit after reading 1. Figure 14.30 shows the timing when the CMF bit is cleared by the CPU. CMCSR0 write cycle T2 T1 Peripheral clock (P) CMF Figure 14.30 Timing of CMF Clear by the CPU Rev. 5.00 Dec 12, 2005 page 437 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.5 14.5.1 Examples for Use Example of DMA Transfer between A/D Converter and External Memory (Address Reload on) In this example, DMA transfer is performed between the on-chip A/D converter (transfer source) and the external memory (transfer destination) with the address reload function on. Table 14.8 shows the transfer conditions and register settings. Table 14.8 Transfer Conditions and Register Settings for Transfer between On-Chip A/D Converter and External Memory Transfer Conditions Transfer source: on-chip A/D converter Transfer destination: external memory Number of transfers: 128 (reloading 32 times) Transfer source address: incremented Transfer destination address: decremented Transfer request source: A/D converter Bus mode: burst Transfer unit: long word Interrupt request generated at end of transfer Channel priority order: 0 > 2 > 3 > 1 DMAOR H'0101 Register SAR2 DAR2 DMATCR2 CHCR2 Setting H'04000080 H'00400000 H'00000080 H'00089E35 When the address reload function is turned on, the value set in SAR returns to the initially set value at each four transfers. In this example, when an interrupt request is generated from the AD converter, longword data is read from the register in address H'04000080 of the A/D converter, and the data is written to external memory address H'00400000. Since longword data has been transferred, the values in SAR and DAR are H'04000084 and H'003FFFFC, respectively. The bus right is retained and data transfers are successively performed because this transfer is in the burst mode. After four transfers end, fifth and sixth transfers are performed when the address reload function is turned off, and the value in SAR is incremented by 4, such as H'0400008C, H'04000090, H'04000094,.... When the address reload function is on, the DMA transfer stops after the fourth transfer ends and the bus request signal to the CPU is cleared. At this time, the value stored in SAR is not incremented from H'0400008C to H'04000090, but returns to the initially set value H'04000080. The value in DAR continues being incremented regardless of the address reload function setting. Rev. 5.00 Dec 12, 2005 page 438 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) The state in the DMAC differ depending on the address reload function setting as shown in table 14.9. Table 14.9 DMAC Sate after the Fourth Transfer Ends Items SAR DAR DMATCR Bus right DMAC operation Interrupt Transfer request source flag clear Address Reload On H'04000080 H'003FFFFC H'0000007C Released Stops Not generated Executed Address Reload Off H'04000090 H'003FFFFC H'0000007C Held Continues operating Not generated Not executed Notes: 1. When the value in DMATCR reaches 0 and the IE bit in CHCR has been set to 1, interrupts are generated regardless of the address reload function setting. 2. When the value in DMATCR reaches 0, the transfer request source flag is cleared regardless of the address reload function setting. 3. Specify the burst mode when using the address reload function. This function may not be correctly executed in the cycle steal mode. 4. Set the DMATCR value to a multiple of four when using the address reload function. This function may not be correctly executed if other values are specified. 14.5.2 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address on) In this example, DMA transfer is performed between the external memory specified with the indirect address (transfer source) and the SCIF transmitter (transfer destination) using DMAC channel 3. Table 14.10 shows the transfer conditions and register settings. In addition, it is recommendable that the trigger for the number of transmit FIFO data is set to 1 (TTRG1 = TTRG0 = 1 in SCFCR). Rev. 5.00 Dec 12, 2005 page 439 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Table 14.10 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Transfer Conditions Transfer source: external memory Value stored in address H'00400000 Value stored in address H'04500000 Transfer destination: On-chip SCIF TDR2 Number of transfers: 10 Transfer source address: incremented Transfer destination address: fixed Transfer request source: SCIF (TXI2) Bus mode: cycle steal Transfer unit: byte No interrupt request generated at end of transfer Channel priority order: 0 > 1 > 2 > 3 DMAOR H'0001 Register SAR3 -- -- DAR3 DMATCR3 CHCR3 Setting H'00400000 H'00450000 H'55 H'04000156 H'0000000A H'00011C01 When the indirect address is on, data stored in the address set in SAR is not used as transfer source data. In the indirect address, after the value stored in the address set in SAR is read, the read value is used as an address again, and the value stored in the address is read and stored in the address set in DAR. In the example shown in table 14.10, when an SCIF transfer request is generated, the DMAC reads the value in address H'00400000 that is set in SAR3. Since the value H'00450000 is stored in the address, the DMAC reads the value H'00450000. Next, the DMAC uses the read value as an address again, and reads the value H'55 stored in that address. Then, the DMAC writes the value H'55 to address H'04000156 that is set in DAR3; thus one indirect address transfer has completed. In the indirect address, when data is read first from the address set in SAR3, the data transfer size is always longword regardless of the settings of the TS0 and the TS1 bits that specify the transfer data size. However, whether the transfer source address is fixed, incremented, or decremented is specified with the SM0 and SM1 bits. Therefore, in this example, though the transfer data size is specified as byte, the value in SAR3 is H'00400004 when one transfer ends. The write operation is the same as that in the normal dual address transfer. Rev. 5.00 Dec 12, 2005 page 440 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) 14.6 Usage Notes 1. The DMA channel control registers (CHCR0 to CHCR3) can be accessed with any data size. The DMA operation register (DMAOR) must be accessed in byte (8 bits) or word (16 bits) units; other registers must be accessed in word (16 bits) or longword (32 bits) units. 2. When modifying the RS0 to RS3 bits in CHCR0 to CHCR3, first clear the DE bit to 0 (when modifying CHCR with a byte address, be sure to set the DE bit to 0 in advance). 3. If an NMI interrupt is input when the DMAC is not operating, the NMIF bit of the DMAOR is set. 4. A transition to standby mode should be made after the DME bit in DMAOR is cleared to 0 and the transfers that has been accepted by the DMAC end. 5. The on-chip supporting modules that the DMAC can access are, SIOF, SCIF, USB function, A/D converter, and I/O ports. Do not access the other on-chip supporting modules by the DMAC. 6. When starting up the DMAC, set CHCR or DMAOR last. Specifying other registers last does not guarantee normal operation. 7. When the DMA transfer ends normally and subsequently the maximum number of transfers is performed in the same channel, write 0 to DMATCR. Otherwise, normal DMA transfer may not be performed. 8. When using the address reload function, specify the burst mode for the transfer mode. In the cycle-steal mode, normal DMA transfer may not be performed. 9. When using the address reload function, set a multiple of four to DMATCR. Specifying other values does not guarantee normal operation. 10. When detecting an external request at the falling edge, keep the external request pin high when setting the DMAC. 11. Do not access the space from H'4000062 to H'400006F, which is not used by the DMAC. Accessing that space may cause malfunctions. 12. The WAIT signal is ignored when writing to an external address area using DMA 16-byte transfer in dual address mode, and also when transferring data from a DACK-equipped external device to an external address area using DMA 16-byte transfer in single address mode. 13. Big-endian access is used when transferring data from XY memory using the DMAC if all of the following conditions are met: Conditions: (1) Transfer source address in XY memory (2) Indirect addressing mode (3) Byte size data (4) Little-endian data transfer Rev. 5.00 Dec 12, 2005 page 441 of 1034 REJ09B0254-0500 Section 14 Direct Memory Access Controller (DMAC) Measures to avoid the problem: The problem described above occurs only when all of the above conditions are met. It does not arise if even one of the conditions is not met. One of the methods listed below should therefore be employed when using the DMAC to transfer data from XY memory: (1) Use the direct address mode (2) Use long word size or word size data (3) Use big-endian data transfer 14. Do not use the DMAC when in sleep mode. Alternately, set the clock ratio to I:B = 1:1 when using sleep mode. Normal operation cannot be guaranteed otherwise. 15. Do not use the DMAC when only the IFC[2:0] bits in the frequency control register (FRQCR) are modified and the clock ratio is set to other than I:B = 1:1. Normal operation cannot be guaranteed otherwise. However, there is no problem if the STC[2:0] bits are modified simultaneously with the IFC[2:0] bits in the frequency control register (FRQCR). Rev. 5.00 Dec 12, 2005 page 442 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) Section 15 Timer (TMU) 15.1 Overview This LSI has an on-chip 32-bit timer unit (TMU) comprised of three 32-bit timer channels (channels 0 to 2). 15.1.1 Features The TMU has the following features: * Auto-reload 32-bit down-counters for each channel * Auto-reload 32-bit constant registers and 32-bit down counters that can be read or written to at any time for each channel * Interrupt request generation at the counter underflow: Interrupt requests can be generated when the 32-bit down counter underflows (H'00000000 H'FFFFFFFF) in each channel. * Selection of six counter input clocks for each channel: On-chip RTC output clock (16 kHz), P/4, P/16, P/64, and P/256 * All channels can operate when the SH7727 is in standby mode: When the RTC output clock is used as the counter input clock, the count operation is normally performed in standby mode. * Synchronized read: TCNT is a 32-bit register that is successively modified. Since the internal bus for the SH7727 on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built in the TCNT so that the entire 32-bit data in the TCNT can be read at once. * The maximum 2 MHz operating frequency for the 32-bit counter in each channel: Operate the SH7727 so that the clock input to each channel timer counter does not exceed the maximum operating frequency, by dividing the external clock and peripheral clock (P) with the prescaler. Rev. 5.00 Dec 12, 2005 page 443 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the TMU. P Prescaler RTCCLK Clock controller Ch. 0 TSTR TCR0 Counter controller TCNT0 TCOR0 TUNI0 Interrupt controller Ch. 1 TCR1 Counter controller TCNT1 TCOR1 TUNI1 Interrupt controller Ch. 2 TCR2 Counter controller TCNT2 TCOR2 TUNI2 Interrupt controller TMU TCNT: 32-bit timer counter TCOR: 32-bit timer constant register Legend: TSTR: Timer start register TCR: Timer control register Figure 15.1 TMU Block Diagram Rev. 5.00 Dec 12, 2005 page 444 of 1034 REJ09B0254-0500 Module bus Internal bus Bus interface Section 15 Timer (TMU) 15.1.3 Register Configuration Table 15.1 shows the TMU register configuration. Table 15.1 TMU Register Configuration Channel Common 0 Register Timer start register Timer constant register 0 Timer counter 0 Timer control register 0 1 Timer constant register 1 Timer counter 1 Timer control register 1 2 Timer constant register 2 Timer counter 2 Timer control register 2 Abbreviation TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value* Address H'00 H'FFFFFE92 H'FFFFFFFF H'FFFFFE94 H'FFFFFFFF H'FFFFFE98 H'0000 H'FFFFFE9C H'FFFFFFFF H'FFFFFEA0 H'FFFFFFFF H'FFFFFEA4 H'0000 H'FFFFFEA8 H'FFFFFFFF H'FFFFFEAC H'FFFFFFFF H'FFFFFEB0 H'0000 H'FFFFFEB4 Access Size 8 32 32 16 32 32 16 32 32 16 Note: * Initialized by a power-on reset or manual reset. Rev. 5.00 Dec 12, 2005 page 445 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) 15.2 15.2.1 TMU Registers Timer Start Register (TSTR) TSTR is an 8-bit read/write register that selects starting or stopping of the timer counters (TCNT) for channels 0 to 2. TSTR is initialized to H'00 by a power-on reset or manual reset. TSTR is not initialized in standby mode when the on-chip RTC clock (RTCCLK) is selected as the input clock for the channel. However, only if the peripheral clock (P) is selected for the channels, it is initialized in standby mode when the multiplying ratio of PLL circuit 1 is modified and when the MSTP2 bit in STBCR is set to 1. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Bits 7 to 3--Reserved: These bits are always read as 0 and should be written with 0. Bit 2--Counter Start 2 (STR2): Selects starting or stopping of the timer counter 2 (TCNT2). Bit 2: STR2 0 1 Description Halts TCNT2 operation Starts TCNT2 operation (Initial value) Bit 1--Counter Start 1 (STR1): starting or stopping of the timer counter 1 (TCNT1). Bit 1: STR1 0 1 Description Halts TCNT1 operation Starts TCNT1 operation (Initial value) Bit 0--Counter Start 0 (STR0): Selects starting or stopping of the timer counter 0 (TCNT0). Bit 0: STR0 0 1 Description Halts TCNT0 operation Starts TCNT0 operation (Initial value) Rev. 5.00 Dec 12, 2005 page 446 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) 15.2.2 Timer Control Register (TCR) The timer control registers (TCR) are 16-bit read/write registers that control the timer counters (TCNT) and interrupts. The TMU has a total of three TCR registers, one for each channel. The TCR registers control the interrupt generated when the flag that indicates the timer counter (TCNT) underflow has been set to 1, and select the counter clock. When an external clock has been selected, the clock edge can also be selected. TCR is initialized to H'0000 by a power-on reset or manual reset. In standby mode, it is not initialized and retains the value. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 UNIE 0 R/W 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 TPSC2 0 R/W 9 -- 0 R 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W Bits 15 to 9, 7, 6, 4, and 3--Reserved: These bits are always read as 0 and should only be written with 0. Bit 8--Underflow Flag (UNF): This is a status flag that indicates that TCNT underflowed. Bit 8: UNF 0 1 Description TCNT has not underflowed. Clear condition: When 0 is written to UNF TCNT has underflowed (H'00000000 H'FFFFFFFF). Setting condition: When TCNT underflows* (Initial value) Note: * When a write of 1 is provided to UNF, it is not modified and the previous value is retained. Rev. 5.00 Dec 12, 2005 page 447 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) Bit 5--Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt generation when the status flag (UNF) that indicates TCNT underflow has been set to 1. Bit 5: UNIE 0 1 Description Interrupt due to UNF (TUNI) is disabled. Interrupt due to UNF (TUNI) is enabled. (Initial value) Bits 2 to 0--Timer Prescalers 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT count clock. Bit 2: TPSC2 0 Bit 1: TPSC1 0 1 1 0 1 Bit 0: TPSC0 0 1 0 1 0 1 0 1 Description Counts on peripheral clock P/4 Counts on peripheral clock P/16 Counts on peripheral clock P/64 Counts on peripheral clock P/256 Counts on on-chip RTC clock outputs (RTCCLK) Reserved (Setting disabled) Reserved (Setting disabled) Reserved (Setting disabled) (Initial value) 15.2.3 Timer Constant Register (TCOR) The TMU has a total of three TCOR registers, one for each channel. The TCOR registers are 32bit read/write registers that specify a value to be set to the TCNT counter after a TCNT counter underflow occurred. TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset. In standby mode, it is not initialized and retains the value. Rev. 5.00 Dec 12, 2005 page 448 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 1 R/W 23 1 R/W 15 1 R/W 7 1 R/W 30 1 R/W 22 1 R/W 14 1 R/W 6 1 R/W 29 1 R/W 21 1 R/W 13 1 R/W 5 1 R/W 28 1 R/W 20 1 R/W 12 1 R/W 4 1 R/W 27 1 R/W 19 1 R/W 11 1 R/W 3 1 R/W 26 1 R/W 18 1 R/W 10 1 R/W 2 1 R/W 25 1 R/W 17 1 R/W 9 1 R/W 1 1 R/W 24 1 R/W 16 1 R/W 8 1 R/W 0 1 R/W 15.2.4 Timer Counters (TCNT) The TMU has a total of three timer counters (TCNT), one for each channel. The TCNT counters are 32-bit read/write registers that are decremented according to the input clock. The input clock can be selected with the TPSC2 to TPSC0 bits in the timer control register (TCR). When a TCNT decrementation results in an underflow (H'00000000 H'FFFFFFFF), the underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is simultaneously set in TCNT itself and the decrementation continues from that value. The TCNT counter is a 32-bit readable/writable register. Because the internal bus for the SH7727 on-chip peripheral modules is 16 bits wide, a time lag occurs when reading data from 32-bit registers because the upper 16 bits and lower 16 bits are read separately. Since TCNT counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. To prevent this, a buffer register is connected to TCNT so that upper and lower halves are not read separately. Thus all 32 bits in TCNT can thus be read at once and no timing discrepancies occur when reading data. Rev. 5.00 Dec 12, 2005 page 449 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset. In standby mode, it is not initialized and retains the value. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 1 R/W 23 1 R/W 15 1 R/W 7 1 R/W 30 1 R/W 22 1 R/W 14 1 R/W 6 1 R/W 29 1 R/W 21 1 R/W 13 1 R/W 5 1 R/W 28 1 R/W 20 1 R/W 12 1 R/W 4 1 R/W 27 1 R/W 19 1 R/W 11 1 R/W 3 1 R/W 26 1 R/W 18 1 R/W 10 1 R/W 2 1 R/W 25 1 R/W 17 1 R/W 9 1 R/W 1 1 R/W 24 1 R/W 16 1 R/W 8 1 R/W 0 1 R/W Rev. 5.00 Dec 12, 2005 page 450 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) 15.3 15.3.1 TMU Operation Overview Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). The TCNT is a down-counter. The auto-reload function can be used to enable synchronized counting and counting by external events. 15.3.2 Basic Functions Counter Operation: When the STR0 to STR2 bits in the timer start register (TSTR) are set, the corresponding timer counters (TCNT) start decrementation. When TCNT underflows, the UNF flag in the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT and the decrementation is continued. The decrementation is set as follows (figure 15.2): Select operation Select counter clock (1) Select the counter clock with the TPSC2 to TPSC0 bits in the timer control register (TCR). (2) Set whether or not an interrupt is generated when TCNT underflows, with the UNIE bit in TCR. (3) Set a value in the timer constant register (TCOR) (the cycle is the set value plus 1). (3) (4) Set the initial value in the timer counter (TCNT). (5) Set the STR bit in the timer start register (TSTR) to 1 to start operation. (1) Set underflow interrupt generation Set timer constant register Initialize timer counter (2) (4) Start counting (5) Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it. If interrupts are enabled without clearing the flag, another interrupt will be generated. Figure 15.2 Setting the Count Operation Rev. 5.00 Dec 12, 2005 page 451 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) Auto-Reload Count Operation: Figure 15.3 shows the TCNT auto-reload operation. TCOR value set to TCNT during underflow TCNT value TCOR H'00000000 STR0 to STR2 UNF Time Figure 15.3 Auto-Reload Counter Operation TCNT Count Timing: * Internal Clock Operation Select one of the four internal clocks (P/4, P/16, P/64, P/256), which are divided from the peripheral clock P, with the TPSC2 to TPSC0 bits in TCR. Figure 15.4 shows the timing. P Divided clock TCNT input clock TCNT N+1 N N-1 Figure 15.4 Count Timing when Internal Clock is Operating Rev. 5.00 Dec 12, 2005 page 452 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) * On-Chip RTC Clock Operation Select the on-chip RTC clock as the timer clock with the TPSC2 to TPSC0 bits in TCR. RTC output clock TCNT input clock TCNT N+1 N N-1 Figure 15.5 Count Timing when On-Chip RTC Clock is Operating 15.4 Interrupts There is only one source for TMU interrupts: underflow interrupts (TUNI). 15.4.1 Status Flag Set Timing The UNF bit is set to 1 when TCNT underflows. Figure 15.6 shows the timing. P TCNT Underflow signal UNF TUNI H'00000000 TCOR value Figure 15.6 UNF Set Timing Rev. 5.00 Dec 12, 2005 page 453 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) 15.4.2 Status Flag Clear Timing The status flag is cleared when 0 is written by the CPU. Figure 15.7 shows the timing. TCR write cycle T1 P Peripheral address bus UNF TCR address T2 T3 Figure 15.7 Status Flag Clear Timing 15.4.3 Interrupt Sources and Priorities The TMU generates underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, the corresponding interrupt is requested. When an interrupt is generated, codes are set in the interrupt event register (INTEVT, INTEVT2). Provide the appropriate interrupt handling according to the codes. The channel priority can be changed using the interrupt controller (see section 4, Exception Handling, and section 7, Interrupt Controller (INTC)). Table 15.2 lists TMU interrupt sources. Table 15.2 TMU Interrupt Sources Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Low Priority High Rev. 5.00 Dec 12, 2005 page 454 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) 15.5 15.5.1 Usage Notes Writing to Registers Synchronous processing is not performed for timer count operation during register writes. When writing to registers, always clear the start bits (STR2 to STR0) for the desired channel in the timer start register (TSTR) to halt timer counting. 15.5.2 Reading Registers Synchronous processing is performed for timer count operation during register reads. When timer counting and register read processing are performed simultaneously, the register value prior to the TCNT decrementation is read with the synchronous processing. Rev. 5.00 Dec 12, 2005 page 455 of 1034 REJ09B0254-0500 Section 15 Timer (TMU) Rev. 5.00 Dec 12, 2005 page 456 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) Section 16 Realtime Clock (RTC) 16.1 Overview This LSI has a realtime clock (RTC) with its own 32.768-kHz crystal oscillation circuit. 16.1.1 Features The RTC has the following features: * Clock and calendar functions (BCD display): Seconds, minutes, hours, date, day of the week, month, and year * 1 to 64-Hz timer (binary display) * Start/stop function * 30-second adjustment * Alarm interrupt: Frame comparisons of seconds, minutes, hours, date, day of the week, and month can be selected for the alarm interrupt condition * Periodic interrupts: The interrupt cycle can be selected from 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds * Carry interrupt: A carry interrupt indicates when a carry occurs during a counter read * Automatic leap year correction Rev. 5.00 Dec 12, 2005 page 457 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the RTC. Externally connected circuit EXTAL2 Oscillator circuit XTAL2 32.768 kHz Prescaler (/ 2) RTCCLK 16.384 kHz 128 Hz 30second Reset ADJ RSECCNT RMINCNT RHRCNT RWKCNT Prescaler (/ 128) RDAYCNT RMONCNT RYRCNT ATI PRI RSECAR RMINAR CUI Carry detection circuit RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 Legend: R64CNT: RSECCNT: RMINCNT: RHRCNT: RWKCNT: RDAYCNT: RMONCNT: RYRCNT: 64-Hz counter Second counter Minute counter Hour counter Day of the week counter Date counter Month counter Year counter RSECAR: RHRAR: RMINAR: RWKAR: RDAYAR: RMONAR: RCR1: RCR2: RTC Second alarm register Minute alarm register Hour alarm register Day of the week alarm register Date alarm register Month alarm register RTC control register 1 RTC control register 2 Figure 16.1 RTC Block Diagram Rev. 5.00 Dec 12, 2005 page 458 of 1034 REJ09B0254-0500 Module bus Interrupt control circuit Comparator Internal bus R64CNT Bus interface Section 16 Realtime Clock (RTC) 16.1.3 Pin Configuration Table 16.1 shows the RTC pin configuration. Table 16.1 RTC Pin Configuration Pin RTC oscillator crystal pin RTC oscillator crystal pin Power-supply pin dedicated for RTC GND pin dedicated for RTC Abbreviation EXTAL2 XTAL2 Vcc-RTC Vss-RTC I/O I O -- -- Description Connects crystal to RTC oscillator* 1 Connects crystal to RTC oscillator* 1 Power-supply pin for RTC oscillator* GND pin for RTC oscillator* 2 1 Notes: 1. When the RTC is not used, set EXTAL2 to pull-up (to Vcc) and make no connection for XTAL2. 2. Input of external noise via the Vss-RTC pin can cause the device to malfunction. To prevent external noise input via the Vss-RTC, the system and circuitry should include a noise elimination circuit. Rev. 5.00 Dec 12, 2005 page 459 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.1.4 RTC Register Configuration Table 16.2 shows the RTC register configuration. Table 16.2 RTC Registers Name 64-Hz counter Second counter Minute counter Hour counter Day of week counter Date counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Day of week alarm register Date alarm register Month alarm register RTC control register 1 RTC control register 2 Abbreviation R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* H'00 H'09 Address H'FFFFFEC0 H'FFFFFEC2 H'FFFFFEC4 H'FFFFFEC6 H'FFFFFEC8 H'FFFFFECA H'FFFFFECC H'FFFFFECE H'FFFFFED0 H'FFFFFED2 H'FFFFFED4 H'FFFFFED6 H'FFFFFED8 H'FFFFFEDA H'FFFFFEDC H'FFFFFEDE Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Note: * Only the ENB bit in each register is initialized. Rev. 5.00 Dec 12, 2005 page 460 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2 16.2.1 Register Descriptions 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the state of the RTC divider circuits (RTC prescaler or R64CNT) between 64 Hz and 1 Hz. R64CNT is reset to H'00 when the RESET bit in RTC control register 2 (RCR2) or the ADJ bit in RCR2 is set to 1. R64CNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. Bit 7 is always read as 0. Bit: Initial value: R/W: 7 -- 0 R 6 1Hz -- R 5 2Hz -- R 4 4Hz -- R 3 8Hz -- R 2 16Hz -- R 1 32Hz -- R 0 64Hz -- R 16.2.2 Second Counter (RSECCNT) The second counter (RSECCNT) is an 8-bit read/write register that is used for setting/counting in the BCD-coded second section of the RTC. The count operation is performed by a carry for each second of the 64-Hz counter. The settable range is 00 to 59 in decimal. If other values are set, correct operation is not provided. When modifying RSECCNT, check that the count operation has been halted with the START bit in RCR2. RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. Bit: Initial value: R/W: 7 -- 0 R -- R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 -- R/W 1 -- R/W 0 -- R/W 1 second Rev. 5.00 Dec 12, 2005 page 461 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2.3 Minute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded minute section of the RTC. The count operation is performed by a carry for each minute of the second counter. The settable range is 00 to 59 in decimal. If other values are set, correct operation is not provided. When modifying RMINCNT, check that the count operation has been halted with the START bit in RCR2. RMINCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. Bit: Initial value: R/W: 7 -- 0 R -- R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 1 minute -- R/W -- R/W -- R/W 1 0 16.2.4 Hour Counter (RHRCNT) The hour counter (RHRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded hour section of the RTC. The count operation is performed by a carry for each 1 hour of the minute counter. The settable range is 00 to 23 in decimal. If other values are set, correct operation is not provided. When modifying RHRCNT, check that the count operation has been halted with the START bit in RCR2. RHRCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- R/W 4 -- R/W 3 -- R/W 2 1 hour -- R/W -- R/W -- R/W 1 0 10 hours Rev. 5.00 Dec 12, 2005 page 462 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2.5 Day of the Week Counter (RWKCNT) The day of the week counter (RWKCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded day of week section of the RTC. The count operation is performed by a carry for each day of the date counter. The settable range is 0 to 6 in decimal. If other values are set, correct operation is not provided. When modifying RWKCNT, check that the count operation has been halted with the START bit in RCR2. RWKCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day of week -- R/W -- R/W 0 Days of the week are coded as shown in table 16.3. Table 16.3 Day-of-Week Codes (RWKCNT) Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Code 0 1 2 3 4 5 6 Rev. 5.00 Dec 12, 2005 page 463 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2.6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded date section of the RTC. The count operation is performed by a carry for each day of the hour counter. The settable range is 01 to 31 in decimal. If other values are set, correct operation is not provided. When modifying RDAYCNT, check that the count operation has been halted with the START bit in RCR2. RDAYCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. The settable RDAYCNT range differs according to the month and leap year. Please confirm the correct setting. Bit: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 10 days -- R/W -- R/W -- R/W -- R/W 4 3 2 1 day -- R/W -- R/W 1 0 16.2.7 Month Counter (RMONCNT) The month counter (RMONCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded month section of the RTC. The count operation is performed by a carry for each month of the date counter. The settable range is 01 to 12 in decimal. If other values are set, correct operation is not provided. When modifying RMONCNT, check that the count operation has been halted with the START bit in RCR2. RMONCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 10 months -- R/W -- R/W 3 2 1 month -- R/W -- R/W -- R/W 1 0 Rev. 5.00 Dec 12, 2005 page 464 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2.8 Year Counter (RYRCNT) The year counter (RYRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded year section of the RTC. The least significant 2 digits of the western calendar year are displayed. The count operation is performed by a carry for each year of the month counter. The settable range is 00 to 99 in decimal. If other values are set, correct operation is not provided. When modifying RYRCNT, check that the count operation is halted with the START bit in RCR2. RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. Note that a counter value of 00 is treated as a leap year. Bit: Initial value: R/W: 7 -- R/W 6 10 years -- R/W -- R/W -- R/W -- R/W -- R/W 5 4 3 2 1 year -- R/W -- R/W 1 0 16.2.9 Second Alarm Register (RSECAR) The second alarm register (RSECAR) is an 8-bit read/write alarm register that corresponds to the BCD-coded second section counter RSECCNT of the RTC. When the ENB bit is set to 1in RSECAR, the RSECAR value and RSECCNT value are compared. In this way, the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is generated. The settable range is "00 to 59 in decimal + ENB bit". If other values are set, correct operation is not provided. Only the ENB bit in RSECAR is initialized to 0 by a power-on reset, and the other bits are not initialized. The RSECAR contents are retained after a manual reset or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W -- R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 -- R/W 1 -- R/W 0 -- R/W 1 second Rev. 5.00 Dec 12, 2005 page 465 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2.10 Minute Alarm Register (RMINAR) The minute alarm register (RMINAR) is an 8-bit read/write alarm register that corresponds to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1in RMINAR, the RMINAR value and RMINCNT value are compared. In this way, the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is generated. The settable range is "00 to 59 in decimal + ENB bit". If other values are set, correct operation is not provided. Only the ENB bit in RMINAR is initialized to 0 by a power-on reset, and the other bits are not initialized. The RMINAR contents are retained after a manual reset or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W -- R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 1 minute -- R/W -- R/W -- R/W 1 0 16.2.11 Hour Alarm Register (RHRAR) The hour alarm register (RHRAR) is an 8-bit read/write alarm register that corresponds to the BCD-coded hour section counter RHRCNT of the RTC. When the ENB bit is set to 1in RHRAR, the RHRAR value and RHRCNT value are compared. In this way, the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is generated. The settable range is "00 to 23 in decimal + ENB bit". If other values are set, correct operation is not provided. Only the ENB bit in RHRAR is initialized to 0 by a power-on reset, and the other bits are not initialized. The RHRAR contents are retained after a manual reset or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 -- R/W 4 -- R/W 3 -- R/W 2 1 hour -- R/W -- R/W -- R/W 1 0 10 hours Rev. 5.00 Dec 12, 2005 page 466 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2.12 Day of the Week Alarm Register (RWKAR) The day of the week alarm register (RWKAR) is an 8-bit read/write alarm register that corresponds to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1in RWKAR, the RWKAR value and RWKCNT value are compared. In this way, the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is generated. The settable range is "0 to 6 in decimal + ENB bit". If other values are set, correct operation is not provided. Only the ENB bit in RWKAR is initialized to 0 by a power-on reset, and the other bits are not initialized. The RWKAR contents are retained after a manual reset or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day of week -- R/W -- R/W 0 Days of the week are coded as shown in table 16.4. Table 16.4 Day-of-Week Codes (RWKAR) Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Code 0 1 2 3 4 5 6 16.2.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit read/write alarm register that corresponds to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1in RDAYAR, the RDAYAR value and RDAYCNT value are compared. In this way, the RSECAR, Rev. 5.00 Dec 12, 2005 page 467 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is generated. The settable range is "01 to 31 in decimal + ENB bit". If other values are set, correct operation is not provided. The settable RDAYCNT range differs according to the month and leap year. Please confirm the correct setting. Only the ENB bit in RDAYAR is initialized to 0 by a power-on reset, and the other bits are not initialized. The RDAYAR contents are retained after a manual reset or in standby mode. Bit: Initial value: R/W: 7 ENB 0 R/W 6 -- 0 R 5 10 days -- R/W -- R/W -- R/W -- R/W 4 3 2 1 day -- R/W -- R/W 1 0 16.2.14 Month Alarm Register (RMONAR) The month alarm register (RMONAR) is an 8-bit read/write alarm register that corresponds to the BCD-coded month section counter RMONCNT of the RTC. When the ENB bit is set to 1in RMONAR, the RMONAR value and RMONCNT value are compared. In this way, the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are compared. If all values in the specified alarm registers and the corresponding counters match, an RTC alarm interrupt is generated. The settable range is "01 to 12 in decimal + ENB bit". If other values are set, correct operation is not provided. Only the ENB bit in RMONAR is initialized to 0 by a power-on reset, and the other bits are not initialized. The RMONAR contents are retained after a manual reset or in standby mode. Bit: 7 ENB Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 10 months -- R/W -- R/W 3 2 1 month -- R/W -- R/W -- R/W 1 0 Rev. 5.00 Dec 12, 2005 page 468 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.2.15 RTC Control Register 1 (RCR1) The RTC control register 1 (RCR1) is an 8-bit read/write register that contains carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Avoid the use of readmodify-write processing for this register because flags are sometimes set after an operand read. RCR1 is an 8-bit read/write register. The CIE, AIE, and AF bits are initialized by a power-on reset or manual reset. However, the value of the CF flag is undefined after a power-on reset or manual reset. It must therefore be initialized without fail before use. This register is not initialized in standby mode. Bit: Initial value: R/W: 7 CF -- R/W 6 -- 0 R 5 -- 0 R 4 CIE 0 R/W 3 AIE 0 R/W 2 -- 0 R 1 -- 0 R 0 AF 0 R/W Bit 7--Carry Flag (CF): Status flag that indicates that a carry has occurred. CF is set to 1 when a carry occurs in R64CNT or RSECCNT. If the count register is read at this time, the value is not guaranteed; therefore, another read is required. Bit 7: CF 0 1 Description No carry in R64CNT or RSECCNT. Clearing condition: When 0 is written to CF Setting condition: Carry occurred in RSECCNT Read of R64CNT at carry occurrence When 1 is written to CF Bits 6, 5, 2, and 1--Reserved: These bits are always read as 0 and should only be written with 0. Bit 4--Carry Interrupt Enable Flag (CIE): Enables or disables interrupt generation when the carry flag (CF) is set to 1. Bit 4: CIE 0 1 Description A carry interrupt is not generated when the CF flag is set to 1 A carry interrupt is generated when the CF flag is set to 1 (Initial value) Rev. 5.00 Dec 12, 2005 page 469 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) Bit 3--Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the alarm flag (AF) is set to 1. Bit 3: AIE 0 1 Description An alarm interrupt is not generated when the AF flag is set to 1 An alarm interrupt is generated when the AF flag is set to 1 (Initial value) Bit 0--Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in alarm registers (only for the registers with ENB bit set to 1) match the clock and calendar time. This flag is cleared to 0 when 0 is written, but the previous value is retained when 1 is to be written. Bit 0: AF 0 1 Description Clock/calendar and alarm register have not matched since last reset to 0. Clearing condition: When 0 is written to AF (Initial value) Setting condition: Clock/calendar and alarm register have matched (only for the registers with ENB set to 1)* Note: * The value is not modified when 1 is written to AF. 16.2.16 RTC Control Register 2 (RCR2) The RTC control register 2 (RCR2) is an 8-bit read/write register that controls periodic interrupts, 30-second adjustment ADJ, divider circuits RESET, and starting and stopping of the RTC count. It is initialized to H'09 by a power-on reset. By a manual reset, bits except RTCEN and START are initialized. RCR2 is not initialized and retains its contents in standby mode. Bit: Initial value: R/W: 7 PEF 0 R/W 6 PES2 0 R/W 5 PES1 0 R/W 4 PES0 0 R/W 3 RTCEN 1 R/W 2 ADJ 0 R/W 1 RESET 0 R/W 0 START 1 R/W Rev. 5.00 Dec 12, 2005 page 470 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) Bit 7--Periodic Interrupt Flag (PEF): Indicates that interrupts are generated with the period designated by the PES bits. When this bit is set to 1, periodic interrupts are generated. Bit 7: PEF 0 1 Description Interrupts not generated with the period designated by the PES bits. Clearing condition: When 0 is written to PEF Setting condition: When interrupts are generated with the period designated by the PES bits When 1 is written to PEF (Initial value) Bits 6 to 4--Periodic Interrupt Flags (PES2 to PES0): These bits specify the periodic interrupt. Bit 6: PES2 0 Bit 5: PES1 0 1 1 0 1 Bit 4: PES0 0 1 0 1 0 1 0 1 Description No periodic interrupts generated (Initial value) Periodic interrupt generated every 1/256 second Periodic interrupt generated every 1/64 second Periodic interrupt generated every 1/16 second Periodic interrupt generated every 1/4 second Periodic interrupt generated every 1/2 second Periodic interrupt generated every 1 second Periodic interrupt generated every 2 seconds Bit 3--RTCEN: Controls the operation of the crystal oscillator for the RTC. Bit 3: RTCEN 0 1 Description Halts the crystal oscillator for the RTC. * Runs the crystal oscillator for the RTC. * (Initial value) Note: * RTCEN should be set to 0 when the RTC is not used. Rev. 5.00 Dec 12, 2005 page 471 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) Bit 2--30 Second Adjustment (ADJ): When the ADJ bit is written with 1, the time of 29 seconds or less will be rounded to 00 seconds and the time of 30 seconds or more to 1 minute. The divider circuits (RTC prescaler and R64CNT) will be simultaneously reset. This bit is always read as 0. Bit 2: ADJ 0 1 (write) Description Normal operation 30-second adjustment. (Initial value) Bit 1--Reset (RESET): When 1 is written to the RESET bit, the divider circuits (RTC prescaler and R64CNT) are initialized. This bit is always read as 0. Bit 1: RESET 0 1 (Write) Description Runs normally. Divider circuits are reset. (Initial value) Bit 0--Start Bit (START): Halts and restarts the counter (clock). Bit 0: START 0 1 Description Second, minute, hour, day, week, month, and year counters are halted.* Second, minute, hour, day, week, month, and year counters operate normally.* (Initial value) Note: * The 64-Hz counter operates normally until it is stopped with the RTCEN bit. Rev. 5.00 Dec 12, 2005 page 472 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.3 16.3.1 RTC Operation Initial Settings of Registers after Power-On All RTC registers should be set initially after the power is turned on. 16.3.2 Setting the Time Figures 16.2 (a) and 16.2 (b) show how to set the time after stopping the clock. This procedure can be used to set the entire calendar and clock function. It can be programmed easily. Usage Notes 1. Initialization Timing for 64 Hz Counter (R64CNT) If it is necessary, after initializing the counter by means of the RESET bit in the RTC's RCR2 register, to confirm that the change has taken effect by reading the R64CNT value, wait at least 107 s after setting the RESET bit to 1 before reading the R64CNT counter. Note that the divider circuit (RTC prescaler) is also initialized when the RESET bit is set to 1. 2. Incrementing RSECCNT by Initializing R64CNT Either method (a) or method (b) below may be used. (a) After setting the RESET bit to 1 and confirming that R64CNT has been initialized, set the START bit to 1. This process is shown in figure 16.2 (a). (b) Set the START bit to 1 and the RESET bit to 1 at the same time. This process is shown in figure 16.2 (b). Note that the processing indicated by the asterisk (*) in figure 16.2 (b) may be omitted if nothing is written to the RCR2 register during an interval of approximately 107 s after the START bit is set to 1. Rev. 5.00 Dec 12, 2005 page 473 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) Confirm R64CNT is not 0 Stop clock Reset divider circuit Set seconds, minutes, hour, day, day of the week, month and year Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Confirm R64CNT is 0 No Yes Start clock Write 1 to START in the RCR2 register Figure 16.2(a) Setting the Time * Confirm R64CNT is not 0 Stop clock Reset divider circuit Set seconds, minutes, hour, day, day of the week, month and year Start clock Reset divider circuit Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Write 1 to RESET and 1 to START in the RCR2 register * Confirm R64CNT is 0 No Yes * Write to RCR2 Figure 16.2(b) Setting the Time Rev. 5.00 Dec 12, 2005 page 474 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.3.3 Reading the Time Figure 16.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. The method of reading the time without using interrupts is shown at (a) in figure 16.3, and the method using carry interrupts is shown at (b). To keep the program simple, method (a) is used normally. a. To read the time without using interrupts Disable the carry interrupt Write 0 to CIE in RCR1 Write 0 to CF in RCR1 Note: Set AF to 1 so that alarm flag is not cleared. Clear the carry flag Read counter register Yes Carry flag = 1? No Read RCR1 and check CF b. To use interrupts Enable the carry interrupt Clear the carry flag Read counter register Yes Interrupt generated? No Disable the carry interrupt Write 1 to CIE in RCR1, and write 0 to CF in RCR1 Note: Set AF in RCR1 to 1 so that alarm flag is not cleared. Write 0 to CIE in RCR1 Figure 16.3 Reading the Time Rev. 5.00 Dec 12, 2005 page 475 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.3.4 Alarm Function Figure 16.4 shows how to use the alarm function. Alarm can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bits (bit 7) in the desired alarm registers to 1, and then set the alarm time in the lower bits. Clear the ENB bits in the registers which are not used for the alarm to 0. When the clock and alarm time match, the AF bit (bit 0) in RCR1 is set to 1. The alarm detection can be checked by reading this bit, but normally it is checked by the interrupt generation. If the AIE bit (bit 3) in RCR1 is written with 1, an interrupt is generated when an alarm occurs. Clock running Disables interrupts (clears the AIE bit in RCR1 to 0) in order to prevent erroneous interrupts, and then writes 1. Cancel alarm interrupt Set alarm time Clear alarm flag Always reset the alarm flag, since a flag may have been set while the alarm time was being set (clear the AF bit in RCR1 register to 0). Monitor alarm time (wait for interrupt or check alarm flag) Figure 16.4 Using the Alarm Function Rev. 5.00 Dec 12, 2005 page 476 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.3.5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 16.5, and the RTC crystal oscillator circuit in figure 16.5. Table 16.5 Recommended Oscillator Circuit Constants (Recommended Values) fosc 32.768 kHz Cin 10 to 22 pF Cout 10 to 22 pF SH7727 EXTAL2 Rf RD XTAL2 XTAL Cin Cout Notes: 1. Select either the Cin or Cout side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. Built-in resistance value Rf (Typ value) = 10 M, RD (Typ value) = 400 k 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a ground plane. 4. The crystal oscillation settling time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2, XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. Figure 16.5 Example of Crystal Oscillator Circuit Connection Rev. 5.00 Dec 12, 2005 page 477 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.4 16.4.1 Usage Notes Writing Registers During RTC Count Operation During the RTC count operation (RCR2 bits 0 = 1), the following registers cannot be written. RSECCNT, RMICNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, and RYRCNT To write these registers, the RTC count operation should be stopped. 16.4.2 RTC Periodic Interrupts Figure 16.6 shows the periodic interrupt function setting flow. Periodic interrupts can be generated with the period specified by the periodic interrupt enable flag (PES) in the RTC control register (RCR2). When the time period specified by PES passed, the periodic interrupt flag (PEF) is set to 1. PEF is cleared to 0 when PES is set and a periodic interrupt is generated. The periodic interrupt generation can be checked by reading this bit, but is usually checked by the interrupt function. PES is set and PEF is cleared in RCR2. Set PES and clear PEF Period set by PES passed Clears PEF PEF is cleared to 0. Figure 16.6 Periodic Interrupt Function Setting Rev. 5.00 Dec 12, 2005 page 478 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) 16.4.3 Using the ADJ Bit in the Real Time Clock (RTC) (1) Description The maximum amount of time from when the ADJ bit in RCR2 of the RTC is set to 1 and when the value read from the second counter (RSECCNT) is reflected is approximately 91.6 s (the time required for pin of the EXTAL2 to connect to the 32.768 kHz oscillator). Note that the second counter itself performs a 30-second adjustment when the ADJ bit is set to 1, so the above delay causes no problems with the functioning of the RTC. (2) Precautions If it is necessary to ensure that the 30-second adjustment triggered by the ADJ bit in RCR2 of the RTC is properly read and its value reflected, the second counter should not be read until a minimum of approximately 91.6 s has passed following the setting of the ADJ bit. Rev. 5.00 Dec 12, 2005 page 479 of 1034 REJ09B0254-0500 Section 16 Realtime Clock (RTC) Rev. 5.00 Dec 12, 2005 page 480 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Section 17 Serial Communication Interface (SCI) 17.1 Overview This LSI has an on-chip serial communication interface (SCI) that supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. The SCI supports a smart card interface, which is a serial communications feature for IC card interfaces that conforms to the ISO/IEC standard 7816-3 for identification cards data transmission protocol type T = 0. See section 18, Smart Card Interface, for more information. 17.1.1 Features Select asynchronous or clock synchronous as the serial communications mode. * Asynchronous mode: Serial data communications are synched by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. It can also communicate with two or more other processors using the multiprocessor communication function. There are 12 selectable serial data communication formats. Data length: Seven or eight bits Stop bit length: One or two bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: By reading the RxD level directly from the port SC data register (SCSPTR) when a framing error occurs * Clock synchronous mode: Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a clock synchronous communication function. There is one serial data communication format. Data length: Eight bits Receive error detection: Overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. Rev. 5.00 Dec 12, 2005 page 481 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. * When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power. 17.1.2 Block Diagram Figure 17.1 shows an SCI block diagram. Bus interface Module data bus Internal data bus SCRDR SCTDR RxD0 SCRSR SCTSR TxD0 SCPCR SCPDR SCSSR SCSSR SCSCR SCSMR Transmit/ receive control SCBRR Baud rate generator P P/4 P/16 P/64 Parity generation Parity check Clock External clock TEI TXI RXI ERI SCK0 SCI Legend: SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register SCSCR: SCSSR: SCBRR: SCPDR: SCPCR: Serial control register Serial status register Bit rate register SC port data register SC port control register Figure 17.1 SCI Block Diagram Rev. 5.00 Dec 12, 2005 page 482 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Figures 17.2 to 17.4 show the block diagrams of the SCI I/O port. SCI pin I/O and data control is performed by bits 3 to 0 of SCPCR and bits 1 and 0 of SCPDR. For details, see section 17.2.8, Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR). Reset R D SCP1MD0 Q C PCRW Reset Q R D Internal data bus SCP1MD1 C PCRW Reset SCPT[1]/SCK0 R Q D SCP1DT1 C PDRW SCI Clock input enable Output enable Serial clock output PDRR* Serial clock input Legend: PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK0 pin, clear the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP1MD1 bit in SCPCR to 1 (see section 17.2.8). Figure 17.2 SCPT[1]/SCK0 Pin Rev. 5.00 Dec 12, 2005 page 483 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Reset R D SCP0MD0 Q C PCRW Reset Q R D Internal data bus SCP0MD1 C PCRW Reset SCPT[0]/TxD0 R Q D SCP0DT1 C PDRW Output enable Serial transmission output SCI Legend: PCRW: SCPCR write PDRW: SCPDR write Figure 17.3 SCPT[0]/TxD0 Pin Rev. 5.00 Dec 12, 2005 page 484 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) SCI SCPT[0]/RxD0 Serial receive data Internal data bus Legend: PDRR: PDR read PDRR* Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Figure 17.4 SCPT[0]/RxD0 Pin 17.1.3 Pin Configuration The SCI has the serial pins summarized in table 17.1. Table 17.1 SCI Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 I/O I/O Input Output Function Clock I/O Receive data input Transmit data output Note: They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKEO bits in SCSCR and the C/A bit in SCSMR. Break state transmission and detection can be performed by means of the SCI's SCSPTR register. Rev. 5.00 Dec 12, 2005 page 485 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.1.4 Register Configuration Table 17.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or clock synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 17.2 Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Port SC data register Port SC control register Abbreviation SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCPDR SCPCR R/W R/W R/W R/W R/W R/(W)* R R/W R/W 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'8008 Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A Access size 8 8 8 8 8 8 H'04000136 8 2 (H'A4000136)* H'04000116 16 2 (H'A4000116)* Notes: Registers with addresses beginning at H'04 are located in area 1 of physical space. Consequently, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. The only value that can be written is 0 to clear the flags. 2. When address translation by the MMU is not executed, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 486 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.2 17.2.1 Register Descriptions Receive Shift Register (SCRSR) Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- The receive shift register (SCRSR) receives serial data. Data input at the RxD0 pin is loaded into the SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the SCRDR. The CPU cannot read or write the SCRSR directly. 17.2.2 Receive Data Register (SCRDR) Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into the SCRDR for storage. The SCRSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby or module standby mode. Rev. 5.00 Dec 12, 2005 page 487 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.2.3 Transmit Shift Register (SCTSR) Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into the SCTSR, then transmits the data serially from the TxD0 pin, LSB (bit 0) first. After transmitting one-byte data, the SCI automatically loads the next transmit data from the SCTDR into the SCTSR and starts transmitting again. If the TDRE bit of the SCSSR is 1, however, the SCI does not load the SCTDR contents into the SCTSR. The CPU cannot read or write the SCTSR directly. 17.2.4 Transmit Data Register (SCTDR) Bit: Initial value: R/W: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W The transmit data register (SCTDR) is an eight-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into the SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in the SCTDR during serial transmission from the SCTSR. The CPU can always read and write the SCTDR. The SCTDR is initialized to H'FF by a reset or in standby and module standby modes. Rev. 5.00 Dec 12, 2005 page 488 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.2.5 Serial Mode Register (SCSMR) Bit: 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value: R/W: The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SCSMR. The SCSMR is initialized to H'00 by a reset or in standby and module standby modes. Bit 7--Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or A clock synchronous mode. Bit 7: C/A A 0 1 Description Asynchronous mode Clock synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR 0 1 Description Eight-bit data Seven-bit data* (Initial value) Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. Rev. 5.00 Dec 12, 2005 page 489 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bit 5: PE 0 1 Description Parity bit not added or checked Parity bit added and checked* (Initial value) Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. E The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored in the clock synchronous mode, or in the asynchronous mode when parity addition and check is disabled. Bit 4: O/E E 0 1 Description Even parity* 2 Odd parity* 1 (Initial value) Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP 0 1 Description One stop bit * 2 Two stop bits* 1 (Initial value) Notes: 1. In transmitting, a single bit of 1 is added at the end of each transmitted character. 2. In transmitting, two bits of 1 are added at the end of each transmitted character. Rev. 5.00 Dec 12, 2005 page 490 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in the asynchronous mode; it is ignored in the clock synchronous mode. For the multiprocessor communication function, see section 17.3.3, Multiprocessor Communication. Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available. P, P/4, P/16 and P/64. For further information on the clock source, bit rate register settings, and baud rate, see section 17.2.9, Bit Rate Register (SCBRR). Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Note: P: Peripheral clock Description P P/4 P/16 P/64 (Initial value) 17.2.6 Serial Control Register (SCSCR) Bit: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value: R/W: The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCSCR. The SCSCR is initialized to H'00 by a reset or in standby and module standby modes. Rev. 5.00 Dec 12, 2005 page 491 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SCSSR) is set to 1 due to transfer of serial transmit data from the SCTDR to the SCTSR. Bit 7: TIE 0 1 Description Transmit-data-empty interrupt request (TXI) is disabled* Transmit-data-empty interrupt request (TXI) is enabled (Initial value) Note: * The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SCSSR) is set to 1 due to transfer of serial receive data from the SCRSR to the SCRDR. It also enables or disables receive-error interrupt (ERI) requests. Bit 6: RIE 0 1 Description Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled* (Initial value) Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Note: * RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. Bit 5--Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE 0 1 Description Transmitter disabled* 2 Transmitter enabled* 1 (Initial value). Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is fixed to 1. 2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SCSSR) is cleared to 0 after writing of transmit data into the SCTDR. Select the transmit format in the SCSMR before setting TE to 1. Bit 4--Receive Enable (RE): Enables or disables the SCI serial receiver. Rev. 5.00 Dec 12, 2005 page 492 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bit 4: RE 0 1 Description Receiver disabled* 2 Receiver enabled* 1 (Initial value) Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. Select the receive format in the SCSMR before setting RE to 1. Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is ignored in the clock synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) [Clear conditions] 1. When MPIE is cleared to 0 2. When the multiprocessor bit (MPB) is set to 1 in receive data 1 Multiprocessor interrupts are enabled* Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SCSSR) are disabled until data with a multiprocessor bit of 1 is received. Note: * The SCI does not transfer receive data from the SCRSR to the SCRDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SCSSR). When it receives data that includes MPB = 1, the SCSSR's MPB flag is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in the SCSCR are set to 1), and allows the FER and ORER bits to be set. (Initial value) Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted. Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) requests are disabled* Transmit-end interrupt (TEI) requests are enabled* (Initial value) Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0, or by clearing the TEIE bit to 0. Rev. 5.00 Dec 12, 2005 page 493 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bits 1 and 0--Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK0 pin. Depending on the combination of CKE1 and CKE0, the SCK0 pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the asynchronous mode and the internal clock are selected (CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an external clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source, see table 17.10 in section 17.3, Operation. Bit 1: CKE1 0 Bit 0: CKE0 0 Description Asynchronous mode Clock synchronous mode 1 Asynchronous mode Clock synchronous mode 1 0 Asynchronous mode Clock synchronous mode 1 Asynchronous mode Clock synchronous mode Internal clock, SCK pin used for input pin (input 1 signal is ignored)* Internal clock, SCK pin used for synchronous clock 1 output* 2 Internal clock, SCK pin used for clock output* Internal clock, SCK pin used for synchronous clock output 3 External clock, SCK pin used for clock input* External clock, SCK pin used for synchronous clock input 3 External clock, SCK pin used for clock input* External clock, SCK pin used for synchronous clock input Notes: 1. Initial value 2. The output clock frequency is the same as the bit rate. 3. The input clock frequency is 16 times the bit rate. Rev. 5.00 Dec 12, 2005 page 494 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.2.7 Serial Status Register (SCSSR) Bit: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value: R/W: Note: * The only value that can be written is a 0 to clear the flag. The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating state. The CPU can always read and write the SCSSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SCSSR is initialized to H'84 by a reset or in standby and module standby modes. Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from the SCTDR into the SCTSR and new serial transmit data can be written in the SCTDR. Bit 7: TDRE 0 Description SCTDR contains valid transmit data [Clear condition] When software reads TDRE after it has been set to 1, then writes 0 in TDRE or data is written in SCTDR. 1 SCTDR does not contain valid transmit data [Setting conditions] 1. When the chip is reset or enters standby mode 2. When the TE bit in the serial control register (SCSCR) is cleared to 0 3. When SCTDR contents are loaded into SCTSR, so new data can be written in SCTDR. (Initial value) Rev. 5.00 Dec 12, 2005 page 495 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bit 6--Receive Data Register Full (RDRF): Indicates that SCRDR contains received data. Bit 6: RDRF 0 Description SCRDR does not contain valid received data [Clear conditions] 1. When the chip is reset or enters standby mode 2. When software reads RDRF after it has been set to 1, then writes 0 in RDRF. 1 SCRDR contains valid received data [Setting condition] When serial data is received normally and transferred from SCRSR to SCRDR. Note: The SCRDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost. (Initial value) Bit 5--Overrun Error (ORER): Indicates that data reception aborted due to an overrun error. Bit 5: ORER 0 Description 1 Receiving is in progress or has ended normally* (Initial value) [Clear conditions] 1. When the chip is reset or enters standby mode 1 2. When ORER=1 is read and then 0 is written to ORER. 2 A receive overrun error occurred* [Setting condition] When reception of the next serial data ends when RDRF is set to 1. Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. 2. SCRDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. Rev. 5.00 Dec 12, 2005 page 496 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bit 4--Framing Error (FER): Indicates that data reception aborted due to a framing error in the asynchronous mode. Bit 4: FER 0 Description Receiving is in progress or has ended normally* [Clear conditions] 1. When the chip is reset or enters standby mode 2. When FER=1 is read and then 0 is written to FER. 1 A receive framing error occurred FER is set to 1 if the stop bit at the end of receive data is checked and found to 2 be 0.* Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. 2. When the stop bit length is two bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the SCRDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. 1 (Initial value) Bit 3--Parity Error (PER): Indicates that data reception (with parity) aborted due to a parity error in the asynchronous mode. Bit 3: PER 0 Description Receiving is in progress or has ended normally* [Clear conditions] 1. When the chip is reset or enters standby mode 2. When PER=1 is read and then 0 is written to PER. 1 A receive parity error occurred* [Setting condition] When the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SCSMR). Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. 2. When a parity error occurs, the SCI transfers the receive data into the SCRDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. 2 1 (Initial value) Rev. 5.00 Dec 12, 2005 page 497 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, the SCTDR did not contain valid data, so transmission has ended. TEND is a readonly bit and cannot be written. Bit 2: TEND 0 Description Transmission is in progress [Clear condition] When TDRE=1 is read and then 0 is written to TDRE. 1 End of transmission [Setting conditions] 1. When the chip is reset or enters standby mode 2. When TE is cleared to 0 in the serial control register (SCSCR) 3. If TDRE is 1 when the last bit of a one-byte serial character is transmitted. (Initial value) Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a read-only bit and cannot be written. Bit 1: MPB 0 1 Description Multiprocessor bit value in receive data is 0* Multiprocessor bit value in receive data is 1 (Initial value) Note: * If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode. The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value) Rev. 5.00 Dec 12, 2005 page 498 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.2.8 Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR) The port SC control register (SCPCR) and port SC data register (SCPDR) control I/O and data for the port multiplexed with the serial communication interface (SCI) pins. SCPCR settings are used to perform I/O control, to enable data written in SCPDR to be output to the TxD0 pin, and input data to be read from the RxD0 pin, and to control serial transmission/reception breaks. It is also possible to read data on the SCK0 pin, and write output data. SCPCR Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: R/W: 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W SCPDR Bit: 7 SCP7DT Initial value: R/W: 0 R 6 SCP6DT 0 R/W 5 SCP5DT 0 R/W 4 SCP4DT 0 R/W 3 SCP3DT 0 R/W 2 SCP2DT 0 R/W 1 SCP1DT 0 R/W 0 SCP0DT 0 R/W SCI pin I/O and data control are performed by bits 3 to 0 of SCPCR and bits 1 and 0 of SCPDR. SCPCR Bits 3 and 2--Serial Clock Port I/O (SCP1MD1, SCP1MD0): These bits specify serial port SCK0 pin I/O. When the SCK0 pin is actually used as a port I/O pin, clear the C/A bit of SCSMR and bits CKE1 and CKE0 of SCSCR to 0. Bit 3: SCP1MD1 0 1 Bit 2: SCP1MD0 0 1 0 1 Description SCP1DT bit value is not output to SCK0 pin SCP1DT bit value is output to SCK0 pin SCK0 pin value is read from SCP1DT bit (Initial values: 1 and 0) Rev. 5.00 Dec 12, 2005 page 499 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) SCPDR Bit 1--Serial Clock Port Data (SCP1DT): Specifies the serial port SCK0 pin I/O data. Input or output is specified by the SCP1MD0 and SCP1MD1 bits. In output mode, the value of the SCP1DT bit is output from the SCK0 pin. Bit 1: SCP1DT 0 1 Description I/O data is low I/O data is high (Initial value) SCPCR Bits 1 and 0--Serial Port Break I/O (SCP0MD1, SCP0MD0): These bits specify the serial port TxD0 pin output condition. When the TxD0 pin is actually used as a port output pin and outputs the value set with the SCP0DT bit, clear the TE bit of SCSCR to 0. Bit 1: SCP0MD1 0 0 Bit 0: SCP0MD0 0 1 Description SCP0DT bit value is not output to TxD0 pin SCP0DT bit value is output to TxD0 pin (Initial value) SCPDR Bit 0--Serial Port Break Data (SCP0DT): Specifies the serial port RxD0 pin input data and TxD0 pin output data. The TxD0 pin output condition is specified by the SCP0MD0 and SCP0MD1 bits. When the TxD0 pin is set to output mode, the value of the SCP0DT bit is output to the TxD0 pin. The RxD0 pin value is read from the SCP0DT bit regardless of the values of the SCP0MD0 and SCP0MD1 bits, if RE in the SCSCR is set to 1. The initial value of this bit after a power-on reset is undefined. Bit 0: SCP0DT 0 1 Description I/O data is low I/O data is high (Initial value) Block diagrams of the SCI I/O ports are shown in figures 17.2 to 17.4. 17.2.9 Bit Rate Register (SCBRR) Bit: Initial value: R/W: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Rev. 5.00 Dec 12, 2005 page 500 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write the SCBRR. The SCBRR is initialized to H'FF by a reset or in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in two channels. The SCBRR setting is calculated as follows: Asynchronous mode: N = P 64 x 22n-1 x B P 8x2 2n-1 x 106 - 1 Clock synchronous mode: N = B: N: P: n: xB x 106 - 1 Bit rate (bit/s) SCBRR setting for baud rate generator (0 N 255) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 17.3.) Table 17.3 SCSMR Settings SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Note: Find the bit rate error for the asynchronous mode by the following formula: Error (%) = P x 106 (N + 1) x B x 64 x 22n-1 -1 x 100 Table 17.4 lists examples of SCBRR settings in the asynchronous mode; table 17.5 lists examples of SCBRR settings in the clock synchronous mode. Rev. 5.00 Dec 12, 2005 page 501 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) P (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) % -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 n 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 1 2.4576 Error (%) % -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (2) P (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 3.6864 Error (%) % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 Rev. 5.00 Dec 12, 2005 page 502 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (3) P (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 4.9152 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) % -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (4) P (MHz) Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 6.144 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 7.3728 Error (%) % -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 Rev. 5.00 Dec 12, 2005 page 503 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (5) P (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) % -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (6) P (MHz) 14.7456 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 Rev. 5.00 Dec 12, 2005 page 504 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.4 Bit Rates and SCBRR Settings in Asynchronous Mode (7) P (MHz) 24 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 Error (%) % -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 126 92 186 92 186 92 186 92 46 28 22 28.7 Error (%) % 0.31 0.46 -0.08 0.46 -0.08 0.46 -0.08 0.46 -0.61 -1.03 1.55 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) % 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 Rev. 5.00 Dec 12, 2005 page 505 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.5 Bit Rates and SCBRR Settings in Clock Synchronous Mode P (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 4 n -- 2 2 1 1 0 0 0 0 0 0 0 0 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- -- Notes: Settings with an error of 1% or less are recommended. Blank: No setting possible --: Setting possible, but error occurs. (Refer to section 17.2.9, Bit Rate Register (SCBRR)) *: Continuous transmit/receive not possible as transfer capability to the buffer becomes insufficient. Rev. 5.00 Dec 12, 2005 page 506 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.6 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used. Tables 17.7 and 17.8 list the maximum rates for external clock input. Table 17.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 5.00 Dec 12, 2005 page 507 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.7 Maximum Bit Rates during External Clock Input (Asynchronous Mode) P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 Table 17.8 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) P (MHz) 8 16 24 28.7 30 External Input Clock (MHz) 1.3333 2.6667 4.0000 4.7833 5.0000 Maximum Bit Rate (bits/s) 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0 Rev. 5.00 Dec 12, 2005 page 508 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.3 17.3.1 Operation Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission format are selected in the serial mode register (SCSMR), as listed in table 17.9. The SCI clock source is selected by the combination of the C/A bit in the serial mode register (SCSMR) and the CKE1 and CKE0 bits in the serial control register (SCSCR), as listed in table 17.10. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, overrun errors and breaks. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Clock Synchronous Mode: * The transmission/reception format has a fixed eight-bit data length. * In receiving, it is possible to detect overrun errors. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a synchronous clock signal to external devices. When an external clock is selected, the SCI operates on the input synchronous clock. The on-chip baud rate generator is not used. Rev. 5.00 Dec 12, 2005 page 509 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.9 Serial Mode Register Settings and SCI Communication Formats SCSMR Settings Bit 7 Bit 6 C/A CHR A 0 0 Bit 5 PE 0 1 1 0 1 0 1 1 * * * * * * * 1 Bit 2 MP 0 Bit 3 STOP 0 1 0 1 0 1 0 1 0 1 0 1 * Clock synchronous 8-bit Not set Asynchronous (multiprocessor format) 8-bit 7-bit Not set Set Set 7-bit Not set Set Mode Asynchronous SCI Communication Format Data Length 8-bit Parity Bit Not set Multipro- Stop Bit cessor Bit Length Not set 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Note: * Don't care. Table 17.10 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR Bit 7 C/A A 0 SCSCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 1 0 1 0 1 0 1 0 1 Clock synchronous mode Internal External Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK0 Pin Function SCI does not use the SCK0 pin Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Outputs the synchronous clock Inputs the synchronous clock Rev. 5.00 Dec 12, 2005 page 510 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.3.2 Operation in Asynchronous Mode In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 17.5 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idling (marking) 1 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 1 Stop bit 1 Serial data 0 Start bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 One unit of communication data (character or frame) Figure 17.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Transmit/Receive Formats Table 17.11 lists the 12 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Rev. 5.00 Dec 12, 2005 page 511 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Table 17.11 Serial Communication Formats (Asynchronous Mode) SCSMR Bits CHR 0 PE 0 MP STOP 0 0 1 START 2 Serial Transmit/Receive Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 START 8-bit data STOP STOP 0 1 0 0 START 8-bit data P STOP 0 1 0 1 START 8-bit data P STOP STOP 1 0 0 0 START 7-bit data STOP 1 0 0 1 START 7-bit data STOP STOP 1 1 0 0 START 7-bit data P STOP 1 1 0 1 START 7-bit data P STOP STOP 0 -- 1 0 START 8-bit data MPB STOP 0 -- 1 1 START 8-bit data MPB STOP STOP 1 -- 1 0 START 7-bit data MPB STOP 1 -- 1 1 START 7-bit data MPB STOP STOP Notes: --: START: STOP: P: MPB: Don't care bits Start bit Stop bit Parity bit Multiprocessor bit Rev. 5.00 Dec 12, 2005 page 512 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK0 pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 17.10). When an external clock is input at the SCK0 pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK0 pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 17.6 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 17.6 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 17.7 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is: Rev. 5.00 Dec 12, 2005 page 513 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Initialize Clear TE and RE bits in SCSCR to 0 Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Select transmit/receive format in SCSMR Set value to SCBRR Wait Has a 1-bit interval elapsed? Yes Set TE or RE in SCSCR to 1. Also set RIE, TIE, TEIE, and MPIE as necessary. (4) No (1) Select the clock source in the serial control register (SCSCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made to SCSCR. (2) Select the communication format in the serial mode register (SCSMR). (3) Write the value corresponding to the bit rate in the bit rate register (SCBRR) unless an external clock is used. (4) Wait at least one bit interval, then set TE or RE in the serial control register (SCSCR) to 1. Also set RIE, TIE, TEIE, and MPIE as necessary. Setting TE and RE enables the TxD and RxD pins to be used. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). (1) (2) (3) End Figure 17.7 Sample SCI Initialization Flowchart Rev. 5.00 Dec 12, 2005 page 514 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Serial Data Transmission (Asynchronous Mode): Figure 17.8 shows a sample flow chart for serial data transmission. After enabling the SCI transmission, transmit serial data following the procedure shown below: Start transmission Read TDRE bit in SCSSR (1) No TDRE = 1? Yes Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 (2) All data transmitted? Yes Read TEND bit in SCSSR (1) SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. (2) To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. No TEND = 1? Yes Break output? Yes Set SCPDR and SCPCR Clear TE bit SCSCR to 0 End transmission (3) No (3) To output a break at the end of serial transmission: Set the SC port data register (SCPDR) and SC port control register (SCPCR), then clear the TE bit to 0 in the serial control register (SCSCR). For SCPCR and SCPDR settings, see section 17.2.8, Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR). No Figure 17.8 Sample Serial Transmission Flowchart Rev. 5.00 Dec 12, 2005 page 515 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from the SCTDR into the transmit shift register (SCTSR). 2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCSCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: One or two 1 bits (stop bits) are output. e. Marking: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SCSSR, outputs the stop bit, then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 17.9 shows an example of SCI transmit operation in the asynchronous mode. Rev. 5.00 Dec 12, 2005 page 516 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 Idle 1 (marking) TDRE TEND TXI interrupt request generated Writes data to TXI interrupt SCTDR with the request TXI interrupt generated processing routine and clear TDRE bit to 0 1 frame TEI interrupt request generated Figure 17.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 5.00 Dec 12, 2005 page 517 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Serial Data Reception (Asynchronous Mode): Figure 17.10 shows a sample flow chart for serial data reception. After enabling the SCI reception, receive serial data following the procedure shown below: (1) Receive error processing and break detection: If a receive error occurs, read Read ORER, PER, and FER the ORER, PER and FER bits bits in SCSSR of the SCSSR to identify the error. After executing the necessary error processing, Yes PER, FER, ORER = 1? clear ORER, PER and FER all to 0. Receiving cannot resume if No ORER, PER or FER remain set (1) to 1. When a framing error Error processing occurs, the RxD pin can be read to detect the break state. Read the RDRF bit in SCSSR No (2) (2) SCI status check and receivedata read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. (3) To continue receiving serial data: Read the SCRDR receive data and clear the RDRF flag in SCSSR to 0 before the stop bit of the current frame is received. Start reception RDRF = 1? Yes Read reception data of SCRDR (3) and clear RDRF bit in SCSSR to 0 No All data received? Yes Clear the RE bit in SCSCR to 0 End reception Figure 17.10 Sample Serial Reception Data Flowchart (1) Rev. 5.00 Dec 12, 2005 page 518 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 Yes No PER = 1? Yes Parity error processing Clear ORER, PER, and FER bits in SCSSR to 0 End Figure 17.10 Sample Serial Reception Data Flowchart (2) Rev. 5.00 Dec 12, 2005 page 519 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into the SCRSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SCSMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from the SCRSR into the SCRDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the SCRDR. If one of the checks fails (receive error), the SCI operates as indicated in table 17.12. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCSCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 17.12 Receive Error Conditions and SCI Operation Receive Error Overrun error Framing error Parity error Abbreviation ORER FER PER Condition Receiving of next data ends while RDRF is still set to 1 in SCSSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SCSMR Data Transfer Receive data not loaded from SCRSR into SCRDR Receive data loaded from SCRSR into SCRDR Receive data loaded from SCRSR into SCRDR Figure 17.11 shows an example of SCI receive operation in the asynchronous mode. Rev. 5.00 Dec 12, 2005 page 520 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idling (marking) RDRF RXI interrupt request generated 1 frame Reads data with the RXI interrupt processing routine and clears RDRF bit to 0 ERI interrupt request generated by framing error FER Figure 17.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 17.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they Rev. 5.00 Dec 12, 2005 page 521 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 17.12 shows an example of communication among processors using the multiprocessor format. Transmitting station Serial communications circuit Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial data H'01 (MPB = 1) ID transmit cycle = specifies receiving station H'AA (MPB = 0) Data transmit cycle = data transmission to receiving station specified by ID MPB: Multiprocessor bit Figure 17.12 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Communication Formats Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 17.11. Clock See the description in the asynchronous mode section. Rev. 5.00 Dec 12, 2005 page 522 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Transmitting and Receiving Data Multiprocessor Serial Data Transmission: Figure 17.13 shows a sample flow chart for multiprocessor serial data transmission. After enabling the SCI transmission, transmit multiprocessor serial data following the procedure shown below: Start transmission Read TDRE bit in SCSSR (1) No TDRE = 1? Yes Write transmission data to SCTDR and set MPBT bit in SCSSR Clear TDRE bit to 0 (1) SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SCSSR. Finally, clear TDRE to 0. (2) To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. (2) Transmission ended? Yes Read TEND bit in SCSSR No TEND = 1? Yes Break output? Yes (3) Set SCPDR and SCPCR Clear TE bit SCSCR to 0 No No (3) To output a break at the end of serial transmission: Set the port SC data register (SCPDR) and port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register (SCSCR). For SCPCR and SCPDR settings, see section 17.2.8, Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR). End transmission Figure 17.13 Sample Multiprocessor Serial Transmission Flowchart Rev. 5.00 Dec 12, 2005 page 523 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from the SCTDR into the transmit shift register (SCTSR). 2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits are output, LSB first. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit: One or two 1 bits (stop bits) are output. e. Marking: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, outputs the stop bit, then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 17.14 shows SCI transmission in the multiprocessor format. Rev. 5.00 Dec 12, 2005 page 524 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 1 Serial data Start bit 0 D0 D1 Multiprocessor bit Stop Start Data bit bit D7 0/1 1 0 D0 D1 Multiprocessor bit Stop Data bit D7 0/1 1 Idling 1 (marking) TDRE TEND TXI interrupt request generated Writes data to TXI interrupt TDR with the TXI request interrupt progenerated cessing routine and clears TDRE bit to 0 1 frame TEI interrupt request generated Figure 17.14 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 5.00 Dec 12, 2005 page 525 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Multiprocessor Serial Data Reception: Figure 17.15 shows a sample flow chart for multiprocessor serial data reception. After enabling the SCI reception, receive multiprocessor serial data following the procedure shown below: Start reception Set MPIE bit in SCSCR to 1 Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR No Yes (1) (1) ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1. (2) SCI status check and compare to ID reception: Read the serial status register (SCSSR), check that RDRF is set to 1, then read data from the receive data register (SCRDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. (3) SCI status check and data receiving: Read SCSSR, check that RDRF is set to 1, then read data from the receive data register (SCRDR). (4) Receive error processing and break detection: If a receive error occurs, read the ORER and FER bits in SCSSR to identify the error. After executing the necessary error processing, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. (2) RDRF = 1? Yes Read receive data in SCRDR No Is ID the station's ID? Yes Read ORER and FER bits in SSCSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR RDRF = 1? Yes Read receive data in SCRDR (4) No Yes No All data received? Yes Clear RE bit in SCSCR to 0 End reception (3) Error processing Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 5.00 Dec 12, 2005 page 526 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 Yes Clear ORER and FER bits in SCSSR to 0 End Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 5.00 Dec 12, 2005 page 527 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Figure 17.16 shows an example of SCI receive operation using a multiprocessor format. Data (ID1) D0 D1 D7 Stop Start Data MPB bit bit (data 1) 1 1 0 D0 D1 D7 1 Serial data MPIE Start bit 0 Stop MPB bit 0 1 1 Idling (marking) RDRF RDR value RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 Reads RDR data with the RXI interrupt processing routine and clears RDRF bit to 0 ID1 ID is not station's No RXI interrupt, ID, so MPIE bit is generated set to 1 again RDR state is maintained (a) Own ID does not match data Start bit 0 Data (ID2) D0 D1 D7 Data Stop Start bit bit (Data 2) 1 0 D0 D1 D7 Stop MPB bit 0 1 1 Serial data MPIE MPB 1 1 Idling (marking) RDRF RDR value ID1 ID2 Data2 RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 Reads RDR data with the RXI interrupt processing routine and clears RDRF bit to 0 (b) Own ID matches data ID is that of station, so reception continues unchanged and data is received by the RXI interrupt processing routine MPIE bit set to 1 again Figure 17.16 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 5.00 Dec 12, 2005 page 528 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.3.4 Clock Synchronous Operation In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 17.17 shows the general format in clock synchronous serial communication. One unit of communication data (character or frame) * Synchronization clock * LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Note: * High except in continuous transmitting or receiving Figure 17.17 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In the clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising edge of the serial clock. Rev. 5.00 Dec 12, 2005 page 529 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Communication Format The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR). See table 17.10. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the SCI receives in 2character units, so a 16 pulse synchronization clock is output. To receive in 1-character units, select an external clock source. Transmitting and Receiving Data SCI Initialization (clock synchronous mode) Before transmitting and receiving data, the TE and RE bits in SCSCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 17.18. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and the transmit shift register (SCTSR) is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR. Figure 17.18 is a sample flowchart for initializing the SCI. Rev. 5.00 Dec 12, 2005 page 530 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Initialize Clear TE and RE bits in SCSCR to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0) (1) Select the clock source in the serial control register (SCSCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. (1) (2) Select the communication format in the serial mode register (SCSMR). (3) Write the value corresponding to the bit rate in the bit rate register (SCBRR) unless an external clock is used. (4) Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCSCR) to 1. Also set RIE, TIE, TEIE and MPIE. Setting TE and RE allows use of the TxD and RxD pins. Set transmit/receive format in SCSMR (2) Set value in SCBRR Wait Has a 1-bit period elapsed? Yes Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits (4) No (3) End Figure 17.18 Sample SCI Initialization Flowchart Rev. 5.00 Dec 12, 2005 page 531 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Serial Data Transmission (Clock Synchronous Mode): Figure 17.19 shows a sample flow chart for serial data transmission. After enabling the SCI transmission, transmit serial data following the procedure shown below: Start transmission Read TDRE bit in SCSSR No (1) TDRE = 1? Yes Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 (1) SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. (2) To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. All data transmitted? Yes Read TEND bit in SCSSR No (2) TEND = 1? Yes Clear TE bit in SCSCR to 0 End transmission No Figure 17.19 Sample Serial Transmission Flowchart Rev. 5.00 Dec 12, 2005 page 532 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data and loads this data from the SCTDR into the transmit shift register (SCTSR). 2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data are output from the TxD0 pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from the SCTDR into the SCTSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, transmits the MSB, then holds the transmit data pin (TxD0) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK0 pin is held in the high state. Figure 17.20 shows an example of SCI transmit operation. Transfer direction Synchronization clock Serial data LSB Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Writes data to TDR TXI interrupt with the TXI interrupt request request processing routine generated generated and clears TDRE bit to 0 1 frame TEI interrupt request generated Figure 17.20 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 5.00 Dec 12, 2005 page 533 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Serial Data Reception (Clock Synchronous Mode): Figure 17.21 shows a sample flow chart for serial data reception. After enabling the SCI transmission, transmit serial data following the procedure shown below: When switching from the asynchronous mode to the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. Start reception (1) Receive error processing: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. (2) SCI status check and receive data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. (3) To continue receiving serial data: Read SCRDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Read ORER bit in SCSSR Yes (1) Error processing (2) ORER = 1? No Read RDRF bit in SCSSR No RDRF = 1? Yes Read receive data in SCRDR and (3) clear RDRF bit in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End reception Figure 17.21 Sample Serial Reception Flowchart (1) Rev. 5.00 Dec 12, 2005 page 534 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Error processing No ORER = 1? Yes Overrun error processing Clear ORER bit in SCSSR to 0 End Figure 17.21 Sample Serial Reception Flowchart (2) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into the SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from the SCRSR into the SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in the SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 17.12. This state prevents further transmission or reception. While receiving, the RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 17.22 shows an example of the SCI receive operation. Rev. 5.00 Dec 12, 2005 page 535 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data RDRF ORER Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request generated Reads data with the RXI interrupt processing routine and clears RDRF bit to 0 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Figure 17.22 Example of SCI Operation in Reception Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode) Figure 17.23 shows a sample flowchart for simultaneous serial transmit and receive operations. After enabling the SCI transmission/reception, provide simultaneous serial transmit and receive operations following the procedure shown below: Rev. 5.00 Dec 12, 2005 page 536 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Start transmission/reception Read TDRE bit in SCSSR No (1) TDRE = 1? Yes Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 Read ORER bit in SCSSR Yes (2) Error processing (1) SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. (2) Receive error processing: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. (3) SCI status check and receive data read: Read the serial status register (SCSSR), check that RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. (4) To continue transmitting and receiving serial data: Read the RDRF bit and SCRDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. ORER = 1? No Read RDRF bit in SCSSR No (3) RDRF = 1? Yes Read receive data of SCRDR and clear RDRF bit in SCSSR to 0 (4) No All data transmitted/received? Yes Clear TE and RE bits in SCSCR to 0 End transmission/reception Note: When switching transmit or receive operation to simultaneous serial transmit and receive operations, first clear the TE bit and RE bit to 0, and then set both these bits to 1 simultaneously. Figure 17.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 5.00 Dec 12, 2005 page 537 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.4 SCI Interrupt Sources The SCI has four interrupt sources in each channel: Transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 17.13 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in the SCSSR is set to 1. RXI is requested when the RDRF bit in the SCSSR is set to 1. ERI is requested when the ORER, PER, or FER bit in the SCSSR is set to 1. TEI is requested when the TEND bit in the SCSSR is set to 1. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 17.13 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Low Priority When Reset Is Cleared High See section 4, Exception Handling, for information on the priority order and relationship to nonSCI interrupts. Rev. 5.00 Dec 12, 2005 page 538 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) 17.5 Usage Notes Note the following points when using the SCI. SCTDR Write and TDRE Flags: The TDRE bit in the serial status register (SCSSR) is a status flag indicating loading of transmit data from the SCTDR into the SCTSR. The SCI sets TDRE to 1 when it transfers data from the SCTDR to the SCTSR. Data can be written to the SCTDR regardless of the TDRE bit state. If new data is written in the SCTDR when TDRE is 0, however, the old data stored in the SCTDR will be lost because the data has not yet been transferred to the SCTSR. Before writing transmit data to the SCTDR, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 17.14 indicates the state of the SCSSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the SCRSR contents cannot be transferred to the SCRDR, so receive data is lost. Table 17.14 SCSSR Status Flags and Transfer of Receive Data SCSSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error RDRF 1 0 0 1 1 0 ORER 1 0 0 1 1 0 1 FER PER 0 1 0 1 0 1 1 0 0 1 0 1 1 1 Receive Data Transfer SCRSR SCRDR X O O X X O X Overrun error + framing error + parity error 1 X: Receive data is not transferred from SCRSR to SCRDR. O: Receive data is transferred from SCRSR to SCRDR. Break Detection and Processing: Break signals can be detected by reading the RxD0 pin directly when a framing error (FER) is detected. In the break state, the input from the RxD0 pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: The TxD0 pin I/O condition and level can be determined by means of the SCP0DT bit of the port SC data register (SCPDR) and bits SCP0MD0 and SCP0MD1 of the port SC control register (SCPCR). These bits can be used to send breaks. To send a break during serial transmission, clear the SCP0DT bit to 0 (designating low level), then clear the TE bit to 0 Rev. 5.00 Dec 12, 2005 page 539 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD0 pin. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is confirmed. Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Reception Margin in the Asynchronous Mode: In the asynchronous mode, the SCI operates on a base clock of 16 times the transfer rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 17.24). 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit -7.5 clocks +7.5 clocks D0 D1 Figure 17.24 Receive Data Sampling Timing in Asynchronous Mode Rev. 5.00 Dec 12, 2005 page 540 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) The reception margin in the asynchronous mode is given by formula 1. Formula 1: M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5)F - 2N N Where: M = Reception margin (%) N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0-1.0) L = Frame length (L = 9-12) F = Absolute deviation of clock frequency Assuming values of F = 0, D = 0.5 and N = 372 in formula (1), the reception margin is given by formula 2. Formula 2: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%. Cautions for Clock Synchronous External Clock Mode: * Set TE = RE = 1 only when the external clock SCK is 1. * Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed from 0 to 1. * When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the SCK input of the D7 bit in RxD, but it cannot be copied to SCRDR. Caution for Clock Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the SCK output of the D7 bit in RxD, but it cannot be copied to SCRDR. Rev. 5.00 Dec 12, 2005 page 541 of 1034 REJ09B0254-0500 Section 17 Serial Communication Interface (SCI) Rev. 5.00 Dec 12, 2005 page 542 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Section 18 Smart Card Interface 18.1 Overview As an additional serial communications interface function (SCI), an IC card (smart card) interface that is compatible to the ISO/IEC standard 7816-3 for identification of cards is supported. Register settings are used to switch between the ordinary serial communication interface and the smart card interface. 18.1.1 Features The smart card interface has the following features: * Asynchronous mode Data length: Eight bits Parity bit generation and check Receive mode error signal detection (parity error) Transmit mode error signal detection and automatic re-transmission of data Supports both direct convention and inverse convention * Bit rate can be selected using on-chip baud rate generator. * Three types of interrupts: Transmit-data-empty, receive-data-full, and communication-error interrupts are requested independently. Rev. 5.00 Dec 12, 2005 page 543 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the smart card interface. Bus interface Module data bus Internal data bus SCRDR SCTDR SCSCMR SCSSR SCSCR SCSMR Transmit/ receive control SCBRR RxD0 SCRSR SCTSR Baud rate generator P P/4 P/16 P/64 TxD0 Parity generation Parity check Clock External clock TXI RXI ERI SCK0 SCI Legend: SCSCMR: SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: SCSCR: SCSSR: SCBRR: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Figure 18.1 Smart Card Interface Block Diagram Rev. 5.00 Dec 12, 2005 page 544 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 18.1.3 Pin Configuration Table 18.1 summarizes the smart card interface pins. Table 18.1 SCI Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 I/O Output Input Output Function Clock output Receive data input Transmit data output 18.1.4 Register Configuration Table 18.2 summarizes the registers used by the smart card interface. The SCSMR, SCBRR, SCSCR, SCTDR, and SCRDR registers are the same as in the ordinary SCI function. They are described in section 17, Serial Communication Interface (SCI). Table 18.2 Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Abbreviation SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR R/W R/W R/W R/W R/W R R/W Initial Value* H'00 H'FF H'00 3 Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C Access Size 8 8 8 8 8 8 8 H'FF *1 H'84 R/(W) H'00 *2 Notes: 1. Only 0 can be written, to clear the flags. 2. Bits 0, 2, and 3 are cleared. The value of the other bits is undefined. 3. Initialized by a power-on or manual reset. Rev. 5.00 Dec 12, 2005 page 545 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 18.2 Register Descriptions This section describes the registers added for the smart card interface and the bits whose functions are changed. 18.2.1 Smart Card Mode Register (SCSCMR) The smart card mode register (SCSCMR) is an 8-bit read/write register that selects smart card interface functions. SCSCMR bits 0, 2, and 3 are initialized to H'00 by a reset and in standby mode. Bit: Initial value: R/W: 7 -- -- R 6 -- -- R 5 -- -- R 4 -- -- R 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- -- R 0 SMIF 0 R/W Bits 7 to 4 and 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3: SDIR 0 1 Description Contents of SCTDR are transferred as LSB first, receive data is stored in SCRDR as LSB first. (Initial value) Contents of SCTDR are transferred as MSB first, receive data is stored in SCRDR as MSB first. Bit 2--Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the data. This function is used in combination with bit 3 for transmitting and receiving with an inverse convention card. SINV does not affect the logic level of the parity bit. See section 18.3.4, Register Settings, for information on how parity is set. Bit 2: SINV 0 1 Description Contents of SCTDR are transferred unchanged, receive data is stored in SCRDR unchanged. (Initial value) Contents of SCTDR are inverted before transfer, receive data is inverted before storage in SCRDR. Rev. 5.00 Dec 12, 2005 page 546 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Bit 0--Smart Card Interface Mode Select (SMIF): Enables the smart card interface function. Bit 0: SMIF 0 1 Description Smart card interface function disabled Smart card interface function enabled (Initial value) 18.2.2 Serial Status Register (SCSSR) In the smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions for bit 2, the TEND bit, are also changed. Bit: Initial value: R/W: 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 0 R/(W)* 4 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W ORER FER/ERS Note: * Only 0 can be written, to clear the flag. Bits 7 to 5--These bits have the same function as in the ordinary SCI. See section 17, Serial Communication Interface (SCI), for more information. Bit 4--Error Signal Status (ERS): In the smart card interface mode, bit 4 indicates the state of the error signal returned from the receiving side during transmission. The smart card interface cannot detect framing errors. Bit 4: ERS 0 Description Receiving ended normally with no error signal. (Initial value) ERS is cleared to 0 when the chip is reset or enters standby mode, or when software reads ERS after it has been set to 1, then writes 0 in ERS. 1 An error signal indicating a parity error was transmitted from the receiving side. ERS is set to 1 if the error signal sampled is low. Note: The ERS flag maintains its state even when the TE bit in SCSCR is cleared to 0. Rev. 5.00 Dec 12, 2005 page 547 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Bits 3 to 0--These bits have the same function as in the ordinary SCI. See section 17, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows. Bit 2: TEND 0 Description Transmission is in progress. TEND is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE. 1 End of transmission. TEND is set to 1 when: * * * * the chip is reset or enters standby mode, the TE bit in SCSCR is 0 and the FER/ERS bit is also 0, the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after a one-byte serial character is transmitted, or the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after a one-byte serial character is transmitted. (Initial value) Note: etu: Elementary Time Unit (time for transfer of 1 bit) 18.3 18.3.1 Operation Overview The primary functions of the smart card interface are described below. 1. Each frame consists of 8-bit data and 1 parity bit. 2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: time for transfer of 1 bit) from the end of the parity bit to the start of the next frame. 3. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed from the start bit if a parity error was detected. 4. During transmission, it automatically transmits the same data after allowing at least 2 etu from the time the error signal is sampled. 5. Only start-stop type asynchronous communication functions are supported; no synchronous communication functions are available. Rev. 5.00 Dec 12, 2005 page 548 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 18.3.2 Pin Connections Figure 18.2 shows the pin connection diagram for the smart card interface. During communication with an IC card, transmission and reception are both carried out over the same data transfer line, so connect the TxD0 and RxD0 pins on the chip. Pull up the data transfer line to the power supply VCC side with a resistor. When using the clock generated by the smart card interface on an IC card, input the SCK pin output to the IC card's CLK pin. This connection is not necessary when the internal clock is used on the IC card. Use the chip's port output as the reset signal. Apart from these pins, the power and ground pin connections are usually also required. Note: When the IC card is not connected and both RE and TE are set to 1, closed communication is possible and auto-diagnosis can be performed. VCC TxD0 Data line RxD0 SCK0 Px (port) Clock line IO CLK LSI Reset line RST IC card Connected device Figure 18.2 Pin Connection Diagram for the Smart Card Interface 18.3.3 Data Format Figure 18.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. During transmission, error signals are sampled and data re-transmitted whenever an error signal is detected. Rev. 5.00 Dec 12, 2005 page 549 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface With no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output With parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 18.3 Data Format for Smart Card Interface The operating sequence is: 1. The data line is high impedance when not in use and is fixed high with a pull-up resistor. 2. The transmitting side starts one frame of data transmission. The data frame starts with a start bit (Ds, low level). The start bit is followed by eight data bits (D0 to D7) and a parity bit (Dp). 3. On the smart card interface, the data line returns to high impedance after this. The data line is pulled high with a pull-up resistor. 4. The receiving side checks parity. When the data is received normally with no parity errors, the receiving side then waits to receive the next data. When a parity error occurs, the receiving side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving station returns the signal line to high impedance after outputting the error signal for a specified period. The signal line is pulled high with a pull-up resistor. 5. The transmitting side transmits the next frame of data unless it receives an error signal. If it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. Rev. 5.00 Dec 12, 2005 page 550 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 18.3.4 Register Settings Table 18.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or 0 must be set to the indicated value. The settings for the other bits are described below. Table 18.3 Register Settings for the Smart Card Interface Register SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C Bit 7 C/A BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 FER/ ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Note: Dashes indicate unused bits. 1. Setting the serial mode register (SCSMR): The C/A bit selects the set timing of the TEND flag, and selects the clock output state with the combination of bits CKE1 and CKE0 in the serial control register (SCSCR). Set the O/E bit to 0 when the IC card uses the direct convention or to 1 when it uses the inverse convention. Select the on-chip baud rate generator clock source with the CKS1 and CKS0 bits (see section 18.3.5, Clock). 2. Setting the bit rate register (SCBRR): Set the bit rate. See section 18.3.5, Clock, to see how to calculate the set value. 3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do for the ordinary SCI0. See section 17, Serial Communication Interface (SCI), for more information. The CKE0 bit specifies the clock output. When no clock is output, set 0; when a clock is output, set 1. 4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both set to 0 for IC cards that use the direct convention and both to 1 when the inverse convention is used. The SMIF bit is set to 1 for the smart card interface. Figure 18.4 shows sample waveforms for register settings of the two types of IC cards (direct convention and inverse convention) and their start characters. In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and communication is LSB first. The start character data is H'3B. The parity bit is even (from the smart card standards), and thus 1. Rev. 5.00 Dec 12, 2005 page 551 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and communication is MSB first. The start character data is H'3F. The parity bit is even (from the smart card standards), and thus 0, which corresponds to state Z. Only data bits D7 to D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in SCSMR to odd parity mode. This applies to both transmission and reception. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State a. Direct convention (SDIR, SINV, and O/E are all 0) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State b. Inverse convention (SDIR, SINV, and O/E are all 1) Figure 18.4 Waveform of Start Character 18.3.5 Clock Only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. The bit rate for the clock is set by the bit rate register (SCBRR) and the CKS1 and CKS0 bits in the serial mode register (SCSMR), and is calculated using the equation below. Table 18.5 shows sample bit rates. If clock output is then selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the SCK0 pin. B= P 1488 x 22n-1 x (N + 1) x 106 Where: N = Value set in SCBRR (0 N 255) B = Bit rate (bit/s) P = Peripheral module operating frequency (MHz) n = 0 to 3 (table 18.4) Rev. 5.00 Dec 12, 2005 page 552 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Table 18.4 Relationship of n to CKS1 and CKS0 n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Table 18.5 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0) P (MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 13.00 17473.1 8736.6 5824.4 14.2848 19200.0 9600.0 6400.0 16.00 21505.4 10752.7 7168.5 18.00 24193.5 12096.8 8064.5 Note: The bit rate is rounded to two decimal places. Calculate the value to be set in the bit rate register (SCBRR) from the operating frequency and the bit rate. N is an integer in the range 0 N 255, specifying a smallish error. N= P x 106 - 1 1488 x 22n-1 x B Table 18.6 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0) (MHz) (9600 Bits/s) 7.1424 N 0 Error 0.00 N 1 10.00 Error 30.00 N 1 10.7136 Error 25.00 N 1 13.00 Error 8.99 N 1 14.2848 Error 0.00 N 1 16.00 Error 12.01 N 2 18.00 Error 15.99 Rev. 5.00 Dec 12, 2005 page 553 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Table 18.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 Maximum Bit Rate (Bit/s) 9600 13441 14400 17473 19200 21505 24194 N 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 The bit rate error is found as follows: Error (%) = ( P x 106 - 1) x 100 1488 x 22n-1 x B x (N + 1) Table 18.8 shows the relationship between transmit/receive clock register set values and output states on the smart card interface. Table 18.8 Register Set Values and SCK Pin Register Value Setting 1 *1 SMIF 1 C/A A 0 CKE1 0 CKE0 0 Output Port SCK Pin State Determined by setting of port register SCP1MD1 and SCP1MD0 bits SCK (serial clock) output state Low output High output Low output state SCK (serial clock) output state High output state SCK (serial clock) output state 1 2 *2 1 1 2 3* 0 1 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 Notes: 1. The SCK output state changes as soon as the CKE0 bit is modified. The CKE1 bit should be cleared to 0. 2. The clock duty remains constant despite stopping and starting of the clock by modification of the CKE0 bit. Rev. 5.00 Dec 12, 2005 page 554 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 18.3.6 Data Transmission and Reception Initialization: Initialize the SCI0 using the following procedure before sending or receiving data. Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. Figure 18.5 shows a flowchart of the initialization process (example). 1. Clear TE and RE in the serial control register (SCSCR) to 0. 2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SCSSR). 3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits) in the serial mode register (SCSMR). At this time also clear the CHR and MP bits to 0 and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR). When the SMIF bit is set to 1, the TxD and RxD pins both switch from ports to SCI0 pins and become high impedance. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR). 6. Set the clock source select bits (CKE1 and CKE0 bits) in the serial control register (SCSCR). Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock is output from the SCK pin. 7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and RE bits simultaneously unless performing auto-diagnosis. Rev. 5.00 Dec 12, 2005 page 555 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Initialize Clear TE and RE bits in SCSCR to 0 Clear SCSSR's FER/ERS, PER and ORER flags to 0 Set SCSMR's O/E bit to parity, set CKS1 and CKS0 bits to the clock and set C/A Set SCSMR's SMIF, SDIR, and SINV bits Set value in SCBRR Set SCSCR's CKE1 and CKE0 bits to the clock and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 Wait Has a 1-bit interval elapsed? Yes Set SCSCR's TIE, RIE, TE, and RE bits (7) No (1) (2) (3) (4) (5) (6) End Note: Numbers refer to the preceding procedure. Figure 18.5 Initialization Flowchart (Example) Rev. 5.00 Dec 12, 2005 page 556 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Serial Data Transmission: The processing procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission. This results in the transmission processing flowchart shown in figure 18.6 (example). 1. Initialize the smart card interface mode as described in initialization above. 2. Check that the FER/ERS bit in SCSSR is cleared to 0. 3. Repeat steps 2 and 3 until the TEND flag in SCSSR is set to 1. 4. Write the transmit data into SCTDR, clear the TDRE flag to 0 and start transmitting. The TEND flag will be cleared to 0. 5. To transmit more data, return to step 2. 6. To end transmission, clear the TE bit to 0. This processing can be interrupted. When the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested when the TEND flag is set to 1 at the end of the transmission. When the RIE bit is set to 1 and interrupt requests are enabled, a communication error interrupt (ERI) will be requested when the ERS flag is set to 1 when an error occurs in transmission. See Interrupt Operation below for more information. Rev. 5.00 Dec 12, 2005 page 557 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Start Initialize (1) Start transmission (2) No FER/ERS = 0? Yes Error processing No TEND = 1? Yes Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 No All data transmitted? Yes No (5) (4) (3) FER/ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCSCR to 0 (6) End transmission Note: Numbers refer to the preceding procedure. Figure 18.6 Transmission Flowchart (Example) Rev. 5.00 Dec 12, 2005 page 558 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Serial Data Reception: The processing procedures in the smart card mode are the same as in ordinary SCI processing. The reception processing flowchart is shown in figure 18.7 (example). 1. Initialize the smart card interface mode as described above in Initialization and in figure 18.5. 2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both to 0 after performing the appropriate error processing procedures. 3. Repeat steps 2 and 3 until the RDRF flag is set to 1. 4. Read the receive data from SCRDR. 5. To receive more data, clear the RDRF flag to 0 and return to step 2. 6. To end reception, clear the RE bit to 0. This processing can be interrupted. When the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested when the RDRF flag is set to 1 at the end of the reception. When an error occurs during reception and either the ORER or PER flag is set to 1, a communication error interrupt (ERI) will be requested. See Interrupt Operation below for more information. The received data will be transferred to SCRDR even when a parity error occurs during reception and PER is set to 1, so this data can still be read. Rev. 5.00 Dec 12, 2005 page 559 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Start Initialize (1) Start reception (2) No ORER = 0 or PER = 0? Yes Error processing No RDRF = 1? Yes Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 (6) (5) (4) (3) End reception Note: Numbers refer to the preceding procedure. Figure 18.7 Reception Flowchart (Example) Rev. 5.00 Dec 12, 2005 page 560 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization and setting RE to 0 and TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization and setting TE to 0 and RE to 1. The TEND flag can be used to check if transmission is completed. Interrupt Operation: In the smart card interface mode, there are three types of interrupts: transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode, the transmit-end interrupt (TEI) cannot be requested. Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI interrupt (table 18.9). Table 18.9 Smart Card Mode Operating State and Interrupt Sources Mode Transmit mode Receive mode State Normal Error Normal Error Flag TEND FER/ERS RDRF PER, ORER Mask Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI 18.4 Usage Notes When the SCI is used as a smart card interface, be sure that all criteria in sections 18.4.1, Receive Data Timing and Receive Margin in Asynchronous Mode and 18.4.2, Retransmission (Receive and Transmit Modes) are applied. 18.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode In asynchronous mode, the SCI runs on a basic clock with a frequency of 372 times the transfer rate. During reception, the SCI0 samples the falling of the start bit using the base clock to achieve internal synchronization. Receive data is latched internally on the rising edge of the 186th basic clock cycle (figure 18.8). Rev. 5.00 Dec 12, 2005 page 561 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 372 clock cycles 186 clock cycles 0 185 371 0 185 371 0 Base clock Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 18.8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation: For smart card mode: M = (0.5 - 1 D - 0.5 (1 + F) x 100% ) - (L - 0.5)F - 2N N Where: M = Receive margin (%) N = Ratio of bit rate to clock (N = 372) D = Clock duty (D = 0 to 1.0) L = Frame length (L = 10) F = Absolute value of clock frequency deviation Using this equation, the receive margin when F = 0 and D = 0.5 is as follows: M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev. 5.00 Dec 12, 2005 page 562 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface 18.4.2 Retransmission (Receive and Transmit Modes) Retransmission by the SCI in Receive Mode: Figure 18.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the PER bit before the next parity bit is sampled. 2. The RDRF bit in SCSSR is not set in the frame that caused the error. 3. When the received parity bit is checked and no error is found, the PER bit in SCSSR is not set. 4. When the received parity bit is checked and no error is found, reception is considered to have been completed normally and the RDRF bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an RXI interrupt is requested. 5. When a normal frame is received, the pin maintains a three-state state when it transmits the error signal. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransmitted frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n + 1 Ds D0 D1 D2 D3 D4 5 RDRF 2 PER 1 3 4 Figure 18.9 Retransmission in SCI Receive Mode Rev. 5.00 Dec 12, 2005 page 563 of 1034 REJ09B0254-0500 Section 18 Smart Card Interface Retransmission by the SCI in Transmit Mode: Figure 18.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the FER/ERS bit before the next parity bit is sampled. 2. The TEND bit in SCSSR is not set in the frame that received the error signal that indicated the error. 3. The FER/ERS bit in SCSSR is not set when no error signal is returned from the receiving side. 4. When no error signal is returned from the receiving side, the TEND bit in SCSSR is set to 1 when the transmission of the frame that includes the retransmission is considered completed. If the TIE bit in SCSCR is enabled at this time, a TXI interrupt will be requested. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransmitted frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n + 1 Ds D0 D1 D2 D3 D4 TDRE Transfer from SCTDR to SCTSR TEND 2 FER/ERS 1 Transfer from SCTDR to SCTSR 4 3 Transfer from SCTDR to SCTSR Figure 18.10 Retransmission in SCI Transmit Mode Rev. 5.00 Dec 12, 2005 page 564 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Section 19 Serial Communication Interface with FIFO (SCIF) 19.1 Overview This LSI has one-channel serial communication interface with FIFO (SCIF) that supports asynchronous serial communication. It also has 16-stage FIFO registers for both transfer and receive that enables this LSI efficient high-speed continuous communication. 19.1.1 Features * Asynchronous serial communication: Serial data communications are performed by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats. Data length: Seven or eight bits Stop bit length: One or two bits Parity: Even, odd, or none Receive error detection: Parity and framing errors Break detection: Break is detected when the receive data next the generated framing error is the space 0 level and has the framing error. It is also detected by reading the RxD level directly from the port SC data register (SCPDR) when a framing error occurs * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal transmit/receive clock source * Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. The direct memory access controller (DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receiveFIFO-data-full interrupt. * When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. * On-chip modem control functions (RTS2 and CTS2) Rev. 5.00 Dec 12, 2005 page 565 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) * The quantity of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be known. * The time-out error (DR) can be detected in receiving. 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the SCIF. Bus interface Module data bus Internal data bus SCFRDR2 (16stages) SCFTDR2 (16stages) RxD2 SCRSR2 SCTSR2 TxD2 SCPCR2 SCFDR2 SCFDR2 SCFCR2 SCSSR2 SCSCR2 SCSMR2 Transmit/ receive control SCBRR2 Baud rate generator P P/4 P/16 P/64 Parity generation Parity check Clock RTS2 CTS2 SCIF ERI TXI BRI BRI Legend: SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: Receive shift register 2 Receive FIFO data register 2 Transmit shift register 2 Transmit FIFO data register 2 Serial mode register 2 Serial control register 2 SCSSR2: SCBRR2: SCFCR2: SCFDR2: SCPDR2: SCPCR2: Serial status register 2 Bit rate register 2 FIFO control register 2 FIFO data count set register 2 Port SC data register 2 Port SC control register 2 Figure 19.1 SCIF Block Diagram Rev. 5.00 Dec 12, 2005 page 566 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Figures 19.2 and 19.3 show SCIF I/O ports. Bits 15, 14, 9, 8 of SCPCR and bits 7 and 4 of SCPDR control an input/output and data of the SCIF pins. See section 26.3.13, SC Port Control Register (SCPCR) for more details. Reset R D SCP4MD0 Q C PCRW Reset SCP4MD1 C PCRW Reset SCPT[4]/TxD2 R Q D SCP4DT1 C PDRW Internal data bus Q R D SCIF Output enable Serial transmission output Legend: PCRW: SCPCR write PDRW: SCPDR write Figure 19.2 SCPT[4]/TxD2 Pin Rev. 5.00 Dec 12, 2005 page 567 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) SCIF Internal data bus SCPT[4]/RxD2 Serial receive data Legend: PDRR: SCPDR read PDRR* Note: * When reading the RxD2 pin, set the RE bit in SCSCR2 to 1. Figure 19.3 SCPT[4]/RxD2 Pin 19.1.3 Pin Configuration The SCIF has the serial pins summarized in table 19.1. Table 19.1 SCIF Pins Pin Name Receive data pin Transmit data pin Request to send pin Clear to send pin Abbreviation RxD2 TxD2 RTS2 CTS2 I/O Input Output Output Input Function Receive data input Transmit data output Request to send Clear to send Rev. 5.00 Dec 12, 2005 page 568 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.1.4 Register Configuration Table 19.2 summarizes the SCIF internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 19.2 Registers Register Name Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit FIFO data register 2 Serial status register 2 Receive FIFO data register 2 FIFO control register 2 FIFO data count set register 2 Abbreviation SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCSSR2 SCFRDR2 SCFCR2 SCFDR2 R/W R/W R/W R/W W R/(W)* R R/W R 1 Initial Value H'00 H'FF H'00 -- H'0060 Address Access Size 8 bits H'04000150 2 (H'A4000150)* H'04000152 8 bits 2 (H'A4000152)* H'04000154 8 bits 2 (H'A4000154)* H'04000156 8 bits 2 (H'A4000156)* H'04000158 16 bits 2 (H'A4000158)* Undefined H'0400015A 8 bits 2 (H'A400015A)* H'00 H'0000 H'0400015C 8 bits 2 (H'A400015C)* H'0400015E 16 bits 2 (H'A400015E)* Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Only 0 can be written to clear the flag. 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 569 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.2 19.2.1 Register Descriptions Receive Shift Register 2 (SCRSR2) The receive shift register 2 (SCRSR2) receives serial data. Data input at the RxD2 pin is loaded into the SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the SCFRDR2, which is a receive FIFO data register 2. The CPU cannot read or write the SCRSR2 directly. Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- 19.2.2 Receive FIFO Data Register 2 (SCFRDR2) The 16-byte receive FIFO data register 2 (SCFRDR2) stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register 2 (SCRSR2) into the SCFRDR2 for storage. Continuous receive is enabled until 16 bytes are stored. The CPU can read but not write the SCFRDR2. When data is read without received data in the SCFRDR2, the value is undefined. When the received data in this register becomes full, the subsequent serial data is lost. Bit: R/W: 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 R Rev. 5.00 Dec 12, 2005 page 570 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.2.3 Transmit Shift Register 2 (SCTSR2) The transmit shift register 2 (SCTSR2) transmits serial data. The SCI loads transmit data from the transmit FIFO data register 2 (SCFTDR2) into the SCTSR2, then transmits the data serially from the TxD2 pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from the SCFTDR2 into the SCTSR2 and starts transmitting again. The CPU cannot read or write the SCTSR2 directly. Bit: R/W: 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- 19.2.4 Transmit FIFO Data Register 2 (SCFTDR2) The transmit FIFO data register 2 (SCFTDR2) is a 16-byte 8-bit-length FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR2) is empty, it moves transmit data written in the SCFTDR2 into the SCTSR2 and starts serial transmission. Continuous serial transmission is performed until the transmit data in the SCFTDR2 becomes empty. The CPU can always write to the SCFTDR2. When the transmit data in the SCFTDR2 is full (16 bytes), next data cannot be written. If attempted to write, the data is ignored. Bit: R/W: 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W Rev. 5.00 Dec 12, 2005 page 571 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.2.5 Serial Mode Register 2 (SCSMR2) The serial mode register 2 (SCSMR2) is an eight-bit register that specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SCSMR2. The SCSMR2 is initialized to H'00 by a reset or in standby and module standby modes. Bit: Initial value: R/W: 7 -- 0 R 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 -- 0 R 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7--Reserved: This bit always read 0. The write value should always be 0. Bit 6--Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode. Bit 6: CHR 0 1 Description Eight-bit data. Seven-bit data. * (Initial value) Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit FIFO data register 2 is not transmitted. Bit 5--Parity Enable (PE): Selects whether or not to add a parity bit to transmit data and to check the parity of receive data. Bit 5: PE 0 1 Description Parity bit not added or checked. Parity bit added and checked. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. (Initial value) Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. E The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored when parity addition and check is disabled. Rev. 5.00 Dec 12, 2005 page 572 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Bit 4: O/E E 0 Description Even parity. (Initial value) If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 Odd parity. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP 0 1 Description One stop bit. Two stop bits. In transmitting, two bits of 1 are added at the end of each transmitted character. (Initial value) In transmitting, a single bit of 1 is added at the end of each transmitted character. Bit 2--Reserved: This bit is always read as 0. The write value should always be 0. Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available. P, P/4, P/16 and P/64. For further information on the clock source, bit rate register 2 settings, and baud rate, see section 19.2.8, Bit Rate Register 2 (SCBRR2). Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Note: P: Peripheral clock Description P clock P/4 clock P/16 clock P/64 clock (Initial value) Rev. 5.00 Dec 12, 2005 page 573 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.2.6 Serial Control Register 2 (SCSCR2) The serial control register 2 (SCSCR2) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCSCR2. The SCSCR2 is initialized to H'00 by a reset or in standby and module standby modes. Bit: Initial value: R/W: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 -- 0 R 2 -- 0 R 1 CKE1 0 R/W 0 CKE0 0 R/W Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when serial transmit data is transferred from transmit FIFO data register 2 (SCFTDR2) to transmit shift register 2 (SCTSR2), when the quantity of data in transmit FIFO register 2 becomes less than the specified number of transmission triggers, and when the TDFE flag in serial status register 2 (SCSSR2) is set to1. Bit 7: TIE 0 1 Description Transmit-FIFO-data-empty interrupt request (TXI) is disabled.* Transmit-FIFO-data-empty interrupt request (TXI) is enabled (Initial value) Note: * The TXI interrupt request can be cleared by writing the greater quantity of transmit data than the specified number of transmission triggers to SCFTDR2 and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and receive-error (ERI) interrupts requested when serial receive data is transferred from receive shift register 2 (SCRSR2) to receive FIFO data register 2 (SCFRDR2), when the quantity of data in receive FIFO register 2 becomes more than the specified number of receive triggers, and when the RDRF flag in SCSSR2 is set to1. Bit 6: RIE 0 1 Description Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and receive break interrupt (BRI) requests are disabled.* (Initial value) Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled. Note: * RXI and ERI interrupt requests can be cleared by reading the DR, ER, or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. At RDF, read 1 from the RDF flag and clear it to 0, after reading the received data from SCFRDR2 until the quantity of received data becomes less than the specified number of the receive triggers. Rev. 5.00 Dec 12, 2005 page 574 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Bit 5--Transmit Enable (TE): Enables or disables the SCIF serial transmitter. Bit 5: TE 0 1 Description Transmitter disabled. Transmitter enabled. * (Initial value) Note: * Serial transmission starts after writing of transmit data into the SCFTDR2. Select the transmit format in the SCSMR2 and SCFCR2 and reset the SCFTDR2 before setting TE to 1. Bit 4--Receive Enable (RE): Enables or disables the SCIF serial receiver. Bit 4: RE 0 1 Description Receiver disabled.* 2 Receiver enabled.* 1 (Initial value) Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, FER, and PER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected. Select the receive format in the SCSMR2 before setting RE to 1. Bits 3 and 2--Reserved: These bits are always read as 0. The write value should always be 0. Bits 1 and 0--Clock Enable 1 and 0 (CKE1 and CKE0): These bits should always be set to 00. Rev. 5.00 Dec 12, 2005 page 575 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.2.7 Serial Status Register 2 (SCSSR2) Serial status register 2 (SCSSR2) is a 16-bit register. The upper 8 bits indicate the number of receive errors in the data of receive FIFO data register 2, and the lower 8 bits indicate SCIF operating state. The CPU can always read and write the SCSSR2, but cannot write 1 in the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. The SCSSR2 is initialized to H'0060 by a reset or in standby and module standby modes. Lower 8 bits: Initial value: R/W: 7 ER 0 R/(W)* 6 TEND 1 R/(W)* 5 TDFE 1 R/(W)* 4 BRK 0 R/(W)* 3 FER 0 R 2 PER 0 R 1 RDF 0 R/(W)* 0 DR 0 R/(W)* Note: * The only value that can be written is 0 to clear the flag. Bit 7--Receive Error (ER): Indicates that a parity error has occurred when received data includes a framing error or a parity. Bit 7: ER 0 Description Receive is in progress, or receive is normally completed.* 1 (Initial value) ER is cleared to 0 when the chip is reset or enters standby mode, or when 0 is written after 1 is read from ER. 1 A framing error or a parity error has occurred. ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit 2 of the received data is 1 at the end of one-data receive* , or when the total number of 1's in the received data and in the parity bit does not match the even/odd parity specification specified by the O/E bit of the SCSMR2. Notes: 1. Clearing the RE bit to 0 in SCSCR2 does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the received data is transferred to SCFRDR2 and the receive operation is continued. Whether or not the data read from SCFRDR2 includes a receive error can be detected by the FER and PER bits of SCSSR2. 2. In the stop mode, only the first stop bit is checked; the second stop bit is not checked. Rev. 5.00 Dec 12, 2005 page 576 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Bit 6--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, the SCFTDR2 did not contain valid data, so transmission has ended. Bit 6: TEND 0 1 Description Transmission is in progress. TEND is cleared to 0 when data is written in SCFTDR2. End of transmission. (Initial value) TEND is set to 1 when the chip is reset or enters standby mode, TE is cleared to 0 in the serial control register (SCSCR2), or when SCFTDR2 does not contain received data when the last bit of a one-byte serial character is transmitted. Bit 5--Transmit FIFO Data Empty (TDFE): Indicates that data is transferred from transmit FIFO data register 2 (SCFTDR2) to transmit shift register (SCTSR), the quantity of data in SCFTDR2 becomes less than the number of transmission triggers specified by the TTRG1 and TTRG0 bits in FIFO control register 2 (SCFCR2), and writing the transmit data to SCFTDR2 is enabled. Bit 5: TDFE 0 Description The quantity of transmit data written to SCFTDR2 is greater than the specified number of transmission triggers. (Initial value) TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR2, and software reads 1 from TDFE and then writes 0 to TDFE. 1 The quantity of transmit data in SCFTDR2 is less than the specified number of transmission triggers.* TDFE is set to 1 at reset or at standby mode, or when the quantity of transmission data in SCFTDR2 becomes less than the specified number of transmission triggers as a result of transmission. Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be written when TDFE is 1 is "16 minus the specified number of transmission triggers." If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR2 is indicated by the upper 8 bits of SCFTDR2. Rev. 5.00 Dec 12, 2005 page 577 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Bit 4--Break Detection (BRK): Indicates that a break signal is detected in received data. Bit 4: BRK 0 Description No break signal is being received. (Initial value) BRK is cleared to 0 when the chip is reset or enters standby mode, or software reads BRK after it has been set to 1, then writes 0 in BRK. 1 The break signal is received.* BRK is set to 1 when data including a framing error is received and a framing error occurs with space 0 in the subsequent received data. Note: * When a break is detected, transfer of the received data (H'00) to SCFRDR2 stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of the received data resumes. The received data of a frame in which a break signal is detected is transferred to SCFRDR2. After this, however, no received data is transferred until a break ends with the received signal being mark 1 and the next data is received. Bit 3--Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data register 2 (SCFRDR2). Bit 3: FER 0 Description No receive framing error occurred in the data read from SCFRDR2. (Initial value) FER is cleared to 0 when the chip is power-on reset or enters standby mode, or when no framing error is present in the data read from SCFRDR2. 1 A receive framing error occurred in the data read from SCFRDR2. FER is set to 1 when a framing error is present in the data read from SCFRDR2. Bit 2--Parity Error (PER): Indicates a parity error in the data read from the receive FIFO data register 2 (SCFRDR2). Bit 2: PER 0 Description No receive parity error occurred in the data read from SCFRDR2. (Initial value) PER is cleared to 0 when the chip is power-on reset or enters standby mode, or when no parity error is present in the data read from SCFRDR2. 1 A receive parity error occurred in the data read from SCFRDR2. PER is set to 1 when a parity error is present in the data read from SCFRDR2. Rev. 5.00 Dec 12, 2005 page 578 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Bit 1--Receive FIFO Data Full (RDF): Indicates that received data is transferred to the receive FIFO data register 2 (SCFRDR2), the quantity of data in SCFRDR2 becomes more than the number of receive triggers specified by the RTRG1 and RTRG0 bits in FIFO control register 2 (SCFCR2). Bit 1: RDF 0 Description The quantity of transmit data written to SCFRDR2 is less than the specified number of receive triggers. (Initial value) RDF is cleared to 0 at power-on reset or in standby mode, or when SCFRDR2 is read until the quantity of receive data in SCFRDR2 is less than the specified receive trigger number, and software reads 1 from RDF and then writes 0 to RDF. 1 The quantity of receive data in SCFRDR2 is more than the specified number of receive triggers. RDF is set to 1 when the quantity of receive data which is greater than the specified number of receive triggers is stored in SCFRDR2.* Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be read when RDF is 1 is the specified number of receive triggers. If attempted to read after all data in the SCFRDR2 have been read, the data is undefined. The quantity of receive data in SCFRDR2 is indicated by the lower 8 bits of SCFTDR2. Bit 0--Receive Data Ready (DR): Indicates that the receive FIFO data register 2 (SCFRDR2) stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 ETU has elapsed from the last stop bit. Bit 0: DR 0 Description Receive is in progress, or no received data remains in SCFRDR2 after completing receive normally. (Initial value) DR is cleared to 0 when the chip is power-on reset or enters standby mode, or software reads DR after it has been set to 1, then writes 0 in DR. 1 Next receive data is not received. DR is set to 1 when SCFRDR2 stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 ETU has elapsed from the last stop bit.* Note: * This is equivalent to 1.5 frames with the 8-bit 1-stop-bit format. (ETU: Element Time Unit) Rev. 5.00 Dec 12, 2005 page 579 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Upper 8 bits: Initial value: R/W: 15 PER3 0 R 14 PER2 0 R 13 PER1 0 R 12 PER0 0 R 11 FER3 0 R 10 FER2 0 R 9 FER1 0 R 8 FER0 0 R Bits 15 to 12--Number of Parity Errors 3 to 0 (PER3 to PER0): Indicates the quantity of data including a parity error in the received data stored in the receive FIFO data register 2 (SCFRDR2). The value indicated by the bits 15 to 12 represents the number of parity errors in SCFRDR2. Bits 11 to 8--Number of Framing Errors 3 to 0 (FER3 to FER0): Indicates the quantity of data including a framing error in the received data stored in SCFRDR2. The value indicated by bits 11 to 8 represents the number of framing errors in SCFRDR2. 19.2.8 Bit Rate Register 2 (SCBRR2) The bit rate register 2 (SCBRR2) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register 2 (SCSMR2), determines the serial transmit/receive bit rate. The CPU can always read and write the SCBRR2. The SCBRR2 is initialized to H'FF by a reset or in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in two channels. Bit: Initial value: R/W: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W The SCBRR2 setting is calculated as follows: Asynchronous mode: N= B: N: P: n: P 64 x 22n-1 x B x 106 - 1 Bit rate (bit/s) SCBRR2 setting for baud rate generator (0 N 255) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 19.3.) Rev. 5.00 Dec 12, 2005 page 580 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.3 SCSMR2 Settings SCSMR2 Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Note: Find the bit rate error by the following formula: P x 106 - 1 Error (%) = (N+1) x 64 x 22n-1 x B x 100 Table 19.4 lists examples of SCBRR2 settings. Table 19.4 Bit Rates and SCBRR2 Settings P (MHz) 2 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 0 Error (%) n % -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 1 2.4576 Error (%) % -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 Rev. 5.00 Dec 12, 2005 page 581 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) P (MHz) 3 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 47 23 11 5 3 2 3.6864 Error (%) n % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -7.84 0.00 P (MHz) 4.9152 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) n % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) n % -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) % -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 2 1 1 0 0 0 0 0 0 0 0 4 N 70 207 103 207 103 51 25 12 6 3 2 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 Rev. 5.00 Dec 12, 2005 page 582 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) P (MHz) 6.144 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) n % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 P (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 1 Error (%) % 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 2 2 1 1 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) % 0.16 0.16 0.16 0.16 0.16 0.16 1.73 0.00 1.73 n 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 19 9 4 2 9 12 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 2 1 1 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 7.3728 Error (%) n % -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 -0.26 2 -0.25 1 -1.36 0 -1.70 0 -2.34 0 Rev. 5.00 Dec 12, 2005 page 583 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) P (MHz) 14.7456 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 115200 500000 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 3 0 Error (%) % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 3 0 16 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 8.51 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 4 0 Error (%) % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 6.67 22.9 n 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 4 0 20 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 8.51 25.0 -1.70 0 -1.70 0 -7.84 0 P (MHz) 24 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 115200 500000 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 6 1 Error (%) % 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 3 2 2 1 1 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 6 1 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 3 2 2 1 1 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 7 1 Error (%) % 0.31 0.46 0.46 0.46 0.46 n 3 3 2 1 0 N 132 97 194 97 194 97 194 97 48 29 23 7 1 30 Error (%) % 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 1.73 -6.25 -0.44 3 -0.08 2 -0.08 1 -0.08 0 -0.61 0 -1.03 0 1.55 0 -2.68 0 -10.3 0 -1.70 0 -4.76 0 -23.2 0 -2.34 0 -6.99 0 -25.0 0 Rev. 5.00 Dec 12, 2005 page 584 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used. Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 5.00 Dec 12, 2005 page 585 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.2.9 FIFO Control Register 2 (SCFCR2) Bit: Initial value: R/W: 7 RTRG1 0 R/W 6 RTRG0 0 R/W 5 TTRG1 0 R/W 4 TTRG0 0 R/W 3 MCE 0 R/W 2 TFRST 0 R/W 1 RFRST 0 R/W 0 LOOP 0 R/W The FIFO control register 2 (SCFCR2) resets the number of data in the transmit and receive FIFO register 2, sets the number of trigger data, and contains the permit bit for the loop back test. The SCFCR2 is always read and written by the CPU. It is initialized to H'00 by the reset, the module standby function, or in the standby mode. Bits 7 and 6--Trigger of the Number of Receive FIFO Data (RTRG1 and RTRG0): Set the number of receive data which sets the receive data full (RDF) flag in the serial status register 2 (SCSSR2). These bits set the RDF flag when the number of receive data stored in the receive FIFO register 2 (SCFRDR2) is increased more than the number of setting triggers listed below. Bit 7: RTRG1 0 1 Bit 6: RTRG0 0 1 0 1 Number of Received Triggers 1 4 8 14 (Initial value) Bits 5 and 4--Trigger of the Number of Transmit FIFO Data (TTRG1 and TTRG0): Set the number of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register 2 (SCSSR2). These bits set the TDFE flag when the number of transmit data in the transmit FIFO data register 2 (SCFTDR2) is decreased less than the number of setting triggers listed below. Bit 5: TTRG1 0 1 Bit 4: TTRG0 0 1 0 1 Number of Transmitted Triggers 8 (8)* 4 (12) 2 (14) 1 (15) Note: * Initial value. Values in brackets mean the number of empty SCFTDR2 when a flag occurs. Rev. 5.00 Dec 12, 2005 page 586 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Bit 3--Modem Control Enable (MCE): Enables the modem control signals CTS and RTS. Bit 3: MCE 0 1 Description Disables the modem signal* Enables the modem signal (Initial value) Note: * The CTS is fixed to active 0 regardless of the input value, and the RTS is also fixed to 0. Bit 2--Transmit FIFO Data Register Reset (TFRST): Disables the transmit data in the transmit FIFO data register 2 and resets the data to the empty state. Bit 2: TFRST 0 1 Description Disables reset operation* Enables reset operation (Initial value) Note: * Reset is operated in resets or the standby mode. Bit 1--Receive FIFO Data Register Reset (RFRST): Disables the receive data in the receive FIFO data register 2 and resets the data to the empty state. Bit 1: RFRST 0 1 Description Disables reset operation* Enables reset operation (Initial value) Note: * Reset is operated in resets or the standby mode. Bit 0--Loop Back Test (LOOP): Internally connects the transmit output pin (TXD2) and receive input pin (RXD2) and enables the loop back test. Bit 0: LOOP 0 1 Description Disables the loop back test Enables the loop back test (Initial value) Rev. 5.00 Dec 12, 2005 page 587 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.2.10 FIFO Data Count Set Register 2 (SCFDR2) The SCFDR2 is a 16-bit register which indicates the number of data stored in the transmit FIFO data register 2 (SCFTDR2) and the receive FIFO data register 2 (SCFRDR2). It indicates the number of transmit data in the SCFTDR2 with the upper eight bits, and the number of receive data in the SCFRDR2 with the lower eight bits. The SCFDR2 is always read from the CPU. Upper 8 Bits: Initial value: R/W: 15 -- 0 R 14 -- 0 R 13 -- 0 R 12 T4 0 R 11 T3 0 R 10 T2 0 R 9 T1 0 R 8 T0 0 R The SCFDR2 indicates the number of non-transmitted data stored in the SCFTDR2. The H'00 means no transmit data, and the H'10 means that the full of transmit data are stored in the SCFTDR2. Lower 8 Bits: Initial value: R/W: 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 R4 0 R 3 R3 0 R 2 R2 0 R 1 R1 0 R 0 R0 0 R The SCFDR2 indicates the number of receive data stored in the SCFRDR2. The H'00 means no receive data, and the H'10 means that the full of receive data are stored in the SCFRDR2. Rev. 5.00 Dec 12, 2005 page 588 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.3 19.3.1 Operation Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually. Refer to section 17.3.2, Operation in Asynchronous Mode. The SCIF has the 16-byte FIFO buffer for both transmit and receive, reduces an overhead of the CPU, and enables continuous high-speed communication. Moreover, it has the RTS and CTS signals as the modem control signals. The transmission format is selected in the serial mode register 2 (SCSMR2), as listed in table 19.6. The clock source of SCIF is determined by the combination of CKE1 and CKE0 bits in the serial control register 2 (SCSCR2) as shown in table 19.7. * Data length is selectable from seven or eight bits. * Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO data full, receive data ready, and breaks. * In transmitting, it is possible to detect transmit FIFO data empty. * The number of stored data for both the transmit and receive FIFO registers is displayed. * SCIF clock source The SCIF operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency 16 times the bit rate. Table 19.6 SCSMR2 Settings and SCIF Transmit/Receive SCSMR2 Settings Mode Asynchronous Bit 6 CHR 0 Bit 5 PE 0 1 1 0 1 Bit 3 STOP 0 1 0 1 0 1 0 1 Set 7-bit Not set Set Data Length 8-bit SCIF Transmit/Receive Parity Bit Not set Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits Rev. 5.00 Dec 12, 2005 page 589 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.7 Settings for SCSMR2 and SCSCR2 and Selection of Clock Source of SCIF SCSCR2 Settings Mode Asynchronous Bit 1 CKE1 0 1 Bit 0 CKE0 0 1 0 1 External SCIF Transmit/Receive Clock Clock Source Internal Functions of SCK2 Pins SCIF does not use SCK2 pins. Inhibited Inhibited 19.3.2 Serial Operation Transmit/Receive Formats: Table 19.8 lists eight communication formats that can be selected. The format is selected by settings in the serial mode register (SCSMR2). Table 19.8 Serial Transmit/Receive Formats SCSMR2 Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 STOP 0 1 0 1 0 1 0 1 1 START START START START START START START START Start bit Stop bit Parity bit Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP STOP STOP STOP 11 12 8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data Notes: START: STOP: P: Rev. 5.00 Dec 12, 2005 page 590 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Transmitting and Receiving Data (SCIF Initialization): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register 2 (SCSCR2), then initialize the SCIF as follows. When changing the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register 2 (SCTSR2). Clearing TE and RE to 0, however, does not initialize the serial status register 2 (SCSSR2), transmit FIFO data register 2 (SCFTDR2), or receive FIFO data register 2 (SCFRDR2), which retain their previous contents. Clear TE to 0 after all transmit data are transmitted and the TEND flag in the SCSSR2 is set. The transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared to 0 in transmitting. Set the TFRST bit in the SCFCR2 to 1 and reset the SCFTDR2 before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped. Rev. 5.00 Dec 12, 2005 page 591 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.4 is a sample flowchart for initializing the SCIF. The procedure for initializing the SCIF is: Initialization Clear TE and RE bits in SCSCR2 to 0 (1) Set TFRST and RFRST bits in SCFCR2 to 1 Set CKE1 and CKE0 bits in SCSCR2 (leaving TE and RE bits cleared to 0) Set data transfer format in SCSMR2 Set value in SCBRR2 Wait 1-bit interval elapsed? Yes Set RTRG1-0, TTRG1-0, and MCE in SCFCR2 Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR2 to 1,and set RIE, and TIE bits No (4) (2) (3) (1) Set the clock selection in SCSCR2. Be sure to clear bits RIE TIE, TE, and RE to 0. When clock output is selected, it is output immediately after SCSCR2 settings are made. (2) Set the data transfer format in SCSMR2. (3) Write a value corresponding to the bit rate into the bit rate register 2 (SCBRR2). (Not necessary if an external clock is used.) (4) Wait at least one bit interval, then set the TE bit or RE bit in SCSR2 to 1. Also set the RIE and TIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. End Figure 19.4 Sample SCIF Initialization Flowchart Rev. 5.00 Dec 12, 2005 page 592 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) * Serial data transmission Figure 19.5 shows a sample serial transmission flowchart. After SCIF transmission is enabled, use the following procedure to perform serial data transmission. Start transmission (1) SCIF status check and transmit data write: Read serial status register 2 (SCSSR2) and check that the TDFE flag is set to 1, then write transmit data to the transmit FIFO data register 2 (SCFTDR2), read 1 from the TDFE and TEND flags, then clear these flags to 0. The number of transmit data bytes that can be written is 16 - (transmit trigger set number). (2) Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR2, and then clear the TDFE flag to 0. (3) Break output at the end of serial transmission: To output a break in serial transmission, set the port SC data register (SCPDR) and port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register 2 (SCSCR2). For information on SCPDR2 and SCPCR2, see section 17.2.8. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of the FIFO data count set register 2 (SCFDR2). Read TDFE bit in SCSSR2 (1) TDFE= 1? Yes No Write transmit data (16 - transmit trigger set number) to SCFTDR2, read 1 from TDFE bit and TEND flag in SCSSR2, then clear to 0 (2) No All data transmitted? Yes Read TEND bit in SCSSR2 TEND= 1? Yes (3) Break output? Yes Set SCPDR2 and SCPCR2 Clear TE bit in SCSCR2 to 0 No No End of transmission Figure 19.5 Sample Serial Transmission Flowchart Rev. 5.00 Dec 12, 2005 page 593 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register 2 (SCFTDR2), the SCIF transfers the data from SCFTDR2 to the transmit shift register 2 (SCTSR2) and starts transmitting. Confirm that the TDFE flag in the serial status register 2 (SCSSR2) is set to 1 before writing transmit data to SCFTDR2. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR2 to SCTSR2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR2. When the number of transmit data bytes in SCFTDR2 falls below the transmit trigger number set in the FIFO control register 2 (SCFCR2), the TDFE flag is set. If the TIE bit in the serial control register (SCSR2) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One-bit 0 is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) d. Stop bit(s): One- or two-bit 1s (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR2 transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR2 to SCTSR2, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCSSR2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Figure 19.6 shows an example of the operation for transmission. Rev. 5.00 Dec 12, 2005 page 594 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) TDFE TEND TXI interrupt Data written to TXI interrupt request SCFTDR2 and TDFE request flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 19.6 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 19.7 shows an example of the operation when modem control is used. Start bit Serial data TXD CTS 0 D0 D1 D7 Parity Stop bit bit 0/1 Start bit 0 D0 D1 D7 0/1 Rise this point before a stop bit Figure 19.7 Example of Operation Using Modem Control (CTS CTS) CTS Rev. 5.00 Dec 12, 2005 page 595 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) * Serial data reception Figures 19.8 and 19.9 show sample serial reception flowcharts. After SCIF reception is enabled, use the following procedure to perform serial data reception. Start reception Read DR, ER, BRK flags in SCSSR2 (1) BRK v ER v DR = 1? No Yes (1) Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR2 to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin. (2) SCIF status check and receive data read : Read the serial status register 2 (SCSSR2) and check that RDF = 1, then read the receive data in the receive FIFO data register 2 (SCFRDR2), read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can be identified by an RXI interrupt. (3) Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR2, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR2 can be ascertained by reading the lower bits of SCFDR2. Error processing (2) Read RDF flag in SCSSR2 No RDF = 1? Yes Read receive data in SCFRDR2, and clear RDF flag in SCSSR2 to 0 (3) No All data received? Yes Clear RE bit in SCSCR2 to 0 End reception Figure 19.8 Sample Serial Reception Flowchart (1) Rev. 5.00 Dec 12, 2005 page 596 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Error processing No 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCSSR2. 2. When a break signal is received, receive data is not transferred to SCFRDR2 while the BRK flag is set. However, note that the last data in SCFRDR2 is H'00 and the break data in which a framing error occurred is stored. ER = 1? Yes Receive error processing No BRK= 1? Break processing No DR= 1? Yes Read receive data in SCFRDR2 Clear DR, ER, BRK flags in SCSSR2 to 0 End Figure 19.9 Sample Serial Reception Flowchart (2) Rev. 5.00 Dec 12, 2005 page 597 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register 2 (SCRSR2) to SCFRDR2. c. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR2. Note: Reception becomes in possible after a receive error occurred. 4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit in SCSCR2 is set to 1 when the BRK flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 19.10 shows an example of the operation for reception. Rev. 5.00 Dec 12, 2005 page 598 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Data D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) RDF RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error FER Figure 19.10 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS signal is output when SCFRDR2 is empty. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR2 is full and reception is not possible. Figure 19.11 shows an example of the operation when modem control is used. Start bit 0 D0 D1 D2 Parity bit D7 0/1 1 Start 0 Serial data RXD RTS Figure 19.11 Example of Operation Using Modem Control (RTS RTS) RTS Rev. 5.00 Dec 12, 2005 page 599 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.4 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 19.9 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE and RIE bits in SCSCR2. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDFE flag in the serial status register 2 (SCSSR2) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated. The TDFE flag is cleared when data exceeding the transmit trigger number is written to transmit FIFO data register 2 (SCFTDR2) by the DMAC, 1 is read from TDFE, and then 0 is written to TDFE. When the RDF flag in SCSSR2 is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed when the RDF flag in SCSSR is set to 1. The RDF flag is cleared when receive data is read from receive FIFO data register 2 (SCFRDR2) by the DMAC until the quantity of receive data in SCFRDR2 is less than the receive trigger number, 1 is read from RDF, and then 0 is written to RDF. When the ER flag in SCSSR2 is set to 1, an ERI interrupt request is generated. When the BRK flag in SCSSR2 is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2. Table 19.9 SCIF Interrupt Sources Interrupt Source ERI RXI BRI TXI Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive data FIFO full flag (RDF) or data ready flag (DR) Interrupt initiated by break flag (BRK) Interrupt initiated by transmit FIFO data empty flag (TDFE) DMAC Activation Impossible Possible (RDF only) Impossible Possible Low Priority on Reset Release High See section 4, Exception Processing, for priorities and the relationship with non-SCIF interrupts. Rev. 5.00 Dec 12, 2005 page 600 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 19.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register 2 (SCSSR2) is set when the number of transmit data bytes written in the transmit FIFO data register 2 (SCFTDR2) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register 2 (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR2 is less than or equal to the transmit trigger number, the TDFE flag will be set to 1 again after being cleared to 0. The TDFE flag should therefore be cleared to 0 after a number of data bytes exceeding the transmit trigger number has been written to SCFTDR2. The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO data count set register 2 (SCFDR2). 2. SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register 2 (SCSSR2) is set when the number of receive data bytes in the receive FIFO data register 2 (SCFRDR2) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register 2 (SCFCR2). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 exceeds the trigger number, the RDF flag will be set to 1 again after being cleared to 0. The RDF flag should therefore be cleared to 0 when 1 has been written to RDF after all receive data has been read. The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count set register 2 (SCFDR2). 3. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR2 is halted in the break state, the SCIF receiver continues to operate, so if the BRK flag is cleared to 0 it will be set to 1 again. 4. Sending a Break Signal: The I/O condition and level of the TxD pin are determined by the SCP4DT bit in the port SC data register 2 (SCPDR2) and bits SCP4MD0 and SCP4MD1 in the port SC control register 2 (SCPCR2). This feature can be used to send a break signal. To send a break signal during serial transmission, clear the CP4DT bit to 0 (designating low level), then set the SCP4MD0 and SCP4MD1 bits to 0 and 1, respectively, and finally clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin. Rev. 5.00 Dec 12, 2005 page 601 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) 5. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is confirmed. 6. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 19.12. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RxD2) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 Figure 19.12 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). Equation 1: M = 0.5 - 1 D - 0.5 (1 + F) x 100% ........................ (1) - (L - 0.5) F - 2N N M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency Rev. 5.00 Dec 12, 2005 page 602 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% ...................................................................................................... (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 5.00 Dec 12, 2005 page 603 of 1034 REJ09B0254-0500 Section 19 Serial Communication Interface with FIFO (SCIF) Rev. 5.00 Dec 12, 2005 page 604 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Section 20 Serial IO (SIOF) 20.1 Overview SIOF is a clock-synchronized serial I/O module that can be directly connected to the audio CODEC. 20.1.1 Features Feature of SIOF are listed below. * Serial transmitting 32 bit x 16 step sized FIFO for send or receive communication 8 bit/16 bit/recording or playback function for 16 bit stereo sound Both big endian and little endian are supported in data transmission and reception Variable sampling rate up to 48 kHz Synchronization corresponds to frame sync pulse and switching right/left channels Support CODEC control function through data line Support linear/audio A-Law and -Law CODEC chip Support both master and receive communication mode * Serial clock External clock or peripheral clock (P) may be used as clock source. * Interrupt It is possible to require independently the following 4 interruptions. Transmit interrupt Receive interrupt Error interrupt Control interrupt * DMA transfer Supports transmit/receive operations using DMA transfer in response to a transmit/receive transfer request Rev. 5.00 Dec 12, 2005 page 605 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.1.2 Block Diagram Figure 20.1 shows SIOF block diagram. Peripheral clock (P) TXI RXI ERI CCI 32 Peripheral bus Bus I/F 32 16 32 32 32 32 Control register Tx_FIFO 32 bits x 16 stages Rx_FIFO 32 bits x 16 stages Tx control data Rx control data Baud rate 1/n MCLK generator Timing control P/S S/P SIOF SIOMCLK SCK_SIO SIOFSYNC TXD_SIO RXD_SIO Figure 20.1 SIOF Block Diagram Rev. 5.00 Dec 12, 2005 page 606 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.1.3 Terminal Table 20.1 shows pin list of SIOF. Table 20.1 SIOF Pin List Name Clock input pin Communication clock pin Frame sync pin Transmit data pin Receive data pin Symbol SIOMCLK SCK_SIO SIOFSYNC TXD_SIO RXD_SIO I/O I I/O I/O O I Function Master clock input Serial clock (common for transmitting/ receiving) Frame synchronized signal (common for transmitting/receiving) Transmit data Receive data 20.1.4 Register Configuration Table 20.2 lists the internal registers of SIOF. Table 20.2 SIOF Register Configuration Name Serial mode register Clock select register Receive data assign register Control data assign register Serial control register FIFO control register Status register Interruption enabling register Transmit data register Receive data register Transmit control register Receive control register Symbol SIMDR SISCR SIRDAR SICDAR SICTR SIFCTR SISTR SIIER SITDR SIRDR SITCR SIRCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'1000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'040000C0 (H'A40000C0)* H'040000C2 (H'A40000C2)* H'040000C4 (H'A40000C4)* H'040000C6 (H'A40000C6)* H'040000C8 (H'A40000C8)* H'040000D0 (H'A40000D0)* H'040000D4 (H'A40000D4)* H'040000D6 (H'A40000D6)* H'040000E0 (H'A40000E0)* H'040000E4 (H'A40000E4)* H'040000E8 (H'A40000E8)* Access Size 16 16 16 16 16 16 16 16 32 32 32 Transmit data assign register SITDAR H'040000CC (H'A40000CC)* 16 H'040000EC (H'A40000EC)* 32 Note: * Use the address surrounded by parenthesis when the address translation process by MMU is not applied. Refer to section 20.3.5, Control Data Interface for more details of the control data. Rev. 5.00 Dec 12, 2005 page 607 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2 20.2.1 Register Description Mode Register (SIMDR) This register sets the operating mode of SIOF. This register is initialized by the power on reset or manual reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TRMD1 0 R/W 7 TXDIZ 0 R/W 14 TRMD0 0 R/W 6 LSBF 0 R/W 13 -- 0 R* 5 RCIM 0 R/W 12 REDG 0 R/W 4 -- 0 R* 11 FL3 0 R/W 3 -- 0 R* 10 FL2 0 R/W 2 -- 0 R* 9 FL1 0 R/W 1 -- 0 R* 8 FL0 0 R/W 0 -- 0 R* Note: * 0 must be written into these bits. The operation of this LSI is unpredictable when setting the value other than 0. Bits 13 and 4 to 0--Reserved Bits 15 and 14--Transmit Mode Setting (TRMD1 and TRMD0) Bit 15: TRMD1 0 1 Bit 14: TRMD0 0 1 0 1 Description Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 (Initial value) Note: Refer to section 20.3.3, Transmit Data Format for more details of the functions of each mode. Bit 12--Receive with Sampling Edge (REDG): TXD_SIO is output at the opposite edge from the sampling time of RXD_SIO. (see figure 20.4) Rev. 5.00 Dec 12, 2005 page 608 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 12: REDG 0 1 Description Sample RXD_SIO by falling edge of SCK_SIO Sample RXD_SIO by rising edge of SCK_SIO (Initial value) Note: This mode is effective in master mode 1 or master mode 2. Bits 11 to 8--Frame Length (FL3 to FL0) Bit 11: FL3 0 Bit 10: FL2 0 1 Bit 9: FL1 0/1* 0 1 1 0 1 0/1* 0 1 Bit 8: FL0 0/1* 0 1 0 1 0/1* 0 1 0 1 Description Slot size is 8 bit, frame length is 8 bit Slot size is 8 bit, frame length is 16 bit Slot size is 8 bit, frame length is 32 bit Slot size is 8 bit, frame length is 64 bit Slot size is 8 bit, frame length is 128 bit Slot size is 16 bit, frame length is 16 bit Slot size is 16 bit, frame length is 32 bit Slot size is 16 bit, frame length is 64 bit Slot size is 16 bit, frame length is 128 bit Slot size is 16 bit, frame length is 256 bit (Initial value) Notes: 1. When 8 bit slot size is chosen, control data is not able to be transmitted or received. 2. When LSB first is chosen, control data is not able to be transmitted or received. * Same setting in both 1 and 0. (Don't care) Bit 7--Hi-Z Output Control under Ineffective Case for Transmission (TXDIZ): Ineffective case is the case of transmit data or command are not assigned or transmit operation is disabled. Bit 7: TXDIZ 0 1 Description 1 output ineffective transmission Hi-Z output ineffective transmission (Initial value) Bit 6--LSB First Transmission and Reception (LSBF): Selects MSB first or LSB first for the transmission or reception frame. Bit 6: LSBF 0 1 Description MSB First LSB First (Initial value) Rev. 5.00 Dec 12, 2005 page 609 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 5--Transmit or Receive Control Command Interrupt Mode (RCIM) Bit 5: RCIM 0 1 Description Set RCRDY bit of SISTR register when the contents of SIRCR register is changed. (Initial value) Set RCRDY bit of SISTR register when every control commands are received and set to SIRCR register 20.2.2 Clock Select Register (SISCR) This register sets the operate of baud rate generator. To set up this register, TRMD bit of SIMDR register must be set 10 or 11. This register is initialized in power on reset or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 MSSEL 0 R/W 7 -- 0 R* 14 MSIMM 0 R/W 6 -- 0 R* 13 -- 0 R* 5 -- 0 R* 12 BRPS4 0 R/W 4 -- 0 R* 11 BRPS3 0 R/W 3 -- 0 R* 10 BRPS2 0 R/W 2 BRDV2 0 R/W 9 BRPS1 0 R/W 1 BRDV1 0 R/W 8 BRPS0 0 R/W 0 BRDV0 0 R/W Note: * 0 must be written into this bit. The operation of this LSI is unpredictable when setting the value other than 0. Bit 15--Master Clock Source Choice (MSSEL): Master clock means the clock that is input to the baud rate generator. Bit 15: MSSEL 0 1 Description Use external clock source SIOMCLK input signal as master clock(Initial value) Use peripheral clock (P) as master clock Rev. 5.00 Dec 12, 2005 page 610 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 14--Master Clock Select (MSIMM) Bit 14: MSIMM 0 1 Description Use baud rate generator output clock as clock source Use master clock as clock source (Initial value) Bits 13 and 7 to 3--Reserved Bits 12 to 8--Setting of Prescaler (BRPS4 to BRPS0): The dividing ratio of master clock (BRPS) is set within the range of 00001 (1/1 times), 00010 (1/2 times), to 11111 (1/31 times) and 00000 (1/32 times: initial value). Bits 2 to 0--Setting of Dividing Ratio (BRDV2 to BRDV0): Set the dividing ratio of frequency of output stage (BRDV). Finally, baud rate is decided by the value of BRPS * BRDV (maximum 1/1024). Bit 2: BRDV2 0 Bit 1: BRDV1 0 1 1 0 Bit 0: BRDV0 0 1 0 1 0 Settings other than the above Description 1/2 times of prescaler output 1/4 times of prescaler output 1/8 times of prescaler output 1/16 times of prescaler output 1/32 times of prescaler output (Reserved) (Initial value) Rev. 5.00 Dec 12, 2005 page 611 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2.3 Transmit Data Assign Register (SITDAR) This register specifies the data assignment of transmit data in each transmit frame. This register is initialized in power on reset or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TDLE 0 R/W 7 TDRE 0 R/W 14 -- 0 R 6 TLREP 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 TDLA3 0 R/W 3 TDRA3 0 R/W 10 TDLA2 0 R/W 2 TDRA2 0 R/W 9 TDLA1 0 R/W 1 TDRA1 0 R/W 8 TDLA0 0 R/W 0 TDRA0 0 R/W Bits 14 to 12, 5, and 4--Reserved Bit 15--Transmit Data for Left Channel Enable (TDLE) Bit 15: TDLE 0 1 Description Disable data transmitting of left channel data Enable data transmitting of left channel data (Initial value) Bits 11 to 8--Transmit Data for Left Channel Assignment (TDLA3 to TDLA0): The slot assignment of transmit data for Left channel in transmit frame is specified from 0000(0: initial value) to 1110(14) by this register. The transmit data for left channel is set in bits SITDL 15 to SITDR register. Note: The operation of this LSI is unpredictable when setting 1111 in bits TDLA3 to TDLA0. Bit 7--Transmit Data for Right Channel Enable (TDRE) Bit 7: TDRE 0 1 Description Disable data transmitting of right channel data Enable data transmitting of right channel data (Initial value) Rev. 5.00 Dec 12, 2005 page 612 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 6--Transmit Left Channel Data Repeatedly (TLREP): Setting of this bit is effective when TDRE bit is 1. When 1 is set to this bit, setting of bits 15 to 0 in SITDR register is ignored. Bit 6: TLREP 0 1 Description The data in SITDR bit of SITDR register is transmitted as right channel data. (Initial value) The data in SITDL bit of SITDL register is transmitted as right channel data. Bits 3 to 0--Transmit Data for Right Channel Slot Assignment (TDRA3 to TDRA0): The slot assignment of transmit data for Right channel in transmit frame is specified from 0000(0: initial value) to 1110(14) by this register. The transmit data for right channel is set in SITDR bits 15 to 0 in SITDR register. Note: The operation of this LSI is unpredictable when setting 1111 in bits TDRA3 to TDRA0. 20.2.4 Receive Data Assign Register (SIRDAR) This register specifies the data assignment of received data in each received frame. This register is initialized at power on reset or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 RDLE 0 R/W 7 RDRE 0 R/W 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 RDLA3 0 R/W 3 RDRA3 0 R/W 10 RDLA2 0 R/W 2 RDRA2 0 R/W 9 RDLA1 0 R/W 1 RDRA1 0 R/W 8 RDLA0 0 R/W 0 RDRA0 0 R/W Bits 14 to 12, and 6 to 4--Reserved Bit 15--Receive Data for Left Channel Enable (RDLE) Bit 15: RDLE 0 1 Description Disable receiving of left channel data Enable receiving of left channel data (Initial value) Rev. 5.00 Dec 12, 2005 page 613 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bits 11 to 8--Receive Data for Left Channel Slot Assignment (RDLA3 to RDLA0): The slot assignment of received data for left channel in received frame is specified from 0000(0: initial value) to 1110(14) by this register. The receive data for left channel is stored in bits 15 to 0 in SIRDL of SIRDR register. Note: The operation of this LSI is unpredictable when setting 1111 in bits RDLA3 to RDLA0. Bit 7--Receive Data for Right Channel Enable (RDRE) Bit 7: RDRE 0 1 Description Disable receiving of right channel data Enable receiving of right channel data (Initial value) Bits 3 to 0--Receive Data for Right Channel Slot Assignment (RDRA3 to RDRA0): The slot assignment of received data for right channel in received frame is specified from 0000(0: initial value) to 1110(14) by this register. The receive data for right channel is stored in bits 15 to 0 in SIRDR of SIRDR register. Note: The operation of this LSI is unpredictable when setting 1111 in bits RDRA3 to RDRA0. 20.2.5 Control Command Assign Register (SICDAR) This register specifies the position of control command in each frame. The setting to this register is enabled when 1*** is set to bits FL3 to FL0 of SIMDR register. This register is initialized at power on reset or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 CD0E 0 R/W 7 CD1E 0 R/W 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 CD0A3 0 R/W 3 CD1A3 0 R/W 10 R/W2 0 R/W 2 CD1A2 0 R/W 9 R/W1 0 R/W 1 CD1A1 0 R/W 8 R/W0 0 R/W 0 CD1A0 0 R/W Bits 14 to 12, and 6 to 4--Reserved Rev. 5.00 Dec 12, 2005 page 614 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 15--Control Command Data Channel 0 Enable (CD0E) Bit 15: CD0E 0 1 Description Disable transmitting or receiving of control command of channel 0. (Initial value) Enable transmitting or receiving of control command of channel 0. Bits 11 to 8--Control Command Data Assignment for Channel 0 (CD0A3 to CD0A0): The slot assignment for control channel 0 in transmit and receive frames is specified from 0000(0: initial value) to 1110(14) by this register. The receive data for control channel 0 is set in bits SITC05 to SITC00 of SIRCR register. The receive data for control channel 0 is stored in bits SIRC015 to SIRC00 in SIRCR register. Note: The operation of this LSI is unpredictable when setting 1111 in bits CD0A3 to CD0A0. Bit 7--Control Command Data Channel 1 Enable (CD1E) Bit 7: CD1E 0 1 Description Disable transmitting or receiving of control command of channel 1. (Initial value) Enable transmitting or receiving of control command of channel 1. Bits 3 to 0--Control Command Data Assignment for Channel 1 (CD1A3 to CD1A0): The slot assignment for control channel 1 in transmit and receive frames is specified from 0000(0: initial value) to 1110(14) by this register. The receive data for control channel 1 is set in bits SIRC115 to SIRC10 of SIRCR register. Note: The operation of this LSI is unpredictable when setting 1111 in bits CD1A3 to CD1A0. Rev. 5.00 Dec 12, 2005 page 615 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2.6 Serial Control Register (SICTR) This register sets the operating states of SIOF. This register is initialized at power on reset or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 SCKE 0 R/W 7 -- 0 R 14 FSE 0 R/W 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 TXE 0 R/W 1 TXRST 0 W 8 RXE 0 R/W 0 RXRST 0 W Bits 13 to 10, and 7 to 2--Reserved Bit 15--Serial Clock Output Enable (SCKE): This bit is effective in master mode. When 1 is set to this bit, SIOF initializes baud rata generator, then starts, operation, and outputs the clock that is generated by baud rate generator to SCK_SIO. Bit 15: SCKE 0 1 Description Disable output of SCK_SIO (outputs 0) Enable output of SCK_SIO (Initial value) Bit 14--Frame Synchronize Signal Output Enable (FSE): This bit is effective at master mode. When 1 is set to this bit, SIOF initializes the frame counter, then starts operation. Bit 14: FSE 0 1 Description Disable output of SIOFSYNC (outputs 0) Enable output of SIOFSYNC (Initial value) Rev. 5.00 Dec 12, 2005 page 616 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 9--Transmit Enable (TXE): Setting of this bit becomes effective when next frame starts (at the rising edge of frame synchronize signal)and data are stored in transmit FIFO. After the setting "1" to this bit becomes effective, SIOF submit the transmit request according to the TFWM bit of SIFCTR register. When data is sets to transmit FIFO, transmit data is transfer from TXD_SIO. This bit is initialized at transmit reset. Bit 9: TXE 0 1 Description Disable to transmit data from TXD_SIO (outputs 1) Enable to transmit data from TXD_SIO (Initial value) Bit 8--Receive Enable (RXE): Setting of this bit is effective when next frame starts (at the rising edge of frame synchronizing signal). After the setting "1" to this bit becomes effective, SIOF begins to receive the data from RXD_SIO. When data is sets to the receive FIFO, SIOF submits the request to transfer according to RFWM bit of SIFCTR register. This bit is initialized at receive reset. Bit 8: RXE 0 1 Description Disable to receive data from RXD_SIO Enable to receive data from RXD_SIO (Initial value) Bit 1--Transmitting Operation Reset (TXRST): Setting to this bit becomes effective immediately. After the setting 1 to this bit becomes effective, SIOF change transmit data from TXD_SIO to 1 and initializes the following registers. 1. SITDR register 2. Transmit FIFO write pointer and read pointer 3. TCRDY, TFEMP, and TDREQ bits of SISTR register 4. TXE bit SIOF is cleared automatically when this bit completes the reset, so 0 is always read from this bit. Bit 1: TXRST 0 1 Description Transmitting operation is not reset Transmitting operation is reset (Initial value) Rev. 5.00 Dec 12, 2005 page 617 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 0--Receiving Operation Reset (RXRST): Setting to this bit becomes effective immediately. After the setting 1 to this bit becomes effective, SIOF initializes the following registers and stop receiving from SIORXD. 1. SIRDR register 2. Receiving FIFO write pointer and read pointer 3. RCRDY, RFFUL, and RDREQ bits of SISTR register 4. RXE bit SIOF is cleared automatically when this bit completes the reset, so 0 is always read from this bit. Bit 0: RXRST 0 1 Description Receiving operation is not reset Receiving operation is reset (Initial value) 20.2.7 FIFO Control Register (SIFCTR) This register set trigger point and show current available area of Transmit and Receive FIFO. This register is initialized at power on reset or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TFWM2 0 R/W 7 0 R/W 14 TFWM1 0 R/W 6 0 R/W 13 TFWM0 0 R/W 5 0 R/W 12 TFUA4 1 R 4 RFUA4 0 R 11 TFUA3 0 R 3 RFUA3 0 R 10 TFUA2 0 R 2 RFUA2 0 R 9 TFUA1 0 R 1 RFUA1 0 R 8 TFUA0 0 R 0 RFUA0 0 R RFWM2 RFWM1 RFWM0 Rev. 5.00 Dec 12, 2005 page 618 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bits 15 to 13--Transmit FIFO Water Mark (TFWM2 to TFWM0): The transfer request of the transmit FIFO is controlled by TDREQ bit of SISTR register. FIFO depth is always 16 steps, nevertheless the setting to these bits. Bit 15: TFWM2 0 1 Bit 14: TFWM1 0 Bit 13: TFWM0 0 0 1 1 0 1 Description The transfer request is submitted when the size of empty area in transmit FIFO is 16 steps (Initial value) The transfer request is submitted when the size of empty area in transmit FIFO is larger than 12 steps The transfer request is submitted when the size of empty area in transmit FIFO is larger than 8 steps The transfer request is submitted when the size of empty area in transmit FIFO is larger than 4 steps The transfer request is submitted when the size of empty area in transmit FIFO is larger than 1 step Bits 7 to 5--Receive FIFO Water Mark (RFWM2 to RFWM0): The transfer request of the receive FIFO is controlled by TDREQ bit of SISTR register. FIFO depth is always 16 steps, nevertheless the setting to these bits. Bit 7: RFWM2 0 1 Bit 6: RFWM1 0 Bit 5: RFWM0 0 0 1 1 0 1 Description The transfer request is submitted when the size of empty area of receive FIFO is larger than 1 step (Initial value) The transfer request is submitted when the size of empty area of receive FIFO is larger than 4 steps The transfer request is submitted when the size of empty area of receive FIFO is larger than 8 steps The transfer request is submitted when the size of empty area of receive FIFO is larger than 12 steps The transfer request is submitted when the size of empty area of receive FIFO is at 16 steps Bits 12 to 8--Transmit FIFO Usable Area (TFUA4 to TFUA0): TFUA shows usable number of words for CPU or DMAC to transfer from 00000 to 10000 (initial value). Bits 4 to 0--Receive FIFO Usable Area (RFUA4 to RFUA0): RFUA shows usable number of words for CPU or DMAC to transfer from 00000 (initial value) to 10000. Rev. 5.00 Dec 12, 2005 page 619 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2.8 Status Register (SISTR) This register shows states of SIOF. Each bit of this register becomes interrupt source when 1 is set to corresponding register of SIIER register. This register is initialized at power on reset or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R* 7 -- 0 R* 14 TCRDY 0 R* 6 -- 0 R* 13 TFEMP 0 R* 5 -- 0 R* 12 TDREQ 0 R* 4 FSERR 0 R/W 11 -- 0 R* 3 TFOVR 0 R/W 10 RCRDY 0 R* 2 TFUDR 0 R/W 9 RFFUL 0 R* 1 RFUDR 0 R/W 8 RDREQ 0 R* 0 RFOVR 0 R/W Note: * 0 should be written into these bits. Otherwise the operation is unpredictable. Bits 15, 11, and 7 to 5--Reserved Bit 14--Transmit Control Data Ready (TCRDY): This bit displays condition of SITCR register. SIOF clears when any value is written to SITCR register. This bit becomes effective when 1 is written to TXE bit of SICTR register. SIOF issues control interrupt if interrupt issuing is allowed for this bit. Once any data are written to SICTR register with 0 of TCRDY bit, new data is overwritten to original data and original data of TXD_SIO will be lost. Note: When using this bit, refer to note 2 in section 20.4, Notes on Use. Bit 14: TCRDY 0 1 Description Disable writing into SITCR register Enable writing into SITCR register (Initial value) Bit 13--Transmit FIFO Empty (TFEMP): This bit is showing condition, SIOF clear by writing to SITDR register. This bit becomes effective when 1 is written to the TXE bit of SICTR register. SIOF issues control interrupt if interrupt issuing is allowed by this bit. Rev. 5.00 Dec 12, 2005 page 620 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 13: TFEMP 0 1 Description Transmit FIFO is not empty Transmit FIFO is empty (Initial value) Bit 12--Transmit Data Transfer Request (TDREQ): The transmit data transfer request is issued when empty area of transmit FIFO exceed the setting of TFWM bit of SIFCTR register. This bit is effective when 1 is written to TXE bit of SICTR register. This bit shows condition of transmit FIFO. SIOF clears this bit if empty area of transmit FIFO is smaller than the set value of TFWM bit of SIMDR register. SIOF issues a transmit interrupt if the interrupt issuing is allowed for this bit. Bit 12: TDREQ 0 1 Description No transmit request exists. Transmit request exists. (Initial value) Bit 10--Receive Control Data Ready (RCRDY): This bit shows condition of SIRCR register. SIOF clears SIOF register when SIRCR register is read. New received data will be overwritten to SIRCR register if valid data is received and written to SIRCR register while this bit shows 1. This bit is effective when 1 is written to RXE bit of SICTR register. SIOF issues a control interrupt if the interrupt issuing is allowed to bit. Bit 10: RCRDY 0 1 Description Effective data is not stored in SIRCR register Effective data is stored in SIRCR register (Initial value) Bit 9--Receive FIFO Full (RFFUL): This bit shows condition of Receive FIFO. SIOF clears when SIRDR register is read. This bit is effective when 1 is written to RXE bit of SICTR register. SIOF issues a control interrupt when the interrupt issuing is allowed. Bit 9: RFFUL 0 1 Description Receive FIFO is not full Receive FIFO is full (Initial value) Bit 8--Receive Data Transfer Request (RDREQ): The receive data transfer request is issued when effective received data in receive FIFO exceed the setting of RFWM bit of SIMDR register. This bit is effective when 1 is written to RXE bit of SICTR register. This bit shows condition of receive FIFO. SIOF clears this bit if effective received data area in FIFO is smaller than the set Rev. 5.00 Dec 12, 2005 page 621 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) value of RFWM bit of SIMDR register. SIOF issues a receive interrupt if the interrupt issuing is allowed for this bit. Bit 8: RDREQ 0 1 Description Effective data in receive FIFO does not exceed setting of RFWM bit of SIMDR register (Initial value) Effective data in receive FIFO exceeds setting of RFWM bit of SIMDR register Bit 4--Frame Synchronization Error (FSERR): Frame synchronization error shows that next frame synchronize timing has come before data or control command are transferred. When frame synchronization error has occurred , SIOF transmits or receives data to the slots that are enable to transmit or receive data. This bit becomes effective when 1 is written to TXE bit or RXE bit of SICTR register. This bit is cleared when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this bit. Bit 4: FSERR 0 1 Description Frame synchronization error does not occur Frame synchronization error occurs (Initial value) Bit 3--Transmit FIFO Over Run (TFOVR): Transmit FIFO overrun shows that data are written to SITDR register when transmit FIFO is full. Written data is ignored when Transmit FIFO over run happens. This bit is effective when 1 is written to TXE bit of SICTR register. This bit is cleared when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this bit. Bit 3: TFOVR 0 1 Description Transmit FIFO over run does not occur Transmit FIFO over run occurs (Initial value) Bit 2--Transmit FIFO Under Run (TFUDR):Transmit FIFO under run shows that the load by data transfer from FIFO has occurred when transmit FIFO is empty. SIOF repeats to send the data that was sent before when this under run has occurred. Rev. 5.00 Dec 12, 2005 page 622 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) This bit is effective when 1 is written to RXE bit of SICTR register. This bit is cleared when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this bit. Bit 2: TFUDR 0 1 Description Transmit FIFO under run does not occur Transmit FIFO under run occurs (Initial value) Bit 1--Receive FIFO Under Run (RFUDR): Receive FIFO under run shows that SIRDR register is read when receive FIFO is empty. The data that has been read out from SIRDR is not guaranteed when this under run has occurred. This bit is effective when 1 is written to RXE bit of SICTR register. This bit is cleared when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this bit. Bit 1: RFUDR 0 1 Description Receive FIFO under run does not occur Receive FIFO under run occurs (Initial value) Bit 0--Receive FIFO Over Run (RFOVR): Receive FIFO over shows write action has occurred to receive FIFO by SIOF, when receive FIFO is full. The received data disappears when receive FIFO overrun occurs. This bit is effective when 1 is written to TXE bit or RXE bit of SICTR register. This bit is cleared when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this bit. Bit 0: RFOVR 0 1 Description Transmit over run does not generate Transmit over run generate (Initial value) Rev. 5.00 Dec 12, 2005 page 623 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2.9 Interrupt Enable Register (SIIER) This register allows SIOF interrupt resources to issue interrupt to CPU. When 1 is written to each bit, corresponding interrupt is issued by SIOF. This register is initialized at power on reset, or software reset. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R* 7 -- 0 R* 14 0 R/W 6 -- 0 R* 13 0 R/W 5 -- 0 R* 12 0 R/W 4 0 R/W 11 -- 0 R* 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W TCRDYE TFEMPE TDREQE RCRDYE RFFULE RDREQE FSERRE TFOVRE TFUDRE RFUDRE RFOVRE Note: * 0 should be written into these bits. Otherwise the operation is unpredictable. Bits 15, 11, and 7 to 5--Reserved Bit 14--Transmit Control Data Ready Enable (TCRDYE) Bit 14: TCRDYE 0 1 Description Disable interrupt of transmit control data ready Enable interrupt of transmit control data ready (control interrupt) (Initial value) Bit 13--Transmit FIFO Empty Enable (TFEMPE) Bit 13: TFEMPE 0 1 Description Disable interrupt of transmit FIFO empty Enable interrupt of transmit FIFO empty (control interrupt) (Initial value) Bit 12--Transmit Data Transfer Request Enable (TDREQE) Bit 12: TDREQE 0 1 Description Disable interrupt of transmit data transfer request enable (Initial value) Enable interrupt of transmit data transfer request enable (transmit interrupt) Rev. 5.00 Dec 12, 2005 page 624 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit10--Receive Control Data Ready Enable (RCRDYE) Bit10: RCRDYE 0 1 Description Disable interrupt of receive control data ready Enable interrupt of receive control data ready (control interrupt) (Initial value) Bit 9--Receive FIFO Full Enable (RFFULE) Bit 9: RFFULE 0 1 Description Disable interrupt of receive FIFO full Enable interrupt of receive FIFO full (control interrupt) (Initial value) Bit 8--Receive Data Transfer Request Enable (RDREQE) Bit 8: RDREQE 0 1 Description Disable interrupt of receive data transfer request (Initial value) Enable interrupt of receive data transfer request (receive interrupt) Bit 4--Frame Synchronization Error Enable (FSERRE) Bit 4: FSERRE 0 1 Description Disable interrupt of frame synchronization error Enable interrupt of frame synchronized error (error interrupt) (Initial value) Bit 3--Transmit FIFO Over Run Enable (TFOVRE) Bit 3: TFOVRE 0 1 Description Disable interrupt of transmit FIFO over run Enable interrupt of transmit FIFO over run (error interrupt) (Initial value) Bit 2--Transmit FIFO Under Run Enable (TFUDRE) Bit 2: TFUDRE 0 1 Description Disable interrupt of transmit FIFO under run Enable interrupt of transmit FIFO under run (error interrupt) (Initial value) Rev. 5.00 Dec 12, 2005 page 625 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Bit 1--Receive FIFO Under Run Enable (RFUDRE) Bit 1: RFUDRE 0 1 Description Disable interrupt of receive FIFO under run Enable interrupt of receive FIFO under run (error interrupt) Bit 0--Receive FIFO Over Run Enable (RFOVRE) Bit 0: RFOVRE 0 1 Description Disable interrupt of receive FIFO over run Enable interrupt of receive FIFO over run (error interrupt) 20.2.10 Transmit Data Register (SITDR) This register sets transmit data to SIOF. The data that has been set to this register is stored in transmit FIFO. This register is initialized at power on reset, software reset, or transmit reset. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bits 31 to 16--Transmit Data for Left Channel (SITDL15 to SITDL0): These bits set data transmitted from TXD_SIO as left channel data. The position for left channel side data are assigned as TDLA bit of SITDA register. This bit becomes effective when 1 is set to TDLE bit of SITDAR register. Bits 15 to 0--Transmit Data for Right Channel (SITDR15 to SITDR0): These bits set data transmitted from TXD_SIO as right channel data. The position for left channel side data are assigned as TDRA bit of SITDA register. This bit becomes effective when 1 is set to TDRE bit of SITDAR register, and 0 is set to TLREP bit of SITDAR register. Rev. 5.00 Dec 12, 2005 page 626 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2.11 Receive Data Register (SIRDR) This register reads receive data of SIOF. The data from receive FIFO is stored in this register. This register is initialized at power on reset, software reset, or transmit reset. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bits 31 to 16--Receive Data for Left Channel (SIRDL15 to SIRDL0): These bits stores received data from RXD_SIO as left channel data. The position of left channel side data are assumed as the position what defined by RDLA bit of SIRDAR register. These bits are effective when 1 is written to RDLE bit of SIRDAR register. Bits 15 to 0--Receive Data for Right Channel (SIRDR15 to SIRDR0): These bits stores received data from RXD_SIO as right channel data. The position of left channel side data are assumed as the position what defined by RDRA bit of SIRDAR register. These bits are effective when 1 is written to RDRE bit of SIRDAR register. Rev. 5.00 Dec 12, 2005 page 627 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2.12 Transmit Control Data Register (SITCR) This register sets the transmit control data for SIOF. Setting to this register is effective when 1*** is set to FL bit of SIMDR register. This register is initialized at power on reset, software reset, or transmit reset. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 SITC0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 SITC1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 31 to 16--Transmit Control Data for Channel 0 (SITC015 to SITC00): These bits stores data to be transfer as transmit control channel 0 data from TXD_SIO. The position of control data for channel 0 is determined by the setting of CD0A bit of SICDAR register. This bit is effective when 1 is set to CD0E bit of SICDAR register. Bits 15 to 0--SIOF Transmit Control Data for Channel 1 (SITC115 to SITC10): These bits stores data to be transfer as transmit control channel 1 command from TXD_SIO. The position of control data for channel 1 is determined by the setting of CD1A bit of SICDAR register. This bit is effective when 1 is set to CD1E bit of SICDAR register. Rev. 5.00 Dec 12, 2005 page 628 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.2.13 Receive Control Data Register (SIRCR) This register stores the received control data for SIOF. Setting to this register is effective when 1*** is set to FL bit of SIMDR register. This register is initialized at power on reset, software reset, or receive reset. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 SIRC0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 SIRC1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 31 to 16--Receive Data for Channel 0 (SIRC015 to SIRC00): Received data from RXD_SIO as control channel 0 data is stored to these bits. The position of control channel 0 data is determined by the setting of CD0A bit of SICDAR register. This bit is effective when 1 is set to CD0E bit of SICDAR register. Bits 15 to 0--Receive Data for Channel 1 (SIRC115 to SIRC10): Received data from RXD_SIO as control channel 1 data is stored to these bits. The position of control channel 1 data is determined by the setting of CD1A bit of SICDAR register. This bit is effective when 1 is set to CD1E bit of SICDAR register. Rev. 5.00 Dec 12, 2005 page 629 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3 20.3.1 Operation Serial Clock (1) Master/Slave There are two modes as serial clock listed as below. * Slave mode: SCK_SIO and SIOFSYNC is input. * Master mode: SCK_SIO and SIOFSYNC is output. (2) Baud Rate Generator (BRG) At the SIOF master mode, serial clock is generated using the baud rate generator (BRG). The baud rate can be selected from 1/2 to 1/1024. Figure 20.2 shows the serial clock supply system. From 1/2 to 1/1024 MCLK BRG E SIOMCLK Peripheral clock (P) Timing control Master OE SCK_SIO Figure 20.2 Serial Clock Supply System Table 20.3 shows examples about serial clock frequency. Table 20.3 Examples of SIOF Clock Frequency Sampling Rate Frame Length 32 bits 64 bits 128 bits 256 bits 8 kHz 256 kHz 512 kHz 1.024 MHz 2.048 MHz 44.1 kHz 1.4112 MHz 2.8224 MHz 5.6448 MHz 11.2896 MHz 48 kHz 1.536 MHz 3.072 MHz 6.144 MHz 12.288 MHz Note: In Master mode, SCK_SIO continues to be output regardless of whether there is any data. Rev. 5.00 Dec 12, 2005 page 630 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3.2 Serial Timing (1) SIOFSYNC SIOFSYNC is the frame sync signal, and supports the two modes shown below. * The pulse with 1 bit width which shows the first of the sync pulse frame. * The pulse with 1/2 frame width, which shows left channel in L/R stereo data as high and right channel as low. Figure 20.3 shows synchronized timing as SIOFSYNC. Figure 20.3(a) shows the case for master mode 1, slave mode 1, and slave mode 2. Figure 20.3(b) shows the case for master mode 2. (a) At the synch pulse 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO First bit data (MSB) 1 bit delay (b) At the L/R 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Lch. first bit data (MSB) 1/2 frame length No delay Rch. first bit data (MSB) 1/2 frame length Figure 20.3 SIOF Serial Data Synchronized Timing Rev. 5.00 Dec 12, 2005 page 631 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (2) Transmit or Receive Timing Timing to SCK_SIO for transmitting TXD_SIO or receiving RXD_SIO can be chosen from the following two cases. Timing for transmitting or receiving is set into REDG bit in SIMDR register. In slave mode 1 or slave mode 2, only the sample at falling is valid. * Sample at falling * Sample at rising Figure 20.4 shows the timing for transmitting or receiving. (a) Falling sampling SCK_SIO SIOFSYN TXD_SIO RXD_SIO Receive timing Transmit timing (b) Rising sampling SCK_SIO SIOFSYN TXD_SIO RXD_SIO Receive timing Transmit timing Figure 20.4 SIOF Transmit or Receive Timing 20.3.3 Transmit Data Format SIOF transmit two kind of data shown below. * Transmit or receive data: Transmit data of 8 bit/16 bit/16 bit stereo * Control data: 16 bit length (interface by using the dedicated register) (1) Transmit Mode SIOF has four modes as transmit mode shown in table 20.4. Transmit mode is set to bits TRMD1 to TRMD0 in SIMDR register. Table 20.4 Serial Transmit Mode Transmit Mode Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 SIOFSYNC Sync pulse Sync pulse Sync pulse L/R Bit Delay 1 bit 1 bit 1 bit Nothing Control Data Slot position Secondary FS Slot Position No support Rev. 5.00 Dec 12, 2005 page 632 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (2) Frame Length Frame length of SIOF transmitting is set by bits FL3 bit to FL0 in SIMDR register. Table 20.5 shows relations between value and frame length. Table 20.5 Frame Length FL3, FL2, FL1, FL0 00 - 0100 0101 0110 0111 10 - 1100 1101 1110 1111 Slot Length 8 8 8 8 8 16 16 16 16 16 Bit/Frame 8 16 32 64 128 16 32 64 128 256 Support Transmit Data 8 bit monaural 8 bit monaural 8 bit monaural 8 bit monaural 8 bit monaural 16 bit monaural/stereo 16 bit monaural/stereo 16 bit monaural/stereo 16 bit monaural/stereo 16 bit monaural/stereo (3) Slot Position SIOF can set the position of transmit data, receive data, and control data (common in transmit/receive) in 1 frame independently by slot number. The following register are used for this setting. * Transmit data: SITDAR register * Receive data: SIRDAR register * Control data: SICDAR register Control data is effective when the slot length is 16 bit. The control data for transmission and reception is always assigned to the same slot. Rev. 5.00 Dec 12, 2005 page 633 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3.4 Register Assignment for Transfer Data (1) Transmit or Receive Data Writing into/reading out of transmit/receive data is done for the following registers. * Writing transmit data: SITDR register (32 bit access) * Reading receive data: SIRDR register (32 bit access) Figure 20.5 shows bit alignment of transmit or receive data and SITDR and SIRDR registers. (a) At the 16 bit stereo 31 24 23 Lch. data 16 15 87 Rch. data 0 (b) At the 16 bit monaural 31 24 23 Data 16 15 87 0 (c) At the 8 bit monaural 31 Data 24 23 16 15 87 0 (d) At the 16 bit stereo (right and left same sound) 31 24 23 Data 16 15 87 0 Figure 20.5 Transmit or Receive Data Bit Alignment Note: In figure 20.5, only data portions that are shown by the oblique lines are transmitted or received as effective data. Thus, it is necessary to transmit in byte for 8 bit data and in word 16 bit data. The areas without the oblique lines are not the object to transmit or receive. Rev. 5.00 Dec 12, 2005 page 634 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Monaural or stereo of transmit data is set with TDLE bit and TDRE bit of SILTDAR register. To choose monaural or stereo for receive, RDLE bit and RDRE bit of SIRDAR register must be set. The same sound for right and left in transmit data is set with TLREP bit of SITDAR register. Table 20.6 shows establishment of sound mode for transmit data, table 20.7 shows establishment of sound mode for receive data, use only the left channel in case of monaural 8 bits transfer. Table 20.6 Transmit Data Sound Mode Bit Mode Monaural Stereo Same sound for right and left TDLE 1 1 1 TDRE 0 1 1 TDREP * 0 1 *: Don't care Table 20.7 Receive Data Sound Mode Bit Mode Monaural Stereo RDLE 1 1 RDRE 0 1 Note: Same mode for right and left don't exist in receive data. Rev. 5.00 Dec 12, 2005 page 635 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (2) Control Data Control data is read out/written into the following registers. * Writing transmit control data: SITCR register (32 bit access) * Reading receive control data: SIRCR register (32 bit access) Figure 20.6 shows bit alignments of transmit or receive data and SITCR and SIRCR registers. (a) At the control data 1ch. 31 24 23 Control data ch. 0 16 15 87 0 (b) At the control data 2ch. 31 24 23 Control data ch. 0 16 15 87 Control data ch. 1 0 Figure 20.6 Control Data Bit Alignment The channel number of control data is set with CD0E bit CD1E bit of SICDAR register. Table 20.8 establishment of ch. number for control data. Use channel 0 when using only data one channel as control data. Table 20.8 Control Data Channel Number Establishment Bit Ch. Number 1 2 CD0E 1 1 CD1E 0 1 Rev. 5.00 Dec 12, 2005 page 636 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3.5 Control Data Interface Control data outputs the control command to CODEC and receive the state of CODEC. SIOF support the following two operations as an interface operation of control data. * Control by the slot positions * Control by secondary FS Control data is effective when selecting 16 bit as data length and MSB first receive mode. (1) Control by Slot Positions (Master Mode 1) This is the method that dedicates the slot passion of control data in a frame to transmit or receive the control data. Figure 20.7 shows a sample of control data interface timing by slot position. Note: When using this method, peripheral clock (P) should be used as the master clock (Master Clock Select (MSSEL) = 1). 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Lch. DATA Control ch.0 Rch. DATA Control ch.1 Slot No.0 Slot No.1 Slot No.2 Slot No.3 Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0001, FL = (frame length 128 bits), TDRE = 1, TDRA3 to TDRA0 = 0010, RDRE = 1, RDRA3 to RDRA0 = 0010, CD1E = 1, CD1A3 to CD1A0 = 0011 -- Figure 20.7 Control Data Interface (Slot Position) Rev. 5.00 Dec 12, 2005 page 637 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (2) Control by Secondary FS This is the method that CODEC, which outputs SIOFSYNC as a sync. pulse (FS), transmit or receive the control data by outputting the secondary FS used for transmit or receive for only control data after the period of 1/2 frame, which is different from the original FS output position. Order of the control data interface as secondary FS are listed below. * Normal data are sent as LSB=0 (compulsory is 0 by SIOF) * Transmit data of LSB=1 at transmitting the control data (For 1 by SIOF reading to SITCR register) * CODEC transmits secondary FS * SIOF synchronizes secondary FS and transmit or receive (storing into SIRCR register) the control data (setting data in SITCR register) Figure 20.8 shows timing of control data interface by secondary FS. 1 frame 1/2 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Normal FS Lch.DATA Slot No.0 Secondary FS Control ch.0 Slot No.0 LSB = "1" (secondary FS request) " REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 1100 (frame length 28 bits) TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Normal FS 1/2 frame Setting: TRMD = 01, TDLE = 1, RDLE = 1, CD0E = 1, Figure 20.8 Control Data Interface (Secondary FS) Rev. 5.00 Dec 12, 2005 page 638 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3.6 FIFO (1) Outline Features of SIOF transmit or receive FIFO are listed as below. * Capacity of 32 bits x 16 stages for each of transmission and reception * Pointer is updated by a read/write cycle for all of the access sizes of CPU and DMAC (It is impossible to separate one stage access to multiple times) * Access cycle number is always 2 cycles (P bus cycle) for all of the access sizes. (2) Transmit Request Transmit request of FIFO is displayed in the following two bits of SISTR register. * Transmit request: TDREQ (transmit interrupt factor) * Receive request: RDREQ (receive interrupt factor) It is possible to set independently the condition for each of submitting transmit request of transmit or receive FIFO. Condition of transmit request are set to bits TFWM2 to TFWM0 in SIFCTR register and transfer request of receive FIFO are set to bits RFWM2 to RFWM0. Table 20.9 shows transmit request submit condition, and table 20.10 shows receive request submit condition. Table 20.9 Transmit Request Submit Condition TFWM2 to TFWM0 000 100 101 110 111 Request Stage Number 1 4 8 12 16 Transmit Request Submit 16 stages empty area Over 12 stages empty area Over 8 stages empty area Over 4 stages empty area Over 1 stage empty area Large Used Area Small Rev. 5.00 Dec 12, 2005 page 639 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Table 20.10 Receive Request Submit Condition RFWM2 to RFWM0 000 100 101 110 111 Request Stage Number 1 4 8 12 16 Receive Request Submit Over 1 stage effective area Over 4 stages effective area Over 8 stages effective area Over 12 stages effective area 16 stages effective area Large Used Area Small When the data area or empty area exceed the above stage number, FIFO capacity always can be used 16 stages. Therefore, over flow or under flow error are submitted when the data area, or empty area excesses 16 stages. Even if FIFO is not empty or full, the transmit request is cancelled when the above conditions become not to be satisfied. (3) Showing of Stage Number The state of using transmit or receive FIFO is displayed in the following registers. * Transmit FIFO: Shows stage number of empty area to bits TFUA4 to TFUA0 in SIFCTR register * Receive FIFO: Shows stage number of effective data to bits RFUA4 to RFUA0 of SIFCTR register The above contents show the number of data which CPU or DMAC can transfer. Rev. 5.00 Dec 12, 2005 page 640 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3.7 Procedures for Transmit or Receive (1) Transmitting in Master Figure 20.9 shows an example of setting and operation of transmitting in master. No. Time chart Start 1 Settting of SIMDR register, SIMCR register, SITDAR register, SIRDAR register, SICDAR register, SIFCTR register Setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of FIFO request Set the beggin to operation of baud rate generator Setting content of SIOF SIOF operation 2 "1" is set to SCKE bit of SICTR register 3 SCK_SIO begin to transmit Transmit serial clock 4 "1" is set to FSE bit of SICTR register Set the begin to transmit of frame synchronized signal Set the transmit enable Transmit frame synchronized signal Submit the transmit request 5 "1" is set to TXE bit of SICTR register 6 TDREQ = 1? Y N 7 Setting of SITDR register Set the transmit data 8 Synchronized to SIOFSYNC, content of SITDR is setn from TXD_SIO Transmit Finish to transmit? 9 Y N "0" is set to TXE bit of SICTR register End Set to transmit disable Finish to transmit Figure 20.9 Example of Transmit Operation in Master Rev. 5.00 Dec 12, 2005 page 641 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (2) Receiving in Master Figure 20.10 shows an example of receiving and operation in master. No. Time chart Start 1 Settting of SIMDR register, SIMCR register, SITDAR register, SIRDAR register, SICDAR register, SIFCTR register Setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of FIFO request Set the beggin to operation of baud rate generator Transmit serial clock 3 SCK_SIO begin to transmit Setting content of SIOF SIOF operation 2 "1" is set to SCKE bit of SICTR register 4 "1" is set to FSE bit of SICTR register Set the begin to transmit of frame synchronized signal Transmit frame synchronized signal 5 "1" is set to RXE bit of SICTR register Set the transmit enable 6 Synchronized to SIOFSYNC receive data from RXD_SIOR is stored to SIRDR Receive request is submitted by limit of reveive FIFO 7 RDREQ = 1? Y N Receive 8 Setting of SIRDR register Reading of receive data Finish to transmit? 9 Y N "0" is set to RXE bit of SICTR register End Set to transmit disable Finish to receive Figure 20.10 Example of Receive Operation in Master Rev. 5.00 Dec 12, 2005 page 642 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (3) Transmitting in Slave Figure 20.11 shows an example of transmitting and operation in slave. No. Time chart Start 1 Settting of SIMDR register, SIMCR register, SITDAR register, SIRDAR register, SICDAR register, SIFCTR register Setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of FIFO request Disable to transmit when frame synchronized transmit submit the transmit request Setting content of SIOF SIOF operation 2 "1" is set to TXE bit of SICTR register Set transmit enable 3 TDREQ = 1? Y N 4 Setting of SITDR register Set the transmit data 5 Synchronized to SIOFSYNC send content of SITDR from TXD_SIO Transmit Finish to transmit? 6 Y N "0" is set to TXE bit of SICTR register End Set to transit disable Finish to transmit Figure 20.11 Example of Transmit Operation in Slave Rev. 5.00 Dec 12, 2005 page 643 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (4) Receiving in Slave Figure 20.12 shows an example of receiving and operation in slave. No. Time chart Start 1 Settting of SIMDR register, SIMCR register, SITDAR register, SIRDAR register, SICDAR register, SIFCTR register Setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of FIFO request Set the receive enable Receiving enable when frame synchronized signal receive Receive request is submitted by receive FIFO limit Setting content of SIOF SIOF operation 2 "1" is set to TXE bit of SICTR register 3 Synchronized to SIOFSYNC store receive data from RXD_SIO to SIRDR 4 RDREQ = 1? Y N Receive 5 Reading of SIRDR register Reading of receive data Finish to transmit? 6 Y N "0" is set to RXE bit of SICTR register End Set to receive disable Finish to receive Figure 20.12 Example of Receive Operation in Slave Rev. 5.00 Dec 12, 2005 page 644 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (5) Transmit or Receive Reset SIOF can reset independently the transmit and receive portions by setting 1 in the following bits. * Transmit reset: (TXRST bit of SICTR register) * Receive reset: (RXRST bit of SICTR register) Table 20.11 shows the initialized contents by transmit or receive reset. Table 20.11 Transmit or Receive Reset Reset Type Transmit reset Initialized Register or Bits SITDR register Transmit FIFO write pointer Transmit FIFO read pointer TCRDY, TFEMP, and TDREQ bits in SISTR register TXE bit in SICTR register Receive reset SIRDR register Receive FIF0 write pointer Receive FIF0 read pointer RCRDY, RFFUL, and RDREQ bits in SISTR register RXE bit in SICTR register (6) Module Stop SIOF stops transmit or receive operation with holding the contents of all registers at module stop. Issue the transmit or receive reset, when the transmit or receive operation is not executed directly after the module stop. Rev. 5.00 Dec 12, 2005 page 645 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3.8 Interrupt SIOF has the following four types of interrupt. These types are reflected to IRR4 register in interrupt controller (INTC). * Transmit interrupt (TXI) * Receive interrupt (RXI) * Control interrupt (CCI) * Error interrupt (ERI) (1) Interrupt Factor Each interrupt is submitted by its multiple factors. Each factor is shown in SIOF register as SIOF states. Table 20.12 shows SIOF interrupt factors. Table 20.12 SIOF Interrupt Factors No. 1 2 3 4 5 6 7 Error (ERI) Type Transmit (TXI) Receive (RXI) Control (CCI) Bit TDREQ RDREQ TCRDY RCRDY TFEMP RFFUL TFUDF Function Transmit FIFO send request Receive FIFO send request Transmit control data ready Receive control data ready Transmit FIFO empty Receive FIFO full Transmit FIFO under flow Explanation of Interrupt Data of over setting is stared to transmit FIFO Data of over setting is stared to receive FIFO Enable writing into transmit control data register Valid data is stored in receive control data register Transmit FIFO is empty Receive FIFO is full The serial data send timing comes when transmit FIFO is empty Write to transit FIFO when transmit FIFO is full Receive serial data when receive FIFO is full Read receive FIFO when receive FIFO is empty Serial signal is received before setting bit number (at slave) 8 9 10 11 TFOVF RFOVF RFUDF FSERR Transmit FIFO over flow Receive FIFO over flow Receive FIFO under flow F3 error Rev. 5.00 Dec 12, 2005 page 646 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) It depends on setting of SIIER register whether or not an interrupt corresponding to each interrupt factor is submitted or not depend. SIOF submits each interrupt when interrupt factor that 1 is set to corresponding bit of SIIER register is set to 1. (2) Transmit/Receive Interrupt Flag Transmit or receive interrupt requests INTC or DMAC to accept the interruption through the interrupt flag, which is generated from the value of TDREQ bit and RDREQ bit in SISTR register. Table 20.13 shows the setting conditions for the transmit or receive interrupt flag. Table 20.13 Setting Conditions for the Transmit or Receive Interrupt Flag Setting Conditions Transmit interrupt flag Receive interrupt flag TDREQ in SISTR register = 1 RDREQ in SISTR register = 1 Resetting Conditions * * * * TDREQ in SISTR register = 0 Acknowledge from DMAC RDREQ in SISTR register = 0 Acknowledge from DMAC (3) Operations in Case of Error SIOF executes the following operations for the errors which are shown in SISTR as status. * Transmit FIFO under run (TFUDR): The data that was transmitted directly before is sent again. * Transmit FIFO over run (TFOVR): The contents of transmit FIFO is protected, the written data that became to over flow is ignored. * Receive FIFO over run (RFOVR): Data that became to over flow is disposed and vanished. * Receive FIFO under run (RFUDR): Data that is read as final data is output on bus. (indefinite in specification) * FS error (FSERR): Internal counter is reset according to the sync. signal that became to error. Rev. 5.00 Dec 12, 2005 page 647 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.3.9 Transmit or Receive Timing Figures 20.13 to 20.19 show examples of serial transmit or receive of SIOF. (1) A Case of 8 bits Monaural (No.1) Sync pulse method, falling edge sampling, transmit data and receive data are assigned to slot No. 0, frame length is 8 bits. 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Lch. DATA Slot No.0 1 bit delay Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 0000 (frame length 16 bits), TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Figure 20.13 Transmit or Receive Timing (8 bits monaural--1) (2) A Case of 8 bits Monaural (No.2) Sync pulse method, falling edge sampling, transmit data and receive data are assigned to slot No.0, frame length is 16 bits. 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Lch. DATA Slot No.0 1 bit delay Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, Slot No.1 FL = 0100 (frame length 16 bits), TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Figure 20.14 Transmit or Receive Timing (8 bits monaural--2) Rev. 5.00 Dec 12, 2005 page 648 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (3) A Case of 16 bits Monaural (No.1) Sync pulse method, falling edge sampling, transmit data and receive data are assigned to slot No. 0, frame length is 64 bits. 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Lch. DATA Slot No.0 1 bit delay Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL=1101 (frame length 64 bits) TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Slot No.1 Slot No.2 Slot No.3 Figure 20.15 Transmit or Receive Timing (16 bits monaural--1) (4) A Case of 16 bits Stereo (No.1) L/R method, rising edge sampling and Lch. data are assigned to slot No. 0, Rch.data is assigned to slot No. 1, and frame length is 32 bits. 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO No delay Setting: TRMD = 11, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 1, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0= 0000, CD0A3 to CD0A0 = 0000, FL = 1100 (flame length 32 bits), TDRE = 1, TDRA3 to TDRA0 = 0001, RDRE = 1, RDRA3 to RDRA0 = 0001, CD1E = 0, CD1A3 to CD1A0 = 0000 Lch. DATA Slot No.0 Rch. DATA Slot No.1 Figure 20.16 Transmit or Receive Timing (16 bits stereo--1) Rev. 5.00 Dec 12, 2005 page 649 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (5) A Case of 16 bits Stereo (No.2) L/R method, rising edge sampling and Lch.transmit data are assigned to slot No. 0, Lch. receive data are assigned to slot No.1, Lch. receive data are assigned to slot No. 2, Rch. receive data is assigned to slot No. 3, and frame length is 64 bits. 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Slot No.0 No delay Setting: TRMD = 01, TDLE = 1, RDLE = 1, CD0E = 0, REDG = 1, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0001, CD0A3 to CD0A0 = 0000, FL = 1101 (frame length 64 bits), TDRE = 1, TDRA3 to TDRA0 = 0010, RDRE = 1, RDRA3 to RDRA0 = 0011, CD1E = 0, CD1A3 to CD1A0 = 0000 Lch. DATA Lch. DATA Slot No.1 Slot No.2 Rch. DATA Rch. DATA Slot No.3 Figure 20.17 Transmit or Receive Timing (16 bits stereo--2) (6) A Case of 16 bits Stereo (No. 3) Sync pulse method, falling edge sampling and Lch. data are assigned to slot No. 0, Rch. data is assigned to slot No. 2, control ch. data 0 is assigned to slot No. 1, control ch. data 0 is assigned to slot No. 3, and frame length is 128 bits. 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Lch. DATA Control ch. 0 Rch. DATA Control ch. 1 Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 1 bit delay Setting: TRMD = 00 or 10, TDLE = 1, RDLE = 1, CD0E = 1, REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0001, FL = 1110 (frame length 128 bits), TDRE = 1, TDRA3 to TDRA0 = 0010, RDRE = 1, RDRA3 to RDRA0 = 0010, CD1E = 1, CD1A3 to CD1A0 = 0011 Figure 20.18 Transmit or Receive Timing (16 bits stereo--3) Rev. 5.00 Dec 12, 2005 page 650 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (7) A Case of bits Monaural (No. 2) Sync pulse method, falling edge sampling and secondary FS are requested, Lch. data is assigned to slot No. 0, control ch. data 0 are assigned to slot No. 0, and frame length is 128 bits. (a) When the control ch. is not transferred 1 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Lch. DATA Slot No. 0 Slot No. 1 Slot No. 2 Slot No. 3 Slot No. 4 Slot No. 5 Slot No. 6 Slot No. 7 LSB = "0" (secondary FS request) 1 bit delay (b) When the control ch. is transferred 1/2 frame SCK_SIO SIOFSYN TXD_SIO RXD_SIO Normal FS Lch. DATA Slot No.0 1 bit delay Secondary FS Control ch.0 Slot No.1 Slot No.2 Slot No.3 Slot No.0 Slot No.1 Slot No.2 Slot No.3 LSB = "1" (secondary FS request) REDG = 0, TDLA3 to TDLA0 = 0000, RDLA3 to RDLA0 = 0000, CD0A3 to CD0A0 = 0000, FL = 1110 (frame length 128 bits), TDRE = 0, TDRA3 to TDRA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000 Normal FS 1 frame 1/2 frame Setting: TRMD = 01 TDLE = 1, RDLE = 1, CD0E = 1, Figure 20.19 Transmit or Receive Timing (16 bits monaural--2) Rev. 5.00 Dec 12, 2005 page 651 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 20.4 Usage Notes Note the following when using the SIOF. For details on using versions previous to the SH7727B please refer to 20.4.1, Notes on Using the SIOF with Versions Previous to the SH7727B, in addition to the notes below. 1. Using the transmit function in sleep mode If transmission is enabled when data has already been written to the transmit FIFO, one or two of the initial data bytes may be lost. Therefore, data should not be written to the transmit FIFO before enabling transmission. 2. Using control data transmission/reception consecutively on control data interface (secondary FS position) The TCRDY value may become 1 before transmit control data is sent, and if the next control data is written to the control data register at this point, the control data waiting to be sent will be overwritten and erased. At this time, also, the control sequence is disrupted and the SIOF switches around the primary FS and secondary FS, with the result that transmission/reception of data and control data can no longer be performed normally. The control data register should therefore be written to after transmit control data has been sent. Example: Reference RCRDY, and write to the control data register when RCRDY is 1. After transmit control data has been written, it is essential to read the receive control register (SIRCR) and clear RCRDY. 3. DMA transfer Do not use 16-byte DMA transfer. (See section 14.3.4, DMA Transfer Types.) 4. Access from the CPU When performing access from the CPU, do not access the SIOF's transmit/receive FIFO consecutively, but instead insert an access to somewhere else between SIOF transmit/receive FIFO accesses. 5. Transmit/receive FIFO underflow If the transmit/receive FIFO underflows during a transmit/receive operation, control of the SIOF's transmit/receive FIFO may fail and data may be lost. To prevent this, either set a watermark so that underflow does not occur, or execute a transmit reset (TXRST) or receive reset (RXRST) when an empty interrupt is generated. Rev. 5.00 Dec 12, 2005 page 652 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) 6. Transmit/receive reset execution When using the SIOF again after a transmit/receive operation ends, or after erroneous operation occurs, first execute a transmit reset (TXRST) or receive reset (RXRST). 7. Using the control data interface (slot position) Loss of transmit or control data may occur if transmit and control data are mixed within a single frame during a transmit operation in any of the following modes: (1) Master mode with an external clock (SIOMCLK) used as the master clock (2) Slave mode Therefore, the control data interface (slot position) should be used under the following conditions: (1) Master mode (2) Master clock: Peripheral clock (PCLK) 8. Serial IO (SIOF) reception operation During serial IO (SIOF) operation, if reception is performed with a slot length of 8 bits and LSB first, unwanted data is added at the start of the reception data, FIFO storage is delayed one byte at a time, and the final portion of the data remains in the shift register. To prevent this, use one of the three methods described below. (1) Perform reception using a slot length of 8 bits and LSB first, and read and discard the unwanted data. Read and discard the unwanted data at the start of the reception data. Then, input a dummy FS after the final portion of data so that the real final portion of data is stored in the FIFO. This will ensure that reception operates correctly when a slot length of 8 bits and LSB first is used. (2) Perform reception using a slot length of 8 bits and MSB first, then use software processing to convert the data to LSB-first format. Data reception operates correctly when a slot length of 8 bits and MSB first is used. After receiving the data in MSB-first format, use software processing to convert the data read from the FIFO from MSB-first to LSB-first format. The result can then be used as 8-bit slot length LSB-first data. (3) Perform reception using a slot length of 16 bits and LSB first, and read only the required data. Data reception operates correctly when a slot length of 16 bits and LSB first is used. Then one of the following two methods can be used to obtain data that can be used as 8-bit slot length LSB-first data. (a) Make settings on the transmitting side so that only the upper 8 bits are used for actual data. Then, after the 16-bit data is received by the SH7727, extract the upper 8 bits and use it as 8-bit slot length LSB-first data. Rev. 5.00 Dec 12, 2005 page 653 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) (b) Transmit two 8-bit units of data at once. Then, after the 16-bit data is received by the SH7727, separate the upper and lower 8-bit portions and treat them as two 8-bit units of data. They can then be used as 8-bit slot length LSB-first data. 20.4.1 Notes When using SIOF, the following phenomenon may occur. (1) During SIOF transmit with DMA transferring, SIOF may suddenly stop internal DMA transfer request, then underflow error ocurs and transmit operation stops. (2) During SIOF transmit and transmit FIFO empty, underflow or overflow, some data transmit may fail, depending on the timing relationship between transmit FIFO write in and read out. (3) During SIOF receive operation with DMA internal peripheral module request mode, some data receive may fail, due to unexpected overflow errors caused on the manner that only one data transfer request exceeding watermark of receive FIFO. (4) During receive operation, some receive data may fail when a write occurs at reading from receive FIFO. (5) During SIOF receive operation and receive FIFO empty, underflow or overflow, some data receive may fail, depending on the timing relationship between receive FIFO write in and read out. In this case, the statuses of full, underflow, and overflow may not be reflected to flags. Countermeasures Countermeasures to deal with software using SIOF. (1) Notes (1) and (2) With referring to transmit FIFO transfer request interrupt (SIFTXI) caused by under watermark of transmit FIFO, write the exactly same number of data with that of transmit FIFO empty slots with DMA auto request. At that time, make sure to set the watermark value so as not to occur transmit FIFO empty nor underflow when transmit operation. Example: When 12 empty slots are set to transmit FIFO, write 12 data to transmit FIFO with DMA auto request by transmit FIFO transfer interrupt (SIFTXI). (2) Notes (3), (4), and (5) With referring to receive FIFO transfer request interrupt (SIFRXI) caused by over watermark of receive FIFO, read the (valid number - 2) of data from receive FIFO with DMA auto request. Read operation shall be done before next receive data write. Rev. 5.00 Dec 12, 2005 page 654 of 1034 REJ09B0254-0500 Notes on Using the SIOF with Versions Previous to the SH7727B Section 20 Serial IO (SIOF) At that time, make sure to set the watermark value so as not to receive FIFO full nor overflow when receive operation. Example: When 12 empty slots are set to receive FIFO, read 12 data from receive FIFO with DMA auto request by receive FIFO transfer interrupt (SIFRXI). Etc. (1) Not to use DMA 16 bytes transfer. (See section 14.3.4, DMA Transfer Types.) (2) Recommend DMA auto request for SIOF access. When from CPU, not to use continuous access. (3) When newly use SIOF after transmit/receive operation, proceed transfer operation after transmit reset (TXRST) or receive reset (RXRST). Rev. 5.00 Dec 12, 2005 page 655 of 1034 REJ09B0254-0500 Section 20 Serial IO (SIOF) Rev. 5.00 Dec 12, 2005 page 656 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Section 21 Analog Front End Interface (AFEIF) 21.1 Overview This LSI has an AFE interface that supports softwaremodem. This AFE interface can efficiently execute the modem processing, because it includes 128 stages of FIFO for each of transmission and reception. This AFE interface also includes the interface to data access arrangement (DAA) such as dial pulse generator circuit and ringing detection. Therefore, it is possible to establish a modem system with a minimum of hardware. 21.1.1 Features * Serial interface with FIFO * Clock synchronized serial interface * Transmit/receive FIFO size is 16 bits (maximum) x 128 words * Transmit/receive interrupt threshold size is programmable * Dial pulse generator circuit is included * Ringing detection (calling signal) function is included Rev. 5.00 Dec 12, 2005 page 657 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.1.2 Block Diagram Figure 21.1 shows a block diagram of AFEIF. 32 16 Bus I/F pp-bus 16 Ringing detector 16 Dial pulse generator 16 Control registers 16 16 Tx_FIFO 16 bit x 128 word 16 16 Rx_FIFO 16 bit x 128 word AFE control word AFE status word HC control P/S S/P AFE_RDET AFE_RLYCNT AFE_FS AFE_SCLK AFE_TXOUT AFE_HC1 AFE_RXIN Figure 21.1 Block Diagram of AFE Interface Rev. 5.00 Dec 12, 2005 page 658 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.1.3 Pin Configuration Table 21.1 shows the pins for AFE interface. Table 21.1 Pins for AFE Interface Pin No. 121 114 116 118 119 113 120 Name AFE_RDET AFE_RLYCNT AFE_SCLK AFE_FS AFE_RXIN AFE_HC1 AFE_TXOUT I/O I O I I I O O Function Ringing signal input On-hook control signal Shift clock Frame synchronization signal Serial receive data AFE hardware control signal Serial transmit data 21.1.4 Register Configuration Table 21.2 shows registers for AFEIF. Byte access registers to these is inhibited. Table 21.2 AFEIF Registers Register Name AFEIF control register 1 AFEIF control register 2 AFEIF status register 1 AFEIF status register 2 Make ratio count register Minimum pose count register Dial number queue Ringing pulse counter AFE control data register AFE status data register Transmit data FIFO port Receive data FIFO port Abbreviation ACTR1 ACTR2 ASTR1 ASTR2 MRCR MPCR DPNQ RCNT ACDR ASDR TDFP RDFP R/W R/W R/W R/W R/W R/W R/W R/W R R/W R W R Initial Value H'0000 H'0000 H'0F0A H'0300 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Undetermined Undetermined Address H'04000180 H'04000182 H'04000184 H'04000186 H'04000188 H'0400018A H'0400018C H'0400018E H'04000190 H'04000192 H'04000194 H'04000198 Access Size 16 16 16 16 16 16 16 16 16 16 32 (16) 32 (16) Rev. 5.00 Dec 12, 2005 page 659 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.2 21.2.1 Register Description AFEIF Control Register 1 and 2 (ACTR1, ACTR2) ACTR is the control register for AFEIF and is composed of ACTR1 and ACTR2. ACTR1 is mainly used for FIFO control commands. ACTR2 is used for AFE control commands and DAA control commands. (1) AFEIF Control Register 1 (ACTR1) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 HC 0 R/W 7 DLB 0 R/W 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 FFSZ2 0 R/W 11 -- 0 R 3 FFSZ1 0 R/W 10 -- 0 R 2 FFSZ0 0 R/W 9 -- 0 R 1 TE 0 R/W 8 -- 0 R 0 RE 0 R/W Bits 14 to 8, 6, and 5--Reserved Bit 15--AFE Hardware Control Bit (HC): This bit controls AFE. AFE_HC1 signal is made to high directly often the next serial transmit data transfer, when this bit is written to 1. Then ACDR data (AFE control word) is transferred by founding the second AFE.FS. AFEIF module automatically makes AFE_HC1 signal to low and HC bit to 0, directly after transferring the AFE control word. See section 21.3.2, AFE Interface for more detail about AFE control sequences. Bit 7--FIFO Digital Loop Back (DLB) Bit 7: DLB 0 1 Description Normal operation (Initial value) Digital loop back between Tx FIFO and Rx FIFO is performed. In this time the transmit data is output to AFE_TXOUT, too. Rev. 5.00 Dec 12, 2005 page 660 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Bits 4 to 2--FIFO Interrupt Size Set 2 to 0 (FFSZ2 to FFSZ0): Specifies the size of FIFO. FIFO size to generate interrupt (TFE, RFF, THE, and RHF) is assigned as follows: Bit 4: FFSZ2 0 Bit 3: FFSZ1 0 1 1 0 1 Bit 2: FFSZ0 0 1 0 1 0 1 0 1 Description FIFO Size 128 64 32 16 8 4 2 96 TFE/RFF 128 empty/full 64 empty/full 32 empty/full 16 empty/full 8 empty/full 4 empty/full 2 empty/full 96 empty/full THE/RHF 64 empty/full 32 empty/full 16 empty/full 8 empty/full 4 empty/full 2 empty/full 1 empty/full 48 empty/full (Initial value) Bit 1--Tx Enable (TE) Bit 1: TE 0 Description Transmit operation is disabled. The READ pointer of FIFO is stacked to the first address. WRITE pointer is reset when 0 is written to this bit. TFEM and THEM bits in ASTR1 is set to 1 at that time. (Initial value) Transmit operation is enabled. 1 Bit 0--Rx Enable (RE) Bit 0: RE 0 1 Description Receive operation is disabled. The WRITE/READ pointer is fixed to the first address. RFFM and RHFM bits in ASTR1 is set to 1 at that time. Receive operation is enabled Rev. 5.00 Dec 12, 2005 page 661 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) (2) AFEIF Control Register 2 (ACTR2) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 DPST 0 R/W 11 -- 0 R 3 PPS 0 R/W 10 -- 0 R 2 RCEN 0 R/W 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 RLYC 0 R/W Bits 15 to 5, and 1--Reserved Bit 4--Dial Pulse Start (DPST): Start bit of dial pulse. Dial number within the DPNQ register is output to AFE_RLYCNT as specified by PPS, MRCR and MPCR. After all dial number is output , DPE interrupt is generated to modify the DPST bit to 0. See section 21.3.3, DAA Interface for more detail about dial pulse output sequence. Take care that AFE_RLYCNT must be "H" to enable dial pulse generating circuit Bit 3--Dial Pulse Duration Set (PPS) Bit 3: PPS 0 1 Description 10PPS 20PPS (Initial value) Bit 2--Ringing Counter Enable (RCEN) Bit 2: RCEN 0 1 Description Stop Ringing Counter Start Ringing Counter (Initial value) Note: See section 21.3.3, DAA Interface for more detail about how to count. Rev. 5.00 Dec 12, 2005 page 662 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Bit 0--Relay Control (RLYC): The signal controls Hook Relay. Bit 0: RLYC 0 1 Description On hook state. AFE_RLYCNT goes Low Level. Off hook state. AFE_RLYCNT goes High Level. (Initial value) 21.2.2 Make Ratio Count Register (MRCR) MRCR is the counter that specifies make ratio of dial pulse. Make interval is specified with AFE_FS as base clock of 9,600 Hz. Pulse signal is not output when an invalid data (a data that is greater than 1E0H in case of PPS = 1 (20 pps), or a data that is greater than 3C0H in case of PPS = 0 (10 pps)) was input. Bit: Initial value: R/W: 15 -- 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 to 0 MRCR 0 R/W 21.2.3 Minimum Pause Count Register (MPCR) MPCR is a counter that sets the dial number interval of the dial pulse. The interval is specified with AFE_FS as base clock of 9600 Hz. Bit: Initial value: R/W: 15 to 0 MPCR 0 R/W Rev. 5.00 Dec 12, 2005 page 663 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.2.4 AFEIF Status Register 1 and 2 (ASTR1, ASTR2) ASTR is the control register for AFEIF, and composed of ASTR1 and ASTR2. ASTR1 is mainly used for transmit/receive FIFO interrupt control commands. ASTR2 is used for DAA interrupt control commands. See section 21.3.1, Interrupt Timing for more detail about interrupt handling. (1) AFEIF Status Register 1 (ASTR1) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R/W 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 TFEM 1 R/W 3 TFE 1 R 10 RFFM 1 R/W 2 RFF 0 R 9 THEM 1 R/W 1 THE 1 R 8 RHFM 1 R/W 0 RHF 0 R ASTR1 is composed by interrupt status flags (4 bits) relating transmit/receive FIFO and mask flags (4 bits) for transmit/receive FIFO interrupt signal. Status flag displays full/empty interrupt status of transmit/receive FIFO and half size interrupt status for FIFO. FIFO empty (TFE) and FIFO half size interrupt(THE) shows "1" as initial value, because transmit FIFO is empty after power on reset. These interrupt flags are to be cleared with the data write / read action to FIFO from CPU. Each interrupt mask flag is able to prohibit interrupt generation of each interrupt that indicated in interrupt status flag. Every mask bits are automatically set when TE or RE bit are modified to 1. TFEM and THEM are 1 when TE = 0. RFFM and RHFM are "1" when RE = "0". Each mask bit are reset as 1. Bits 15 to 12 and 7 to 4--Reserved Bit 11--Tx FIFO Empty Interrupt Mask (TFEM) Bit 11: TFEM 0 1 Description TFE Interrupt enable TFE interrupt masked (Initial value) Rev. 5.00 Dec 12, 2005 page 664 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Bit 10--Rx FIFO Full Interrupt Mask (RFFM) Bit 10: RFFM 0 1 Description RFF Interrupt enable RFF Interrupt masked (Initial value) Bit 9--Threshold of Tx FIFO Empty Interrupt Mask (THEM) Bit 9: THEM 0 1 Description THE Interrupt enable THE Interrupt masked (Initial value) Bit 8--Threshold of Rx FIFO Full Interrupt Mask (RHFM) Bit 8: RHFM 0 1 Description RHF Interrupt enable RHF Interrupt masked (Initial value) Bit 3--Tx FIFO Empty Interrupt (TFE) Bit 3: TFE 0 1 Description Normal state TFIFO empty interrupt (Initial value) Set condition: 1. Reset 2. No effective data in area of FIFO 3. TE bit (ACTR1) is set to 0 (TFEM is automatically masked in case 3.) Clear condition: 1. Data are written into FIFO Rev. 5.00 Dec 12, 2005 page 665 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Bit 2--Rx FIFO Full Interrupt (RFF) Bit 2: RFF 0 1 Description No interrupt Rx FIFO full interrupt (Initial value) Set condition: 1. Specified size with FFSZ(ACTR1) of receive data is accumulated into FIFO. Clear condition: 1. Reset 2. Number of data in FIFO becomes smaller than the size that is indicated with FFSZ (ACTR1). 3. RE bit (ACTR1) is set to 0. Bit 1--TX FIFO Half Size Empty (THE) Bit 1: THE 0 1 Description Normal state Tx FIFO Half Size Interrupt (Initial value) Set condition: 1. Reset 2. Number of valid data in FIFO becomes smaller than the half of the size that is indicated with FFSZ. 3. TE bit (ACTR1) is set to 0 (THEM is automatically masked in case 3.) Clear condition: 1. Number of valid data in FIFO becomes greater than the half of the size that is indicated by FFSZ. Rev. 5.00 Dec 12, 2005 page 666 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Bit 0--RX FIFO Half Size Full (RHF) Bit 0: RHF 0 1 Description Normal state Rx FIFO half size interrupt (Initial value) Set condition: 1. The half of specified size with FFSZ (ACTR1) of receive data is accumulated into FIFO. Clear condition: 1. Reset 2. Number of data in FIFO becomes smaller than the half of the size that is indicated by FFSZ (ACTR1). 3. RE bit (ACTR1) is set to 0 (2) AFEIF Status Register 2 (ASTR2) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 -- 0 R 7 -- 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 DPEM 1 R/W 1 DPE 0 R/W 8 RDETM 1 R/W 0 RDET 0 R/W ASTR2 is the register that is composed of interrupt status flag (2 bits) relating DAA control and mask flag (2 bits) of interrupt signals for DAA control. Status flags shows statuses of ringing detect interrupt, end of dial pulse output interrupt. Interrupt flags are cleared by 0 write after read action of this register. Each Interrupt signal are able to be masked by each interrupt masks. Bit 9--Dial Pulse End Interrupt Mask (DPEM) Bit 9: DPEM 0 1 Description Interrupt enable Interrupt mask (Initial value) Rev. 5.00 Dec 12, 2005 page 667 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Bit 8--Ringing Detect Mask (RDETM) Bit 8: RDETM 0 1 Description Ringing interrupt enable Ringing interrupt mask (Initial value) Bit 1--Dial Pulse End (DPE) Bit 1: DPE 0 1 Description Normal state Dial pulse end interrupt (Initial value) Set condition: 1. Output of all of dial pulse sequences completed or end command 0H detected 2. Illegal end (unspecified dial number and DPST set when RLYC bit (ACTR2) is low level) Clear condition: 1. Reset 2. Interrupt status 1 is read and then 0 is written to this bit. Bit 0--Ringing Detect (RDET) Bit 0: RDET 0 1 Description Normal state Ringing waveform detect (Initial value) Set condition: 1. Ringing waveform is input to AFE_RDET pin (Latched at rising edge) Clear condition: 1. Reset 2. Interrupt status 1 is read and then 0 is written to this bit. Rev. 5.00 Dec 12, 2005 page 668 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.2.5 Dial Pulse Number Queue (DPNQ) This is the dial pulse number queue up to 4 digits which has 4-bits registers. This queue generates dial pulse according to the following table in the order of dial pulse number. A dial-pulse-end interrupt is sent out after DN3 is output or if 0H or a value other than the corresponding data is detected. Bit: Initial value: R/W: 15 to 12 DN0 0000 R/W 11 to 8 DN1 0000 R/W 7 to 4 DN2 0000 R/W 3 to 0 DN3 0000 R/W Table 21.3 Telephone Number and Data TEL No. 0 1 2 3 4 5 6 7 8 9 Pause End Corresponding Data AH 1H 2H 3H 4H 5H 6H 7H 8H 9H FH 0H Rev. 5.00 Dec 12, 2005 page 669 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.2.6 Ringing Pulse Counter (RCNT) The result of counting 1 cycle of ringing wave form with AFE_FS is shown here. Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R RCNT Bits 15 to 0--Ringing Counter Value (RCNTV): The result of counting 1 cycle of input ringing wave form with AFE_FS (output of AFE). See section 21.3.3, DAA Interface for more detail about the ringing detect sequence. 21.2.7 AFE Control Data Register (ACDR) ACDR is the register to store the AFE control word. After 1 is written to HC bit (ACTR1), data is transferred to AFE at the timing of 3rd FS. Bit: Initial value: 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 ACDR R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 21.2.8 AFE Status Data Register (ASDR) ASDR is the register to store the AFE status word. After 1 is written to HC bit (ACTR2), data is transferred to ASDR from AFE at the timing of 3rd FS. Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R ASDR Rev. 5.00 Dec 12, 2005 page 670 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.2.9 Transmit Data FIFO Port (TDFP) TDFP is the write only port for transmit FIFO. Transmit FIFO has 128 stages (maximum), and can generate interrupt of the data empty as well as of the threshold size specified by FFSZ (ACTR1). Directly after the reset and when TE (ACTR1) bit is 0, the pointer of FIFO is set to the first address and data becomes empty. The interrupt will occur when the TE bit (ACTR1) is written to 1 at that state. In normal case, TE bit should be changed after writing data into transmit FIFO. Bit: Initial value: R/W: 15 W 14 W 13 W 12 W 11 W 10 W 9 W 8 W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W TDFP 21.2.10 Receive Data FIFO Port (RDFP) RDFP is the read only register for receive FIFO. Receive FIFO has 128 stages (maximum), and can generate interrupt of the data full as well as of the threshold size specified by FFSZ (ACTR1). Directly after the reset and when RE bit (ACTR1) is 0, the pointer of FIFO is fixed at the first address and data from RDFP becomes undetermined. Bit: Initial value: R/W: 15 R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 R RDFP 21.3 21.3.1 Operation Interrupt Timing AFE interface module generates 3 types of interrupt: FIFO data transfer, ringing detect, and dial pulse transmit end. The timing of each interruption is described below. (1) FIFO Interrupt Timing Figure 21.2 shows interrupt timing of data transfer FIFO. Transmit FIFO generates the TFE and THE interrupts after the last data is transfer red shift register. Receive FIFO generates the RFF and RHF interrupt after the last data or specified word is transferred from shift register to FIFO. Rev. 5.00 Dec 12, 2005 page 671 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) AFE_FS AFE_TX OUT TFE/TTE AFE_FS AFE_RX IN RFF/RTF First First+1 Half-1 Half Data 1 Data 2 Half-1 Half Figure 21.2 FIFO Interrupt Timing (2) Ringing Interrupt Timing As the figure 21.3 shows, the ringing signal from the line is transformed to rectangular wave and then input to AFEIF. The interrupt is generated at the rising edge of input wave in AFEIF module. Ringing wave Input wave INT. occur Figure 21.3 Ringing Interrupt Occurrence Timing (3) Dial Pulse Interrupt Timing Dial pulse interrupt is generated in the dial pulse transmit sequence when AFEIF reads 0H (end) data from DPNQ register or all of 4 digits are output. Refer to section 21.3.3, DAA Interface about dial pulse sequence. Rev. 5.00 Dec 12, 2005 page 672 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) (4) Interrupt Generator Circuit Interrupt is generated as is shown in figure 21.4. That is, AFEIFI signal is generated by performing OR operation on the four signals from ASTR1 in FIFO interrupt control and the two signals from ASTR2 in DAA interrupt control, and then sent out to INTC as one interrupt signal. ASTR1 (FIFO cont.) INT. mask 4 INT. factor 4 4 AFEIFI 2 2 ASTR2 (DAA cont.) INT. mask 2 INT. factor Figure 21.4 Interrupt Generator 21.3.2 AFE Interface (1) Serial Data Transfer Specification The specification for serial data transfer is base on that of STLC7550, which is an AFE manufactured by ST microelectronics. STLC7550 has a self-oscillation mode, and flame synchronous signal AFE_FS used for serial transfer and serial bit clock AFE_SCLK are supplied by AFE. Figure 21.5 shows the serial transfer interface. After outputting the valid data, AFE_TXOUT holds the value of LSB. Sampling period AFE_FS AFE_SCLK AFE_TXOUT MSB LSB AFE_RXIN Figure 21.5 AFE Serial Interface Rev. 5.00 Dec 12, 2005 page 673 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) (2) HC Control Sequence AFEIF module supports hardware control STLC7550 that is an AFE manufactured by ST microelectronics. Figure 21.6 shows the AFE control sequence. Sampling period 1/2 sampling period (3) AFE_FS AFE_TXOUT Data word Data word Control word Data word Write 1 to HC bit of ACTR1 (5) Mode change (1) (2) (4) AFE_HC1 HC0: Kept to 1 AFE I/F Write "1" to HC bit of ACTR1 DATA STLC7550 FS for data DATA FS for data HC1 goes to 1 DATA DATA FS for data FS for control word FS for data AFE mode change FS for data HC1 goes to 0 DATA DATA 1. If the CPU write "1" to the HC bit of ACTR1, the AEFIF drives AFE_HC1 to "H" right after transmit next data. 2. AFE fetches the HC1's status of "H" at rising edgge of next AFE_FS. 3. AFE output the FS at the next 1/2 sampling period and then AFEIF transfer the AFE control word. 4. AFEIF keeps AFE_HC1 to "H" for 2nd FS and return to "L" after transmit the control word. 5. AFE fetches the AFE_HC1's status of "L" and changes the mode of itself. Figure 21.6 AFE Control Sequence Rev. 5.00 Dec 12, 2005 page 674 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 21.3.3 DAA Interface Figure 21.7 shows the blocks diagram of DAA circuit. Ringing detect and dial pulse sending sequence are described below. AFE_RLYCNT Hyblid circuit Hook relay Tip AFEIF AFE (STLC7550) DC holding circuit Ring AFE_RDET Ringing detector Figure 21.7 DAA Block Diagram (1) Ringing Detect Sequence After the first ringing interrupt occurs, counting starts with writing 1 into RCEN bit of CTR2. AFE must be operating before counting, because periodic counter counts AFE_FS from falling edge to next falling edge. The value of RCNTV register is effective only after 2nd interrupt generation, because the value of RCNTV register is transferred from counter with a trigger of ending of 1st period cycle. RCNTV will be 258H (600 in decimal) if ringing cycle is 16Hz and counted by 9600Hz which is default value of AFE_FS. Figure 21.8 shows detecting sequence of ringing. Rev. 5.00 Dec 12, 2005 page 675 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Count up RCNTV RCNTV RCNTV set set set RCNTV set 1. First INT occur. RCEN (ACTR2) turns on. 2. From 2nd INT, read the RCNTV. 3. After acknowledge the ringing, RCEN (ACTR) turns off and goes to off hook operation. Figure 21.8 Ringing Detect Sequence (2) Dial Pulse Sending Sequence A dial pulse is generated according to the conditions that are specified in ACTR2, and is sent out to AFE_RLYCNT. As the basic clock for generating the dial pulse is AFE_FS that is input from AFE, it is necessary to make AFE in operating state. An example of control sequence for dial pulse sending is shown below. Note that this sequence cannot be operated when RLYC bit (ACTR2) is low. [Conditions] Make ratio: Pulse interval: Dial number: 33% 20 PPS 0,1234567 ("," means pause) Minimum pause: 600 ms [Control sequence] 1. Set PPS (ACTR2) "1", MKR "9EH1", MNRPCNT "1680H" 2. Set DPNQ "AF12H". 3. Set RLYC "H". (Off Hook) Rev. 5.00 Dec 12, 2005 page 676 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) 4. Detect dial tone or wait specific period. (Controlled by software) 5. Write "1" to DPST (ACTR2). (Start sending dial pulse) 6. After 4 digit of dial pulses are sent, interrupt is generated. (DPST is reset to "0") 7. Set DPNQ1 "3456H". 8. Write "1" to DPST (ACTR2). 9. After 4 digit of dial pulses are sent, interrupt is generated. (DPST is reset to "0") 10. Set DPNQ2 "70XXH". 11. Write "1" to DPST (ACTR2). 12. After 1 digit of dial pulse is sent, interrupt is generated. (DPST is reset to "0", finish sending) 21.3.4 Wake up Ringing Interrupt System wake up function by the ringing signal from telephone line is realized by inputting AFE_RDET signal, that is an input signal for ringing, to PINT pin. Rev. 5.00 Dec 12, 2005 page 677 of 1034 REJ09B0254-0500 Section 21 Analog Front End Interface (AFEIF) Rev. 5.00 Dec 12, 2005 page 678 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller Section 22 USB Pin Multiplex Controller 22.1 Feature The USB multiplex controller controls the data path to USB transceiver from USB host controller port 1 or USB function controller. Both USB host port 1 and USB function controller are connected to USB transceiver 1 via multiplexer that is controlled by EXPFC register. The USB host controller port 2 and USB transceiver 2 are connected one-to-one. USB transceiver 1 can be connected to USB host controller or USB function controller, while USB transceiver 2 can only be connected to the USB host controller. Because these ports and transceivers are controlled individually, USB transceiver 2 can be connected to either the USB host controller or the USB function controller regardless its status. The signals to USB transceiver are used as external pins USB1d _**** which are multiplexed with pins 113 to 122. Rev. 5.00 Dec 12, 2005 page 679 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller 22.1.1 Block Diagram Figure 22.1 shows the connections between the on-chip USB host controller of the SH7727, the USB function controller, and the on-chip 2-port USB transceiver. USB host pwr_en ovr_current Transceiver pwr_en Power Port 1 Transceiver Power Port 2 Transceiver USB2_pwr_en USB2_ovr_current USB transceiver 2 USB2P USB2M ovr_current pwr_en/ control pin multiplexer ovr_current/ VBUS multiplexer USB1_pwr_en USB1_ovr_current/ USBF_VBUS Control USB function USB host/function transceiver signals multiplexer Select Select USB digital signal USB1d_**** Power Port 1 Transceiver VBUS Transceiver USB transceiver 1 USB1P USB1M Figure 22.1 Block Diagram of USB PIN Multiplexer Rev. 5.00 Dec 12, 2005 page 680 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller 22.1.2 Pin Configuration USB pin multiplexer controller has pins that are shown in tables 22.1, 22.2, and 22.3 Table 22.1 Pin Configuration (Digital Transceiver Signal) Name RCV pin DPLS pin DMNS pin TXDPLS pin TXENL pin SUSPEND pin SPEED pin TXSE0 pin Symbol USB1d_RCV USB1d_DPLS USB1d_DMNS USB1d_TXDPLS USB1d_TXENL USB1d_SPEED USB1d_TXSE0 I/O Input Input Input Output Output Output Output Description Input pin for receive data from differential receiver Input pin for D+ signal from receiver Input pin for D- signal from receiver D+ transmit output pin Driver output enable pin Transceiver suspend state output pin Transceiver speed control pin SE0 state output pin USB1d_SUSPEND Output Note: The pins shown in table 22.1 are used for connecting an external USB transceiver, and cannot be used when the on-chip USB transceiver is connected. Table 22.2 Pin Configuration (Analog Transceiver Signal) Name 1P pin 1M pin 2P pin 2M pin Symbol USB1P USB1M USB2P USB2M I/O I/O I/O I/O I/O Description D+ port1 transceiver pin D- port1 transceiver pin D+ port2 transceiver pin D- port2 transceiver pin Note: The pins shown in table 22.2 can be used as two ports USB host controller pins, or one port USB host controller pins and one port USB function controller pins. make these pins open, when they are not used. Rev. 5.00 Dec 12, 2005 page 681 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller Table 22.3 Pin Configuration (Power Control signal) Name Power enable pin 1 Power enable pin 2 One current pin 1/ VBUS pin Over current pin 2 Symbol USB1_pwr_en USB2_pwr_en USB1_ovr_current/ USBF_VBUS USB2_ovr_current I/O Output Output Input Input Description USB port 1 power enable control USB port 2 power enable control USB port 1 over-current detect/ USB cable connection monitor pin USB port2 Over-current detect Note: The pins shown in table 22.3 can be used for power control of USB. Pins for port 1 have the functions that are multiplexed functions of USB controller and USB function controller. 22.1.3 Register Configuration Table 22.4 shows the registers for USB pin multiplexer controller. Table 22.4 Register Configuration Name Extra pin function controller Abbreviation EXPFC R/W R/W Initial Value H'0000 Address H'A4000234 Access Size 16 Rev. 5.00 Dec 12, 2005 page 682 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller 22.2 22.2.1 Register Description Extra Pin Function Controller (EXPFC) Bit: 15 -- 0 R 7 -- 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R/W* 12 -- 0 R 4 -- 0 R/W* 11 -- 0 R 3 -- 0 R/W* 10 -- 0 R 2 -- 0 R/W* 9 -- 0 R 1 USB_ TRANS 8 -- 0 R 0 USB_SEL Initial value: R/W: Bit: Initial value: R/W: 0 R 0 W 0 W Note: * 0 must be set in reading or writing. Bits 15 to 2--Reserved: Write 0 to these bits. When 1 is written to this bits, the operation is unpredictable. Bit 1--USB Port 1 Transceiver (USB_TRANS) Bit 1 0 1 Function USB transceiver is enabled USB digital signals output is enabled (Initial value) Bit 0--USB Port 1 Signal Source Selection (USB_SEL) Bit 0 0 1 Function (signal source selection) USB HOST is used USB Function is used (Initial value) Note: USB port 2 is for dedicated use by the USB host controller. Rev. 5.00 Dec 12, 2005 page 683 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller 22.3 22.3.1 Examples of External Circuit Example of the Connection between USB Function Controller and Transceiver Figures 22.2 to 22.5 show example connections of USB function controller and transceiver. Figures 22.2 and 22.3 show connections when using the built-in USB transceiver. Figures 22.4 and 22.5 show connections when not using the built-in USB transceiver. When using the USB function controller, the signals must be input to the cable connection monitor pin UJBF_VBUS. The USBF_VBUS pin is multiplexed with the USB1_ovr_current pin, and writing 1 to bit 0 of the EXPFC register selects the USBF_VBUS pin functions. According to the status of the USBF_VBUS pin, the USB function controller recognizes whether the cable is connected/disconnected. Also, pin D+ must be pulled up in order to notify the USB host/hub that the connection is established. The sample circuits in figures 22.2 to 22.5 use the USB1_pwr_en pin for pull-up control. SH7727 USB1_pwr_en IC allowing voltage application when system power is off IC2 IC1 USBF_VBUS USB1P USB1M USB1d_SPEED USB1d_TXENL USB1d_TXDPLS USB1d_TXSEO USB1d_RCV USB1d_DPLS USB1d_DMNS USB1d_SUSPEND GND D- 27 27 3.3V IC allowing voltage application when system power is off D+ 1.5k USB connector 5V USB function VBUS Figure 22.2 Example 1 of Transceiver Connection for USB function Controller (On-chip transceiver is used) Rev. 5.00 Dec 12, 2005 page 684 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller SH7727 USB1_pwr_en USB function IC1 USBF_VBUS USB1P USB1M USB1d_SPEED USB1d_TXENL USB1d_TXDPLS USB1d_TXSEO USB1d_RCV USB1d_DPLS USB1d_DMNS USB1d_SUSPEND GND D- 27 27 3.3V IC allowing voltage application when system power is off D+ IC allowing voltage application when system power is off IC2 1.5k USB connector 5V VBUS Figure 22.3 Example 2 of Transceiver Connection for USB function Controller (On-chip transceiver is used) Rev. 5.00 Dec 12, 2005 page 685 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller SH7727 USB1_pwr_en IC allowing voltage application when system power is off IC2 IC1 USBF_VBUS 3.3V IC allowing voltage application when system power is off USB1d_SPEED USB1d_TXENL USB1d_TXDPLS USB1d_TXSEO USB1d_RCV USB1d_DPLS USB1d_DMNS USB1d_SUSPEND SPEED OE VPO D- VMO/FSEO RCV VP VM SUSPEND D+ USB function 1.5k USB connector 5V VBUS D+ D- GND PDIUSBP11A etc. Figure 22.4 Example 3 of Transceiver Connection for USB function Controller (On-chip transceiver is not used) Rev. 5.00 Dec 12, 2005 page 686 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller SH7727 USB1_pwr_en USB function IC1 USBF_VBUS 3.3V IC allowing voltage application when system power is off IC allowing voltage application when system power is off IC2 1.5k USB connector 5V VBUS USB1d_SPEED USB1d_TXENL USB1d_TXDPLS USB1d_TXSEO USB1d_RCV USB1d_DPLS USB1d_DMNS USB1d_SUSPEND SPEED OE VPO D+ D+ D- VMO/FSEO RCV VP VM SUSPEND D- GND PDIUSBP11A etc. Figure 22.5 Example 4 of Transceiver Connection for USB function Controller (On-chip transceiver is not used) Rev. 5.00 Dec 12, 2005 page 687 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller D+ Pull-up Control Control D+ pull-up by using USB1_pwr_en pin in the system when the connection--notification (D+ pull-up) to USB host or hub is wished to be inhibited (i.e., during high-priority processing or initialization processing). The D+ pull-up control signal and USBF_VBUS pin input signal should be controlled by using the USB1_pwr_en pin and the USB cable VBUS (AND circuit) as is shown in examples of figures 22.2 and 22.4 D+ pull-up is inhibited when the USB1_pwr_en pin is high in examples of figures 22.2 to 22.5. (The initial setting of the USB1_pwr_en pin is High.) Pull-up D+ after confirming that USBF_VBUS pin became high, when the pull-up control is performed directly by USB1_pwr_en pin as is shown in examples of figures 22.3 and 22.5. D+ pull-up is inhibited when the USB1_pwr_en pin is low in examples of figures 22.3 and 22.5. Use an IC such that allows voltage application when system power is off (for example, HD74LV1G126A) for the pull-up control IC (IC2 in figures 22.2 to 22.5). (The UDC core in the SH7727 holds the powered state when USBF_VBUS pin is low, regardless of the D+/D- state.) Detection of USB Cable Connection/Disconnection As USB function controller in the SH7727 manages the state by hardware, USB_VBUS signal is necessary to recognize connection or disconnection of the USB cable. The power supply signal (VBUS) in the USB cable is used for USBF_VBUS. However, if the cable is connected to the USB host or hub when the power of USB function controller (SH7727--installed system) is off, a voltage of 5 V will be applied from the USB host or hub. Therefore, use an IC such that allows voltage application when system power is off (for example, HD74LV1G08A) for the IC1 in figures 22.2 to 22.5. Rev. 5.00 Dec 12, 2005 page 688 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller 22.3.2 Example of the Connection between USB Host Controller and Transceiver Figures 22.6 and 22.7 show example connections of the USB host controller and transceiver. Figure 22.6 shows an example connection using the built-in transceiver 1. By using the USB2_ovr_current, USB2_pwr_en, USB2P, and USB2M pins in an external circuit similar to that in figure 22.6, you can also use built-in USB transceiver 2. Figure 22.7 shows an example connection when not using the built-in USB transceiver. When using the USB host controller, a separate LSI must be used for USB power bus control (equivalent to the USB power control LSIs in figures 22.6 and 22.7). Make sure the LSI has the power supply capacity to satisfy the USB standard, and select one that has an overcurrent protection function. Configure the system so that the input to the USB1_ovr_current pin is Low on detection of an overcurrent. SH7727 USB host USB1_ovr_current USB1_pwr_en USB power control LSI USB connector 5V GND USB1P 27 15k D+ USB1M 27 15k D- Figure 22.6 Example 1 of Transceiver Connection for USB Host Controller (On-chip transceiver is used) Rev. 5.00 Dec 12, 2005 page 689 of 1034 REJ09B0254-0500 Section 22 USB Pin Multiplex Controller SH7727 USB host USB1_ovr_current USB1_pwr_en USB power control LSI USB connector 5V GND USB1d_SPEED USB1d_TXENL USB1d_TXDPLS USB1d_TXSEO USB1d_RCV USB1d_DPLS USB1d_DMNS USB1d_SUSPEND SPEED OE VPO D+ D+ 15k D- 15k D- VMO/FSEO RCV VP VM SUSPEND PDIUSBP11A etc. Figure 22.7 Example 2 of Transceiver Connection for USB Host Controller (On-chip transceiver is not used) 22.3.3 Usage Notes About the USB Transceiver USB transceiver is included in the SH7727. it is also possible to connect an external transceiver according to the setting in EXPFC register (see figures 22.4, 22.5, and 22.7). In this case, ask the manufacturer of the transceiver about the recommended circuit that is used between the USB transceiver and USB connectors. About the Examples of External Circuit These examples of transceiver connection in this chapter are for reference only, therefore proper operation is not guaranteed with these circuit examples. If system countermeasures are required for external surges and ESD noise, use a protective diode, etc. Rev. 5.00 Dec 12, 2005 page 690 of 1034 REJ09B0254-0500 Section 23 USB Function Controller Section 23 USB Function Controller 23.1 Features * Incorporates UDC (USB device controller) conforming to USB1.1 Automatic processing of USB protocol Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) * Transfer speed: Full-speed * Endpoint configuration Endpoint Name Endpoint 0 Abbreviation EP0s EP0i EP0o Endpoint 1 Endpoint 2 Endpoint 3 EP1 EP2 EP3 Transfer Type Setup Control-in Control-out Bulk-out Bulk-in Interrupt Maximum Packet Size 8 8 8 64 64 8 FIFO Buffer Capacity 8 8 8 128 128 8 End point 1 End point 2 End point 3 DMA Transfer -- -- -- Possible Possible -- Configuration 1 -- Interface 0 -- Alternate setting 0 * Interrupt requests: generates various interrupt signals necessary for USB transmission/reception * Clock: Selection by means of EXCPG For details, see section 11, Extend Clock Pulse Generator for USB (EXCPG). * Power-down mode Power consumption can be reduced by stopping internal clock when UDC cable is disconnected Automatic transition to/recovery from suspend state * Can be connected to a Philips PDIUSBP11 Series transceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand) * This USB function controller is a self-power device. It cannot operate by power supplied from the USB cable. Rev. 5.00 Dec 12, 2005 page 691 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.2 Block Diagram Internal peripheral bus USB function module Status and control registers UDC FIFO (288 bytes) Interrupt requests DMA transfer requests To transceiver Clock (48 MHz) UDC: USB device controller Figure 23.1 Block Diagram of UBC 23.3 Pin Configuration Table 23.1 Pin Configuration and Functions Pin Name USBF_VBUS USB1_pwr_en I/O Input Output Function USB cable connection monitor pin USB1 power control pin Can be connected to a Philips PDIUSBP11 series transceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand). See section 22, USB Pin Multiplex Controller, for connection to the USB transceiver. Rev. 5.00 Dec 12, 2005 page 692 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.4 Register Configuration Table 23.2 USB Function Module Registers Name USBEP0i data register USBEP0o data register USBEP0s data register USBEP1 data register USBEP2 data register USBEP3 data register Interrupt flag register 0 Interrupt flag register 1 Trigger register FIFO clear register USBEP0o receive data size register Data status register Endpoint stall register Interrupt enable register 0 Interrupt enable register 1 USBEP1 receive data size register USBDMA setting register Abbreviation USBEPDR0I USBEPDR0O USBEPDR0S USBEPDR1 USBEPDR2 USBEPDR3 USBIFR0 USBIFR1 USBTRG USBFCLR USBEPSZ0O USBDASTS USBEPSTL USBIER0 USBIER1 USBEPSZ1 USBDMA R/W W R R R W W R/W R/W W W R R R/W R/W R/W R R/W Initial Value -- -- -- -- -- -- H'10 H'00 -- -- H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address Access Size 8 H'04000242 (H'A4000242)* H'04000243 8 (H'A4000243)* H'04000247 (H'A400247)* 8 H'0400024E 8 (H'A400024E)* 8 H'04000249 (H'A4000249)* H'04000252 8 (H'A4000252)* H'04000240 8 (H'A4000240)* 8 H'04000241 (H'A4000241)* H'04000244 8 (H'A4000244)* 8 H'04000245 (H'A4000245)* H'04000246 8 (H'A4000246)* H'04000248 8 (H'A4000248)* H'0400024B 8 (H'A400024B)* H'0400024C 8 (H'A400024C)* 8 H'0400024D (H'A400024D)* H'0400024F 8 (H'A400024F)* 8 H'04000251 (H'A4000251)* Rev. 5.00 Dec 12, 2005 page 693 of 1034 REJ09B0254-0500 Section 23 USB Function Controller Name Interrupt select register 0 Interrupt select register 1 Abbreviation USBISR0 USBISR1 R/W R/W R/W Initial Value H'00 H'07 Address Access Size H'0400024A 8 (H'A400024A)* H'04000250 8 (H'A4000250)* Note: * If the MMU does not convert addresses, use addresses in parentheses. 23.5 23.5.1 Register Descriptions USBEP0i Data Register (USBEPDR0I) USBEPDR0I is an 8-byte FIFO buffer for endpoint 0, holding one packet of transmit data for control-in. Transmit data is fixed by writing one packet of data and setting bit 0 in the USB trigger register. When an ACK handshake is returned from the host after the data has been transmitted, EP0i TS in USB interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP0i CLR in the USBFIFO clear register. 23.5.2 USBEP0o Data Register (USBEPDR0O) USBEPDR0O is an 8-byte receive FIFO buffer for endpoint 0. USBEPDR0O holds endpoint 0 receive data other than setup commands. When data is received normally, EP0o TS in USB interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting EP0o RDFN in the USB trigger register enables the next packet to be received. This FIFO buffer can be initialized by means of EP0o CLR in the USBFIFO clear register. 23.5.3 USBEP0s Data Register (USBEPDR0S) USBEPDR0S is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception. USBEPDR0S receives only setup commands requiring processing on the application side. When command data is received normally, SETUP TS in USB interrupt flag register 0 is set. As a setup command must be received without fail, if data is left in this buffer, it will be overwritten with new data. If reception of the next command is started while the current command is being read, command reception has priority, the read by the application is forcibly terminated, and the read data is invalid. Rev. 5.00 Dec 12, 2005 page 694 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.5.4 USBEP1 Data Register (USBEPDR1) USBEPDR1 is a 128-byte receive FIFO buffer for endpoint 1. USBEPDR1 has a dual-FIFO configuration, and has a capacity of twice the maximum packet size. When one packet of data is received normally from the host, EP1 FULL in USB interrupt flag register 0 is set. The number of receive bytes is indicated in the USBEP1 receive data size register. After the data has been read, the buffer that was read is enabled to receive again by writing 1 to EP1 RDFN in the USB trigger register. The receive data in this FIFO buffer can be transferred by DMA (see section 23.5.19, USBDMA Setting Register (USBDMAR)). This FIFO buffer can be initialized by means of EP1 CLR in the USBFIFO clear register. 23.5.5 USBEP2 Data Register (USBEPDR2) USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and EP2 PKTE in the USB trigger register is set, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. Transmit data for this FIFO buffer can be transferred by DMA (see section 23.5.19, USBDMA Setting Register (USBDMAR)). This FIFO buffer can be initialized by means of EP2 CLR in the USBFIFO clear register. 23.5.6 USBEP3 Data Register (USBEPDR3) USBEPDR3 is an 8-byte transmit FIFO buffer for endpoint 3, holding one packet of transmit data in endpoint 3 interrupt transfer. Transmit data is fixed by writing one packet of data and setting EP3 PKTE in the USB trigger register. When an ACK handshake is received from the host after one packet of data has been transmitted normally, EP3 TS in the USB interrupt flag register 1 is set. This FIFO buffer can be initialized by means of EP3 CLR in the USB FIFO clear register. 23.5.7 USB Interrupt Flag Register 0 (USBIFR0) Together with USB interrupt flag register 1, USBIFR0 indicates interrupt status information required by the application. When an interrupt source occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 0. Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. However, EP1 FULL and EP2 EMPTY are status bits, and cannot be cleared. Rev. 5.00 Dec 12, 2005 page 695 of 1034 REJ09B0254-0500 Section 23 USB Function Controller Bit: 7 BRST Initial value: R/W: 0 R/W 6 EP1 FULL 0 R 5 EP2 TR 0 R/W 4 EP2 EMPTY 1 R 3 SETUP TS 0 R/W 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W Bit 7--Bus Reset (BRST): Set to 1 when the bus reset signal is detected on the USB bus. Bit 6--EP1 FIFO Full (EP1 FULL): This bit is set when endpoint 1 receives one packet of data normally from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer. EP1 FULL is a status bit, and cannot be cleared. Bit 5--EP2 Transfer Request (EP2 TR): This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 2 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. Bit 4--EP2 FIFO Empty (EP2 EMPTY): This bit is set when at least one of the dual endpoint 2 transmit FIFO buffers is ready for transmit data to be written. EP2 EMPTY is a status bit, and cannot be cleared. Bit 3--Setup Command Receive Complete (SETUP TS): This bit is set to 1 when endpoint 0 receives normally a setup command requiring decoding on the application side, and returns an ACK handshake to the host. Bit 2--EP0o Receive Complete (EP0o TS): This bit is set to 1 when endpoint 0 receives data from the host normally, stores the data in the FIFO buffer, and returns an ACK handshake to the host. Bit 1--EP0i Transfer Request (EP0i TR): This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 0 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. Bit 0--EP0i Transmit Complete (EP0i TS): This bit is set when data is transmitted to the host from endpoint 0 and an ACK handshake is returned. Rev. 5.00 Dec 12, 2005 page 696 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.5.8 USB Interrupt Flag Register 1 (USBIFR1) Together with USB interrupt flag register 0, USBIFR1 indicates interrupt status information required by the application. When an interrupt source occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 1. Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 VBUSMN 0 R 2 EP3 TR 0 R/W 1 EP3 TS 0 R/W 0 VBUSF 0 R/W Bits 7 to 4--Reserved: These bits are always read as 0. The write value should always be 0. Bit 3--USB Connect Status (VBUSMN): This bit is a status bit for monitoring the state of the USBF_VBUS pin. It reflects the state of the USBF_VBUS pin. Bit 2--EP3 Transfer Request (EP3 TR): This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. Bit 1--EP3 Transmit Complete (EP3 TS): This bit is set when data is transmitted to the host from endpoint 3 and an ACK handshake is returned. Bit 0--USB Bus Connect (VBUSF): This bit is set to 1 when connecting to or disconnecting from the USB bus. The USBF_VBUS pin is used to detect connection/disconnection. The USBF_VBUS pin must be connected, as it is needed inside the module. Rev. 5.00 Dec 12, 2005 page 697 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.5.9 USB Trigger Register (USBTRG) USBTRG generates one-shot triggers to control the transmit/receive sequence for each endpoint. Bit: 7 -- R/W: W 6 EP3 PKTE W 5 EP1 RDFN W 4 EP2 PKTE W 3 -- W 2 EP0s RDFN W 1 EP0o RDFN W 0 EP0i PKTE W Bit 7--Reserved Bit 6--EP3 Packet Enable (EP3 PKTE): After one packet of data has been written to the endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. Bit 5--EP1 Read Complete (EP1 RDFN): Write 1 to this bit after one packet of data has been read from the endpoint 1 FIFO buffer. The endpoint 1 receive FIFO buffer has a dual-FIFO configuration. Writing 1 to this bit initializes the FIFO that was read, enabling the next packet to be received. Bit 4--Endpoint 2 Packet Enable (EP2 PKTE): After one packet of data has been written to the endpoint 2 FIFO buffer, the transmit data is fixed by writing 1 to this bit. Bit 3--Reserved Bit 2--EP0s Read Complete (EP0s RDFN): Write 1 to this bit after EP0s command FIFO data has been read. Writing 1 to this bit enables transmission/reception of data in the following data stage. A NACK handshake is returned in response to transmit/receive requests from the host in the data stage until 1 is written to this bit. Bit 1--EP0o Read Complete (EP0o RDFN): Writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit FIFO buffer initializes the FIFO buffer, enabling the next packet to be received. Bit 0--EP0i Packet Enable (EP0i PKTE): After one packet of data has been written to the endpoint 0 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. Rev. 5.00 Dec 12, 2005 page 698 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.5.10 USBFIFO Clear Register (USBFCLR) USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transmission/reception. Bit: 7 -- R/W: W 6 EP3 CLR W 5 EP1 CLR W 4 EP2 CLR W 3 -- W 2 -- W 1 EP0o CLR W 0 EP0i CLR W Bit 7--Reserved Bit 6--EP3 Clear (EP3 CLR): When 1 is written to this bit, the endpoint 3 transmit FIFO buffer is initialized. Bit 5--EP1 Clear (EP1 CLR): When 1 is written to this bit, both FIFOs in the endpoint 1 receive FIFO buffer are initialized. Bit 4--EP2 Clear (EP2 CLR): When 1 is written to this bit, both FIFOs in the endpoint 2 transmit FIFO buffer are initialized. Bits 3 and 2--Reserved Bit 1--EP0o Clear (EP0o CLR): When 1 is written to this bit, the endpoint 0 receive FIFO buffer is initialized. Bit 0--EP0i Clear (EP0i CLR): When 1 is written to this bit, the endpoint 0 transmit FIFO buffer is initialized. 23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) USBEPSZ0O indicates, in bytes, the amount of data received from the host by endpoint 0. Rev. 5.00 Dec 12, 2005 page 699 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.5.12 USB Data Status Register (USBDASTS) USBDASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all data has been transmitted to the host. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 EP3 DE 0 R 4 EP2 DE 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 EP0i DE 0 R Bits 7 and 6--Reserved: These bits are always read as 0. The write value should always be 0. Bit 5--EP3 Data Present (EP3 DE): This bit is set when the endpoint 3 FIFO buffer contains valid data. Bit 4--EP2 Data Present (EP2 DE): This bit is set when the endpoint 2 FIFO buffer contains valid data. Bits 3 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--EP0i Data Present (EP0i DE): This bit is set when the endpoint 0 FIFO buffer contains valid data. 23.5.13 USB Endpoint Stall Register (USBEPSTL) The bits in USBEPSTL are used to forcibly stall the endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 (EP0 STL) is cleared automatically on reception of 8-bit command data for which decoding is performed by the function. When the SETUPTS flag in USB interrupt flag register 0 is set, a write of 1 to the EP0 STL bit is ignored. For details see section 23.8, Stall Operations. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 EP3 STL 0 R/W 2 EP2 STL 0 R/W 1 EP1 STL 0 R/W 0 EP0 STL 0 R/W Bits 7 to 4--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Dec 12, 2005 page 700 of 1034 REJ09B0254-0500 Section 23 USB Function Controller Bit 3--EP3 Stall (EP3 STL): When this bit is set to 1, endpoint 3 is placed in the stall state. Bit 2--EP2 Stall (EP2 STL): When this bit is set to 1, endpoint 2 is placed in the stall state. Bit 1--EP1 Stall (EP1 STL): When this bit is set to 1, endpoint 1 is placed in the stall state. Bit 0--EP0 Stall (EP0 STL): When this bit is set to 1, endpoint 0 is placed in the stall state. 23.5.14 USB Interrupt Enable Register 0 (USBIER0) USBIER0 enables the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0). When an interrupt flag is set while the corresponding bit in USBIER0 is set to 1, an interrupt request is sent to the CPU. The contents of the interrupt event register (INTEVT2) are determined by the contents of USB interrupt select register 0 (USBISR0). Bit: 7 BRST Initial value: R/W: 0 R/W 6 EP1 FULL 0 R/W 5 EP2 TR 0 R/W 4 EP2 EMPTY 0 R/W 3 SETUP TS 0 R/W 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W 23.5.15 USB Interrupt Enable Register 1 (USBIER1) USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1). When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt request is sent to the CPU. The contents of the interrupt event register (INTEVT2) are determined by the contents of USB interrupt select register 1 (USBISR1). Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 EP3 TR 0 R/W 1 EP3 TS 0 R/W 0 VBUSF 0 R/W 23.5.16 USBEP1 Receive Data Size Register (USBEPSZ1) USBEPSZ1 is the endpoint 1 receive data size register, indicating the amount of data received from the host. The endpoint 1 FIFO buffer has a dual-FIFO configuration; the receive data size indicated by this register refers to the currently selected FIFO. Rev. 5.00 Dec 12, 2005 page 701 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.5.17 USB Interrupt Select Register 0 (USBISR0) USBISR0 selects the interrupt event register (INTEVT2) codes of the interrupt requests indicated in USB interrupt flag register 0. If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR0 is cleared to 0, the interrupt will be USBFI0 (USB function interrupt 0), with an interrupt event register (INTEVT2) code of H'A20. If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR0 is set to 1, the interrupt will be USBFI1 (USB function interrupt 1), with an interrupt event register (INTEVT2) code of H'A40. The initial value designates an interrupt event register (INTEVT2) code of H'A20. If interrupts occur simultaneously, USBFI0 has priority by default. For details on the interrupt event register (INTEVT2), refer to section 4, Exception Handling, and section 7, Interrupt Controller (INTC). Bit: 7 BSRT Initial value: R/W: 0 R/W 6 EP1 FULL 0 R/W 5 EP2 TR 0 R/W 4 EP2 EMPTY 0 R/W 3 SETUP TS 0 R/W 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W 23.5.18 USB Interrupt Select Register 1 (USBISR1) USBISR1 selects the interrupt event register (INTEVT2) codes of the interrupt requests indicated in USB interrupt flag register 1. If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR1 is cleared to 0, the interrupt will be USBFI0 (USB function interrupt 0), with an interrupt event register (INTEVT2) code of H'A20. If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR1 is set to 1, the interrupt will be USBFI1 (USB function interrupt 1), with an interrupt event register (INTEVT2) code of H'A40. The initial value designates an interrupt event register (INTEVT2) code of H'A20. If interrupts occur simultaneously, USBFI0 has priority by default. For details on the interrupt event register (INTEVT2), refer to section 4, Exception Handling, and section 7, Interrupt Controller (INTC). Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 EP3 TR 1 R/W 1 EP3 TS 1 R/W 0 VBUS 1 R/W Rev. 5.00 Dec 12, 2005 page 702 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.5.19 USBDMA Setting Register (USBDMAR) DMA transfer can be carried out between the endpoint 1 and endpoint 2 data registers by means of the on-chip DMA controller. Dual address transfer is performed, using byte transfer units. In order to start DMA transfer, DMA control settings must be made in addition to the settings in this register. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 PULLUP_ E 0 R 1 EP2 DMAE 0 R/W 0 EP1 DMAE 0 R/W Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0. Bit 2--Pull-up Enable (PULLUP_E): This bit is for controlling connection notification (D + pull-up) to the USB host/hub. This bit enables the level of the USB1_pwr_en pin to be controlled. Writing 1 outputs the High level and 0 outputs the Low level. For more information on the D + pull-up control, see section 22, USB Pin Multiplex Controller. Bit 1--Endpoint 2 DMA Transfer Enable (EP2 DMAE): When this bit is set, DMA transfer is enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of space in the FIFO buffer, the transfer request signal to the DMA controller is asserted. When 64 bytes are written to the FIFO buffer in DMA transfer, EP2 packet enabling is set automatically, and 64byte data can be transferred. If there is a space in another FIFO, a transfer request is asserted for the DMA controller again. However, since EP2 packet enable is not set automatically if data packet size for transfer is less than 64 bytes, set EP2 packet enabling by the CPU with a DMA transfer end interrupt. Since EP2-related interrupt requests to the CPU are not masked automatically, interrupt requests must also be masked as necessary in the interrupt enable register. Bit 0--Endpoint 1 DMA Transfer Enable (EP1 DMAE): When this bit is set, DMA transfer can be performed from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of space in the FIFO buffer, the transfer request signal to the DMA controller is asserted. When all received data is read in DMA transfer, the EP1 read-end trigger is performed automatically. EP1-related interrupt requests to the CPU are not masked automatically. Rev. 5.00 Dec 12, 2005 page 703 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.6 23.6.1 Operation Cable Connection USB function Cable disconnection VBUS pin = 0 V UDC core reset in progress Application Connect USB cable USBF_VBUS pin = 1 (USBIFR1/VBUSMN = 1) USBIFR1/VBUSF = 1 USB bus connection interrupt Interrupt request Clear VBUS flag (USBIFR1/VBUSF) Clear UDC core reset Prepare firmware since USB communication starts Bus reset USBIFR0/BRST = 1 Bus reset interrupt Interrupt request Clear bus reset flag (USBIFR0/BRST) Wait receive-end interrupt of set-up command Clear FIFOs (EP0, EP1, EP2, EP3) Wait receive-end interrupt of set-up command Figure 23.2 Cable Connection Operation The above flowchart shows the operation in cable connection. When a USB connection interrupt occurs, connection can be detected by confirming the status of the USBF_VBUS pin. Processing by a USB bus connection interrupt is unnecessary for applications in which USB cable connection is not required to be detected. Prepare processing by a bus reset interrupt. Rev. 5.00 Dec 12, 2005 page 704 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.6.2 Cable Disconnection USB function Cable connection state VBUS pin = 1 Application Disconnect USB cable USBF_VBUS pin = 0 (USBIFR/VBUSMN = 0) USBIFR1/VBUSF = 1 USB bus connection interrupt Interrupt request Clear VBUSF flag (USBIFR/VBUSF) Reset UDC core End Figure 23.3 Cable Disconnection Operation The above flowchart shows the operation in cable disconnection. When a USB bus connection interrupt occurs, disconnection can be detected by confirming the status of the USBF_VBUS pin. Rev. 5.00 Dec 12, 2005 page 705 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.6.3 Control Transfer Control transfer consists of three stages of setup, data (that may not be included), and status (figure 23.4). The data stage consists of multiple bus transactions. The operating flowchart of each stage is shown below. Setup stage Control-in SETUP(0) DATA0 Data stage IN(1) DATA1 Status stage ... IN(0/1) DATA0/1 IN(0) DATA0 OUT(1) DATA1 Control-out SETUP(0) DATA0 OUT(1) DATA1 OUT(0) DATA0 ... OUT(0/1) DATA0/1 IN(1) DATA1 No data SETUP(0) DATA0 IN(1) DATA1 Figure 23.4 Transfer Stage for Control Transfer Rev. 5.00 Dec 12, 2005 page 706 of 1034 REJ09B0254-0500 Section 23 USB Function Controller (1) Setup Stage USB function Application SETUP token reception Receive 8-byte command data in EP0s Command to be processed by application? Yes Set receive-end flag of setup command (USBIFR0/SETUP TS = 1) No Automatic processing by this module Interrupt request Clear SETUP TS flag (USBIFR0/SETUP TS = 0) Clear EP0i FIFO (USBFCLR/EP0iCLR = 1) Clear EP0o FIFO (USBFCLR/EP0oCLR = 1) To data stage Read 8-byte data from EP0s Decode command data Decide data stage direction*1 Write 1 to EP0s read-end bit (USBTRG/EP0s RDFN = 1) *2 To control-in data stage To control-out data stage Notes: 1. The application analyzes command data from the host that must be processed by the application in the setup stage, and decides the following processing methods (for instance, data stage direction). 2. When the transfer direction is control-out, enable an EP0i transfer request interrupt that is required in the status stage. When the transfer direction is control-in, disable the interrupt since it is not used. Figure 23.5 Setup Stage Operation Rev. 5.00 Dec 12, 2005 page 707 of 1034 REJ09B0254-0500 Section 23 USB Function Controller (2) Data Stage (Control-In) USB function Application IN token reception From setup stage 1 written to USBTRG/EP0s RDFN? Yes No NACK Write data to USBEP0i data register (USBEPDR0i) Valid data in EP0i FIFO? Yes Data transmission to host ACK No NACK Write 1 to EP0i packet enable bit (USBTRG/EP0i PKTE = 1) Set EP0i transfer-end flag to 1 (USBIFR0/EP0i TS = 1) Interrupt request Clear EP0i transfer-end flag (USBIFR0/EP0i TS = 0) Write data to USBEP0i data register (USBEPDR0i) Write 1 to EP0i packet enable bit (USBTRG/EP0i PKTE = 1) Figure 23.6 Data Stage Operation (Control-In) Rev. 5.00 Dec 12, 2005 page 708 of 1034 REJ09B0254-0500 Section 23 USB Function Controller The application analyzes command data from the host in the setup stage and decides the following data stage direction. As a result of command data analysis, when the data stage is in-transfer, onepacket data to be sent to the host is written to FIFO. If there is more data to be sent to the host, after data written first is sent to the host (USBIFR0/EP0i TS = 1), data is written to FIFO. The end of the data stage is decided by transferring out-token by the host and entering the status stage. Note: When the size of data transferred from the function is smaller than the size of data requested from the host, the function indicates data stage end by returning a packet smaller than the maximum packet to the host. When the size of data transferred from the function is integer times larger than the maximum packet size, a 0-length packet is transferred and the data stage end is indicated. Rev. 5.00 Dec 12, 2005 page 709 of 1034 REJ09B0254-0500 Section 23 USB Function Controller (3) Data Stage (Control-Out) USB function Application OUT token reception 1 written to USBTRG/EP0s RDFN? Yes No NACK Data reception from host ACK Set EP0o receive-end flag to 1 (USBIFR0/EP0o TS = 1) Interrupt request Clear EP0o receive-end flag (USBIFR0/EP0o TS = 0) OUT token reception Read data from USBEP0o data size register (USBEPSZ0o) 1 written to USBTRG/EP0o RDFN? Yes No NACK Read data from USBEP0o data register (USBEPDR0o) Write 1 to EP0o read-end bit (USBTRG/EP0o RDFN = 1) Figure 23.7 Data Stage Operation (Control-Out) The application analyzes command data from the host in the setup stage and decides the following data stage direction. As a result of command data analysis, when the data stage is out-transfer, data from the host is waited. After data reception (USBIFR0/EP0o TS = 1), data is read from FIFO. Applications then write 1 to the EP0o read-end bit, make reception FIFO empty, and wait for the next data reception. The end of the data stage is decided by transferring in-token by the host and entering the status stage. Rev. 5.00 Dec 12, 2005 page 710 of 1034 REJ09B0254-0500 Section 23 USB Function Controller (4) Status Stage (Control-In) USB function Application OUT token reception 0-byte reception from host ACK Set EP0o reception complete flag (IFR0.EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0.EP0o TS = 0) End of control transfer Write 1 to EP0o read complete bit (TRG.EP0o RDFN = 1) End of control transfer Figure 23.8 Status Stage Operation (Control-In) The status stage in control-in starts with out-token from the host. The application receives 0-byte data from the host and completes control transfer. Rev. 5.00 Dec 12, 2005 page 711 of 1034 REJ09B0254-0500 Section 23 USB Function Controller (5) Status Stage (Control-Out) USB function Application IN token reception Valid data in EP0i FIFO? Yes No NACK Interrupt request Clear EP0i transfer-request flag (USBIFR0/EP0i TR = 0) 0-byte transmission to host ACK Write 1 to EP0i packet enable bit (USBTRG/EP0i PKTE = 1) Set EP0i transfer-end flag (USBIFR0/EP0i TS = 1) Interrupt request Clear EP0i transfer-end flag (USBIFR0/EP0i TS = 0) End of control transfer End of control transfer Figure 23.9 Status Stage Operation (Control-Out) The status stage in control-out starts with in-token from the host. In in-token reception at the start of status stage, an EP0o transfer-request interrupt occurs since no data is in EP0i FIFO. The application acknowledges that the status stage has started by the interrupt. To transfer 0-byte data to the host, no data is written to the EP0i FIFO, and 1 is written to the EP0i packet-enable bit. Therefore, 0-byte data is transferred to the host in the next in-token, and control transfer is completed. However, after the application completes all processing related to the data stage, write 1 to the EP0i packet-enable bit. Rev. 5.00 Dec 12, 2005 page 712 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.6.4 EP1 Bulk-Out Transfer (Dual FIFOs) USB function Application OUT token reception Space in EP1 FIFO? Yes Data reception from host ACK USBIFR0/EP1 FULL status bit automatically set to 1 No NACK Interrupt request Read USBEP1 receive-data size register (USBEPSZ1) Read data from USBEP1 data register (USBEPDR1) Write 1 to EP1 read-end bit (USBTRG/EP1 RDFN = 1) Both FIFOs are empty? Yes USBIFR0/EP1 FULL status bit automatically cleared to 0 No Interrupt request Figure 23.10 EP1 Bulk-Out Transfer Operation EP1 has two 64-byte FIFOs, but the user can perform data reception and receive-data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the USBIFR0/EP1 FULL bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, Rev. 5.00 Dec 12, 2005 page 713 of 1034 REJ09B0254-0500 Section 23 USB Function Controller and so the next packet can be received immediately. When both FIFOs are full, NACK is returned to the host automatically. When reading of the receive data is completed following data reception, 1 is written to the USBTRG/EP1 RDFN bit. This operation empties the FIFO that has just been read, and makes it ready to receive the next packet. 23.6.5 EP2 Bulk-In Transfer (Dual FIFOs) USB function Application IN token reception Valid data in EP2 FIFO? Yes No NACK USBIFR0/EP2 TR interrupt Write 1 to USBIER0/EP2 EMPTY enable bit Data transmission to host ACK Space in EP2 FIFO? No Yes USBIFR0/EP2 EMPTY status bit automatically set 1 Interrupt request USBIFR0/EP2 EMPTY interrupt USBIFR0/EP2 EMPTY status bit automatically cleared to 0 Write one-packet data to USBEP2 data register Write 1 to EP2 packet enable bit (USBTRG/EP2 PKTE = 1) Figure 23.11 EP2 Bulk-In Transfer Operation Rev. 5.00 Dec 12, 2005 page 714 of 1034 REJ09B0254-0500 Section 23 USB Function Controller EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit-data writes without being aware of this dual-FIFO configuration. Write data to one FIFO at one time. For instance, even if two FIFOs are empty, EP2/PKTE cannot be performed after writing 128-byte data continuously. Perform EP2/PKTE in every 64-byte write. To perform bulk-in transfer, since there is no valid data in FIFO in the first in-token, a USBIFR0/EP2 TR interrupt is requested. By the interrupt, write 1 to the USBIER0/EP2 EMPTY bit and enable the EP2 FIFO EMPTY interrupt. Since the two EP2 FIFOs are empty first, the EP2 FIFO EMPTY interrupt is generated immediately. The data to be transmitted is written to the data register using this interrupt. After the first transmit data write, the other FIFO is empty, and so the next transmit data can be written immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one FIFO is empty, USBIFR0/EP2 EMPTY is set to 1. When ACK is returned from the host after data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission is continued. When transmission of all data has been completed, write 0 to USBIFR0/EP2 EMPTY and disable interrupt requests. Rev. 5.00 Dec 12, 2005 page 715 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.6.6 EP3 Interrupt-In Transfer USB function Application IN token reception Valid data in EP3 FIFO? Yes No NACK Clear EP3 transfer-request flag (USBIFR1/EP3 TR = 0) Data transmission to host ACK Write data to USBEP3 data register Write to EP3 packet enable bit (USBTRG/EP3 PKTE = 1) Set EP3 transfer-end flag (USBIFR1/EP3 TS = 1) Clear EP3 transfer-end flag (USBIFR1/EP3 TS = 0) IN token reception Write data to USBEP3 data register Write to EP3 packet enable bit (USBTRG/EP3 PKTE = 1) Note: This flow is an example of interrupt transfer processing. When there is data to be transferred, the following flow can also be considered. "Confirm that FIFO is empty by referring to the EP3 DE bit of the USB data status register and write data to FIFO." Figure 23.12 EP2 Interrupt-In Transfer Operation Rev. 5.00 Dec 12, 2005 page 716 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.7 Processing of USB Standard Commands and Class/Vendor Commands Processing of Commands Transmitted by Control Transfer 23.7.1 A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 23.3 below. Table 23.3 Command Decoding on Application Side Decoding not Necessary on Application Side Clear feature Get configuration Get interface Get status Set address Set configuration Set feature Set interface Decoding Necessary on Application Side Get descriptor Sync frame Set descriptor Class/Vendor command If decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. No processing is necessary by the user. An interrupt is not generated in this case. If decoding is necessary on the application side, the USB function module stores the command in the EP0s FIFO. After normal reception is completed, the USBIER0/SETUP TS flag is set and an interrupt request is generated. In the interrupt routine, 8 bytes of data must be read from the EP0s data register (USBEPDR0S) and decoded by firmware. The necessary data stage and status stage processing should then be carried out according to the result of the decoding operation. Rev. 5.00 Dec 12, 2005 page 717 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.8 23.8.1 Stall Operations Overview This section describes stall operations in the USB function module. There are two cases in which the USB function module stall function is used: * When the application forcibly stalls an endpoint for some reason * When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application; they must be cleared with a Clear Feature command from the host. 23.8.2 Forcible Stall by Application The application uses the USBEPSTL register to issue a stall request for the USB function module. When the application wishes to stall a specific endpoint, it sets the corresponding bit in USBEPSTL (1-1 in figure 23.13). The internal status bits are not changed. When a transaction is sent from the host for the endpoint for which the USBEPSTL bit was set, the USB function module references the internal status bit, and if this is not set, references the corresponding bit in USBEPSTL (1-2 in figure 23.13). If the corresponding bit in USBEPSTL is set, the USB function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 23.13). If the corresponding bit in USBEPSTL is not set, the internal status bit is not changed and the transaction is accepted. Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the USBEPSTL register. Even after a bit is cleared by the Clear Feature command (3-1 in figure 23.13), the USB function module continues to return a stall handshake while the bit in USBEPSTL is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 23.13). To clear a stall, therefore, it is necessary for the corresponding bit in USBEPSTL to be cleared by the application, and also for the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 23.13). Rev. 5.00 Dec 12, 2005 page 718 of 1034 REJ09B0254-0500 Section 23 USB Function Controller (1) Transition from normal operation to stall (1-1) USB Internal status bit 0 USBEPSTL 01 1. 1 written to USBEPSTL by application (1-2) Reference Transaction request Internal status bit 0 USBEPSTL 1 1. IN/OUT token received from host 2. USBEPSTL referenced 1. 1 set in USBEPSTL 2. Internal status bit set to 1 3. Transmission of STALL handshake (1-3) Stall STALL handshake Internal status bit 01 To (2-1) or (3-1) (2) When Clear Feature is sent after USBEPSTL is cleared (2-1) Transaction request Internal status bit 1 USBEPSTL 10 USBEPSTL 1 1. USBEPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. USBEPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake (2-2) STALL handshake Internal status bit 1 USBEPSTL 0 (2-3) Clear Feature command Internal status bit 10 USBEPSTL 0 1. Internal status bit cleared to 0 Normal status restored (3) When Clear Feature is sent before USBEPSTL is cleared to 0 (3-1) Clear Feature command Internal status bit 10 To (1-2) USBEPSTL 1 1. Internal status bit cleared to 0 2. USBEPSTL not changed Figure 23.13 Forcible Stall by Application Rev. 5.00 Dec 12, 2005 page 719 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.8.3 Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to the USBEPSTL register, and returns a stall handshake (1-1 in figure 23.14). Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the USBEPSTL register. After a bit is cleared by the Clear Feature command, USBEPSTL is referenced (3-1 in figure 23.14). The USB function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 23.14). To clear a stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure 23.14). If set by the application, USBEPSTL should also be cleared (2-1 in figure 23.14). Rev. 5.00 Dec 12, 2005 page 720 of 1034 REJ09B0254-0500 Section 23 USB Function Controller (1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 01 USBEPSTL 0 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically To (2-1) or (3-1) (2) When Clear Feature is sent after USBEPSTL is cleared (2-1) Transaction request Internal status bit 1 USBEPSTL 0 1. USBEPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. USBEPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake (2-2) STALL handshake Internal status bit 1 USBEPSTL 0 Stall status maintained (3) When Clear Feature is sent before USBEPSTL is cleared to 0 (3-1) Clear Feature command Internal status bit 10 USBEPSTL 0 1. Internal status bit cleared to 0 2. USBEPSTL not changed Normal status restored Figure 23.14 Automatic Stall by USB Function Module Rev. 5.00 Dec 12, 2005 page 721 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.9 23.9.1 Usage Notes Receiving Setup Data Note the following for EPDR0s that receives 8-byte setup data: 1. As a latest setup command must be received in high priority, the write from the USB bus takes priority over the read from the CPU. If the next setup command reception is started while the CPU is reading data after the data is received, the read from the CPU is forcibly terminated. Therefore, the data read after reception is started becomes invalid. 2. EPDR0s must always be read in 8-byte units. If the read is terminated at a midpoint, the data received at the next setup cannot be read correctly. 23.9.2 Clearing the FIFO If a USB cable is disconnected during data transfer, the data being received or transmitted may remain in the FIFO. When disconnecting a USB cable, clear the FIFO. While a FIFO is transferring data, it must not be cleared. 23.9.3 Overreading and Overwriting the Data Registers Note the following when reading or writing to a data register of this module. (1) Receive data registers The receive data registers must not be read exceeding the valid amount of receive data, that is, the number of bytes indicated by the receive data size register. Even for EPDR1 which has double FIFO buffers, the maximum data to be read at one time is 64 bytes. After the data is read from the current valid FIFO buffer, be sure to write 1 to EP1RDFN in TRG, which switches the valid buffer, updates the receive data size to the new number of bytes, and enables the next data to be received. (2) Transmit data registers The transmit data registers must not be written to exceeding the maximum packet size. Even for EPDR2 which has double FIFO buffers, write data within the maximum packet size at one time. After the data is written, write 1 to PKTE in TRG to switch the valid buffer and enable the next data to be written. Data must not be continuously written to the two FIFO buffers. Rev. 5.00 Dec 12, 2005 page 722 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.9.4 Assigning Interrupt Sources to EP0 The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations. 23.9.5 Clearing the FIFO when DMA Transfer Is Enabled The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is enabled (EP1 DMAE in USBDMA = 1). Cancel DMA transfer before clearing the register. 23.9.6 Notes on TR Interrupt Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i, EP2, or EP3. The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent from the USB host. However, at the timing shown in figure 23.15, multiple TR interrupts occur successively. Take appropriate measures against malfunction in such a case. Note: This module determines whether to return NAK if the FIFO of the target EP has no data when receiving the IN token, but the TR interrupt flag is set only after a NAK handshake is sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is set again. TR interrupt routine CPU Clear Writes TRG. TR flag transmit data PKTE TR interrupt routine Host IN token IN token IN token Determines whether to return NAK USB NAK Sets TR flag Determines whether to return NAK NAK Transmits data ACK Sets TR flag (Sets the flag again) Figure 23.15 TR Interrupt Flag Set Timing Rev. 5.00 Dec 12, 2005 page 723 of 1034 REJ09B0254-0500 Section 23 USB Function Controller 23.9.7 Peripheral Clock (P) Operation Frequency The peripheral clock frequency (P) should be 13 MHz or above when using this module. Rev. 5.00 Dec 12, 2005 page 724 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Section 24 USB HOST Module 24.1 General Description The USB Host Controller module incorporated in SH7727 supports Open Host Controller (Open HCI) Specification for the Universal Serial Bus (USB) as well as the Universal Serial Bus specification ver.1.1. The Open HCI Specification for the USB is a register-level description of Host Controller for the USB which in turn is described by the USB specification. It is necessary to refer Open HCI specification to develop drivers for this USB Host Controller and hardware. 24.1.1 Features * Support open HCI standard ver.1.0 register set * Support Universal Serial Bus standard ver.1.1 * Root Hub function * Support Full speed (12Mbps) mode and Low speed (1.5Mbps) mode * Support Overcurrent detection * Support 127 endpoints control in maximum * The whole area of the synchronous DRAM in area 3 connected to the CPU can be used for transfer data and descriptor. Rev. 5.00 Dec 12, 2005 page 725 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.1.2 Pin Configuration Pin configuration of the USB host controller is shown in table 24.1. For the detailed method for setting each pin, see section 22, USB Pin Multiplex Controller. Table 24.1 Pin Configuration Pin name Power enable pin 1 Power enable pin 2 Over-current pin 1/ VBUS pin Over-current pin 2 1P pin 1M pin 2P pin 2M pin Symbol USB1_pwr_en USB2_pwr_en USB1_ovr_current/ USBF_VBUS USB2_ovr_current USB1P USB1M USB2P USB2M I/O Output Output Input Input I/O I/O I/O I/O Function USB port 1 power enable control USB port 2 power enable control USB port 1 over-current detect/ USB cable connection monitor pin USB port 2 over-current detect D+ port 1 transceiver pin D- port 1 transceiver pin D+ port 2 transceiver pin D- port 2 transceiver pin Rev. 5.00 Dec 12, 2005 page 726 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.1.3 Register Configuration Table 24.2 Register Configuration Register Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentE HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDonrHeadED HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 Symbol -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Initial Value H'00000010 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00002EDF H'00000000 H'00000000 H'00000000 H'00000628 H'02001202 H'00000000 H'00000000 H'00000100 H'00000100 Address H'04000400 H'04000404 H'04000408 H'0400040C H'04000410 H'04000414 H'04000418 H'0400041C H'04000420 H'04000424 H'04000428 H'0400042C H'04000430 H'04000434 H'04000438 H'0400043C H'04000440 H'04000444 H'04000448 H'0400044C H'04000450 H'04000454 H'04000458 Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Rev. 5.00 Dec 12, 2005 page 727 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2 24.2.1 Register Description HcRevision HcRevision Register (H'04000400) Register: HcRevision Bits 31-8 7-0 Reset 0h 10h R/W -- R Offset: 00-03 Description Reserved. Revision (Rev) These read only bits include the BCD expression of the HCI specification version implemented for the host controller. The value H'10 corresponds to version 1.0. All HCI implementation complying to this specification have the value of H'10. Rev. 5.00 Dec 12, 2005 page 728 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.2 HcControl HcControl Register (H'04000404) The HcControl register defines the operation mode for the host controller. Most of bits of this register are amended only by the host controller driver other than HostController Function State and Remote Wakeup Command. Register: HcControl Bits 31-11 10 Reset 0h 0b R/W -- R/W Offset: 04-07 Description Reserved. Read/Write 0's RemoteWakeupEnable (RWE) This bit is used by HCD to enable/disable the remote wakeup function at the same time as the detection of an upstream resume signal. This function is not supported. Be sure to write 0. 9 0b R/W RemoteWakeupConnected (RWC) This bit indicates whether the host controller supports a remote wakeup signal or not. When the remote wakeup is supported and used in the system, the host controller must set this bit between POST in the system firmware. The host controller clears the bit at the same time of the hardware reset, however, does not change at the same time as the software reset. The remote wakeup signal to the system of the host is specific for the host bus, so it is not described in this specification. 0: Remote wakeup signal is not supported. (initial value) 1: Remote wakeup signal is supported. 8 0b R/W InterruptRouting (IR) This bit determines the routing of interrupts generated by the event registered in HcInterruptStatus. HCD clears this bit at the same time as the hardware reset, however, does not clear at the same time as the software reset. HCD uses this bit as a tag to indicate the ownership of the host controller. 0: All interrupts are routed to normal bus interrupt mechanism. (initial value) 1: Interrupts are routed to SMI. Rev. 5.00 Dec 12, 2005 page 729 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcControl Bits 7, 6 Reset 00b R/W R/W Offset: 04-07 Description HostControllerFunctionalState (HCFS) HCD determines whether the host controller has started to route SOF after having read the StartofFrame bit of HcInterruptStatus. This bit can be changed by the host controller only in the UsbSuspend state. The host controller can move from the UsbSuspend state to the UsbResume state after having detected the resume signal from the downstream port. In the host controller, UsbSuspend is entered after the software reset so that UsbReset is entered after the hardware reset. The former resets the route hub. 00: USB reset 01: USB resume 10: USB operation 11: USB suspend 5 0b R/W BulkListEnable (BLE) This bit is set to enable the processing of the bulk list in the next frame. The host controller checks this bit when the processing of the list has been determined. When disabling, HCD can correct the list. When HcBulkCurrentED indicates ED to be deleted, HCD should hasten the pointer by updating HcBulkCurrentED before re-enabling the list processing. 0: Bulk list processing is not carried out. (initial value) 1: Bulk list processing is carried out. 4 0b R/W ControlListEnable (CLE) This bit is set to enable the processing of the control list in the next frame. If cleared by HCD, the processing of the control list is not carried out after next SLF. The host controller must check this bit whenever the list will be processed. When disabling, HCD can correct the list. When HcControlCurrentED indicates ED to be deleted, HCD should hasten the pointer by updating HcBulk before re-enabling the list processing. 0: Control list processing is not carried out. (initial value) 1: Control list processing is carried out. Rev. 5.00 Dec 12, 2005 page 730 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcControl Bits 3 Reset 0b R/W R/W Offset: 04-07 Description IsochronousEnable (IE) This bit is used by HCD to enable/disable the processing of isochronous ED. While processing the periodic list, HC will check the status of this bit when it finds an isochronous ED (F =1). If set (enabled), the host controller continues to process ED. If cleared (disabled), the host controller stops the processing of the periodic list (currently includes only isochronous ED) and starts to process the bulk/control list. Setting this bit is guaranteed to be valid in the next frame (not in the current frame). 0: Processes ED. (initial value) 1: Processes the bulk/control list. 2 0b R/W PeriodicListEnable (PLE) This bit is set to enable the processing of the periodic list. If cleared by HCD, no periodic list processing is carried out after next SOF. HC must check this bit before HC starts to process the list. 0: The periodic list processing is not carried out after next SOF. (initial value) 1: The periodic list processing is carried out after next SOF. 1, 0 00b R/W ControlBulkServiceRatio (CBSR) This bit specifies the service ration of the control and bulk ED. The host controller must compare the ratio specified by the internal calculation whether it has processed several nonvacant control ED in determining whether another control ED is continued to be supplied or switched to bulk ED before any a periodic list is processed. In case of reset, HCD is responsible for restoring this value. 00: 1:1 (initial value) 01: 2:1 10: 3:1 11: 4:1 Rev. 5.00 Dec 12, 2005 page 731 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.3 HcCommandStatus HcCommandStatus Register (H'04000408) The HcCommandStatus register is used by the host controller not only for reflecting the current status of the host controller, but also for receiving a command issued by the host controller driver. A write is for setting the host controller driver. The host controller must guarantee that the bit to which 1 is written to is set and the bit to which 0 is written to is unchanged. The host controller driver must distribute multiple clear commands to the host controller by a previously issued command. The host controller driver can read all bits normally. The SchedulingOverrunCount bit indicates the number of the frame that has detected the Scheduling Overrun error by the host controller. This occurs when the periodic list has not completed before EOF. When the Scheduling Overrun error is detected, the host controller increments the counter and sets SchedulingOverrun in the HcInterruptStatus register. Register: HcCommandStatus Bits 31-18 17-16 Reset 0h 00b R/W -- R Offset: 08-0B Description Reserved. SchedulingOverrunCount (SOC) These bits are incremented in each SchedulingOverrun error. These bits are initially set to B'00 and returned to B'11. These bits are incremented when SchedulingOverrun is detected even though the SchedulingOverrun bit in HcInterruptStatus is set. These bits are used by HCD to monitor any continuous scheduling problem. 15-4 3 0h 0b -- R/W Reserved. OwnershipChangeRequest (OCR) This bit is set by OS HCD to request the change of the control of the host controller. When this bit is set, the host controller sets the OwnershipChange bit in the HcInterruptStatus register. After a change, this bit is cleared and remains until the next request from OS HCD. 0: After a change, this bit is cleared and remains until the next request from OS HCD. (initial value) 1: Set the OwnershipChange bit in the HcInterruptStatus register. Rev. 5.00 Dec 12, 2005 page 732 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcCommandStatus Bits 2 Reset 0b R/W R/W Offset: 08-0B Description BulkListFilled (BLF) This bit is used to indicate that there are some TDs in the list. This bit is set by HCD to the list when TD is added to ED. When the host controller starts to process the head of the list, it checks BF. As long as BulkListFilled is 0, the host controller does not start to process the list. When BulklistFilled is 1, the host controller starts to process the list to set BF to 0. When the host controller finds TD in the list, the host controller sets BulkListFilled to 1. When TD is never found in the list and HCD does not set BulkListFilled, the host controller completes the processing of the list. BulklistFilled is still 0 when the size list processing is stopped. 0: The list is not processed (initial value) 1: The list is processed. 1 0b R/W ControlListFilled (CLF) This bit is used to indicate that there are some TDs in the control list. This bit is set by HCD when TD is added to ED in the control list. When the host controller starts to process the head of the control list, it checks CLK. As long as ControlListFilled is 0, the host controller does not start to process the control list. If CF is 1, the host controller starts to process the control list and ControlListFilled is set to 0. When the host controller finds TD in the list, the host controller sets ControlListFilled to 1. When TD is never found in the control list and HCD does not set ControlListFilled, the host controller completes the processing of the control list. ControllListFilled is still 0 when the control list processing is stopped. 0: The list is not processed. (initial value) 1: The list is processed. Rev. 5.00 Dec 12, 2005 page 733 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcCommandStatus Bits 0 Reset 0b R/W R/W Offset: 08-0B Description HostControllerReset (HCR) This bit is set by HCD to initiate the software reset of the host controller. The system is moved to the UsbSuspend state in which most of the operational registers are reset except for the next state regardless of the functional state of the host controller. For example, an access to the InterrupRouting field in HcControl and without host bus are allowed. This bit is cleared by the host controller upon completion of the reset operation. This bit does not cause any reset to the route hub and the next reset signal is not issued to the downstream port. 0: Cleared by the host controller at the completion of the reset control 1: UsbSuspend state Rev. 5.00 Dec 12, 2005 page 734 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.4 HcInterruptStatus HcInterruptStatus Register (H'0400040C) This register indicates the status in various events that cause hardware interrupts. When an event occurs, the host controller sets the corresponding bit in this register. When the bit is set to 1, a hardware interrupt is generated while an interrupt is enabled and the MsterInterrupEnable bit is set in the HcInterruptEnable register (see section 24.2.5, HcInterruptEnable). The host control driver clears a specified bit in this register by writing 1 in the bit position to be cleared. The host controller driver cannot set any bit of these bits. The host controller never clears bits. Register: HcInterruptStatus Bits 31 30 Reset 0h 0b R/W -- R/W Offset: 0C-0F Description Reserved. OwnershipChange (OC) This bit is set by the host controller when the OwnershipChangeRequest bit in the HcCommandStatus reigster is set. This event generates a system management interrupt at once when not masked. When there is no SMI pin, this bit is set to 0. 0: The OCR bit in the HcCommandStatus register is not set. (initial value) 1: The OCR bit in the HcCommandStatus register is set. 29-7 6 0h 0b -- R/W Reserved. RootHubStatusChange (RHSC) This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus 1, 2 register [Number of Downstream Port] has changed. 0: The content of the HcRhStatus register or HcRhPortStatus register is not changed. (initial value) 1: The content of the HcRhStatus register or HcRhPortStatus register is changed. 5 0b R/W FrameNumberOverflow (FNO) This bit is set when MSB (bit 15) in the HcFumnumber register changes value from 0 to 1 or from 1 to 0 or the HccaFrameNumber bit is updated. 0: MSB or the HccaFrameNumber bit in the HcFmNumber register is not updated. (initial value) 1: MSB or the HccaFrameNumber bit in the HcFmNumber register is updated. Rev. 5.00 Dec 12, 2005 page 735 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcInterruptStatus Bits 4 Reset 0b R/W R/W Offset: 0C-0F Description UnrecoverableError (UE) This bit is set when the host controller detects a system error that is not related to USB. HCD clears this bit after the host controler is reset. 0: System error has not generated yet. (initial value) 1: System error is detected. 3 0b R/W ResumeDetected (RD) This bit is set when the host controller detects that a device of USB issues a resume signal. This bit is not set when HCD sets UsbResume state. 0: The resume signal is not detected. (initial value) 1: The resume signal is detected. 2 0b R/W StartofFrame (SF) This bit is set by the host controller when each frame starts and after the HccaFrameNumber is updated. The host controller simultaneously generates the SOF token. 0: Each frame has not initiated or HccaFrame Number is not updated (initial value) 1: Initiation of each frame and updating of HccaFrameNumber 1 0b R/W WritebackDoneHead (WDH) This bit is set immediately after the host controller has written HcDoneHead to HccaDoneHead. HccaDoneHead is not updated until this bit is cleared. HCD should clear this bit only after the content of HccaDoneHead has been stored. 0: When cleared after set to 1. (initial value) 1: When HcDoneHead is written to HccaDonehead. 0 0b R/W SchedulingOverrun (SO) This bit is set when the USB schedule has overrun after HccaFrameNumber has updated. SchedulingOverrun also increments the SchedulingOverrunCount bit in HcCommandStatus. 0: The USB schedule has not overrun. (initial value) 1: The USB schedule has overrun. Rev. 5.00 Dec 12, 2005 page 736 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.5 HcInterruptEnable HcInterrutpEnable Register (H'04000410) Each enable bit in the HcInterruptEnable register corresponds to the related interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control an event to generate a hardware interrupt. A hardware interrupt is requested in the host bus when a bit in the HcInterruptEnable register is set, a corresponding bit in the HcInteruptEnable register is set, and the MasterInterrupEnable bit is set. As a result, the USBHI bit in Interrupt Request Register 3 (IRR3) of Interrupt Controller INTC is set (the USBHI bit is used in common regardless of the content of the interrupt generation event). Therefore, the USBHI bit can be used when an interrupt generation is detected by HCD. Writing 1 in this register sets the corresponding bit, while writing 0 leaves the bit. When read, the current value of this register is returned. Rev. 5.00 Dec 12, 2005 page 737 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcInterruptEnable Bits 31 Reset 0b R/W R/W Offset: 10-13 Description MasterInterruptEnable (MIE) Setting of this bit to 0 is ignored by the host controller. When this bit is set to 1, an interrupt generation by the event specified in another bit in this register is enabled. This is used by HDC that the master interrupt is enabled. When an interrupt is detected by HCD, use the USBIH bit of Interrupt Controller INTC. 0: Ignore (initial value) 1: Enable interrupt generation due to the specified event. 30 0b R/W OwnershipChangeEnable (OC) 0: Ignore (initial value) 1: Enable interrupt generation due to Ownership Change. 29-7 6 0h 0b -- R/W Reserved. RootHubStatusChangeEnable (RHSC) 0: Ignore (initial value) 1: Enable interrupt generation due to Root Hub Status Change. 5 0b R/W FrameNumberOverflowEnable (FNO) 0: Ignore (initial value) 1: Enable interrupt generation due to Frame Number Overflow. 4 0b R/W UnrecoverableErrorEnable(UE) 0: Ignore (initial value) 1: Enable interrupt generation due to unrecoverable error. 3 0b R/W ResumeDetectedEnable (RD) 0: Ignore (initial value) 1: Enable interrupt generation due to Resume Detected. 2 0b R/W StartOfFrameEnable (SF) 0: Ignore (initial value) 1: Enable interrupt generation due to Start of Frame. 1 0b R/W WritebackDoneHeadEnable (WDH) 0: Ignore (initial value) 1: Enable interrupt generation due to Writeback Done Head. 0 0b R/W SchedulingOverrunEnable (SO) 0: Ignore (initial value) 1: Enable interrupt generation due to Scheduling Overrun. Rev. 5.00 Dec 12, 2005 page 738 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.6 HcInterruptDisable HcInterruptDisable Register (H'04000414) Each disable bit in the HcInterruptDisable register corresponds to the related interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is related to the HcInterruptEnable register. Therefore, writing a 1 to a bit in this register clears the corresponding bit in HcInterruptEnable register, while writing a 0 to a bit leaves the corresponding bit in the HcInterruptEnable register. When read, the current value of the HcInterruptEnable register is returned. Register: HcInterruptDisable Bits 31 Reset 0b R/W R/W Offset: 14-17 Description MasterInterruptEnable (MIE) 0: Ignore 1: Disable interrupt generation due to the specified event. 30 0b R/W OwnershipChangeEnable (OC) 0: Ignore 1: Disable interrupt generation due to Ownership Change. 29-7 6 0h 0b -- R/W Reserved. Read/Write 0's RootHubStatusChangeEnable (RHSC) 0: Ignore 1: Disable interrupt generation due to Root Hub Status Change. 5 0b R/W FrameNumberOverflowEnable (FNO) 0: Ignore 1: Disable interrupt generation due to Frame Number Overflow. 4 0b R/W UnrecoverableErrorEnable (UE) 0: Ignore 1: Disable interrupt generation due to unrecoverable error. 3 0b R/W ResumeDetectedEnable (RD) 0: Ignore 1: Disable interrupt generation due to Resume Detected. 2 0b R/W StartofFrameEnable (SF) 0: Ignore 1: Disable interrupt generation due to Start of Frame. 1 0b R/W WritebackDoneHeadEnable (WDH) 0: Ignore 1: Disable interrupt generation due to Writeback Done Head. Rev. 5.00 Dec 12, 2005 page 739 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcInterruptDisable Bits 0 Reset 0b R/W R/W Offset: 14-17 Description SchedulingOverrunEnable (SO) 0: Ignore 1: Disable interrupt generation due to Scheduling Overrun. 24.2.7 HcHCCA HCCA Register (H'04000418) The HcHCCA register includes physical addresses of the host controller communication area. The host controller driver determines the alignment limitation by writing 1 to all bits in the HcHCCA register and by reading the content of the HcHCCA register. Alignment is evaluated by checking the number of 0 in the lower bits. The minimum alignment is 256 bytes. Consequently, bits 0 to 7 must be always returned to 0 when they are read. This area is used to retain the control structure and interrupt table that are accessed by the host controller and host controller driver. Register: HcHCCA Bits 31-8 7-0 Reset 0h 0h R/W R/W -- Offset: 18-1B Description HCCA Reserved. 24.2.8 HcPeriodCurrentED HcPeriodCurrentED Register(H'0400041C) The HcPeriodCurrentED register includes a physical address of current Isochronous ED or Interrupt ED. Register: HcPeriodCurrentED Bits 31-4 3-0 Reset 0h 0h R/W R/W -- Offset: 1C-1F Description PeriodCurrentED (PCED) Pointer to the current Periodic List ED. (Within memory area3) Reserved. Rev. 5.00 Dec 12, 2005 page 740 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.9 HcControlHeadED HcControlHeadED (H'04000420) The HcControlHeadED register includes a physical address of first ED. Register: HcControlHeadED Bits 31-4 Reset 0h R/W R/W Offset: 20-23 Description ControlHeadED (CHED) Pointer to the Control List Head ED. (Within SRAM memory space) 3-0 0h -- Reserved. 24.2.10 HcControlCurrentED HcControlCurrentED Regsiter (H'04000424) The HcControlCurrentED register includes a physical address of current ED. Register: HcControlCurrentED Bits 31-4 3-0 Reset 0h 0h R/W R/W -- Offset: 24-27 Description ControlCurrentED (CCED) Pointer to the current Control List ED. (Within memory area3) Reserved. 24.2.11 HcBulkHeadED HcBulkHeadED Register (H'04000428) The HcBulkHeadEDregister includes a physical address of first ED in Bulk List. Register: HcBulkHeadED Bits 31-4 3-0 Reset 0h 0h R/W R/W -- Offset: 28-2B Description BulkHeadED (BHED) Pointer to the Bulk List Head ED. (Within memory area3) Reserved. Rev. 5.00 Dec 12, 2005 page 741 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.12 HcBulkCurrentED HcBulkCurrentED Register(H'0400042C) The HcBulkCurrentED register includes a physical address of current ED in the Bulk List. When the bulk list is supplied by the round robin method, endpoints are ordered to the list according to these insertions. Register: HcBulkCurrentED Bits 31-4 3-0 Reset 0h 0h R/W R/W -- Offset: 2C-2F Description BulkCurrentED (BCED) Pointer to the current Bulk List ED. (Within memory area3) Reserved. 24.2.13 HcDoneHead HcDoneHead Register (H'04000430) The HcDoneHead register includes a physical address of finally completed TD added to Done queue. The host controller needs not read this register so that the content is written to HCCA periodically in normal operation. Register: HcDoneHead Bits 31-4 Reset 0h R/W R/W Offset: 30-33 Description DoneHead (DH) Pointer to the current Done List Head ED. (Within memory area 3) 3-0 0h -- Reserved. Rev. 5.00 Dec 12, 2005 page 742 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.14 HcFmInterval HcFmInterval Register(H'04000434) The HcFmInterval register includes a 14-bit value indicating the bit time interval of the frame (i.e., between two serial SOFs) and a 15-bit value indicating the maximum packet size at a full speed that is transmitted and received by the host controller without causing scheduling overrun. The host controller driver adjusts the frame interval minutely by writing a new value over the current value in each SOF. This supplies required programming ability to the host controller to synchronize with an external clock source and to synchronize with offset of an unknown local clock. Register: HcFmInterval Bits 31 Reset 0b R/W R/W Offset: 34-37 Description FrameIntervalToggle (FIT) This bit is toggled by HCD whenever it loads a new value into FrameInterval. 30-16 0h R/W FSLargestDataPacket (FSMPS) This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value expresses the largest data amount of the bit that can be transmitted and received in one transaction by the host controller at any given time without causing scheduling overrun. The field value is calculated by HCD. 15-14 13-0 0h 2EDFh -- R/W Reserved. FrameInterval (FI) These bits specifies the interval between two serial SOFs with bit times. The nominal value is set to 11999. HCD must store the current value of this field before resetting the host controller. With this procedure, this bit is reset to its nominal value by the host controller by setting the HostControllerReset bit in the HcCommandStatus register. HCD can select to restore the stored value at the completion of the reset sequence. Rev. 5.00 Dec 12, 2005 page 743 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.15 HcFmRemaining HcFrameRemaining Register (H'04000438) The HcFmRemaining register is a 14-bit down counter indicating the bit time remaining in the current frame. Register: HcFrameRemaining Bits 31 Reset 0b R/W R Offset: 38-3B Description FrameRemainingToggle (FRT) This bit is always loaded from the FrameIntervalToggle bit in HcFminterval when FrameReamining reaches 0. This bit is used by HCD for the synchronization between FrameInterval and FrameReamining. 30-14 13-0 0h 0b -- R Reserved. FrameRemaining (FR) This counter is decremented at each bit time. When this counter reaches 0, this counter is reset by loading the value of the FramInterval bit specified in the HcFminterval register at the next bit time boundary. When the host controller transits to the UsbOperational state, it read the FrameInterval bit in the HcFminterval register again and use the updated value from the next SOF. Rev. 5.00 Dec 12, 2005 page 744 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.16 HcFmNumber HcFmNumberb Register (H'040004BC) The HcFmNumber register is a 16-bit counter. It indicates the reference of timing between events occurring in the host controller and host controller driver. The host controller driver uses a 16-bit value specified in this register and generates a 32-bit frame number without necessity for a frequent access to the register. Register: HcFmNumber Bits 31-16 15-0 Reset 0h 0b R/W -- R Offset: 3C-3F Description Reserved. FrameNumber (FN) These bits are incremented when HcFmRemaining is reloaded. The count will return to H'0 after H'FFFF. When the host controller transits to the UsbOperational state, these bits are automatically incremented. After the host controller increments the FramNumber bit and sends SOF in each frame boundary, the content is written to HCCA before the host controller reads first ED in the frame. After writing to HCCA, the host controller sets the StartofFrame bit in the HcInterruptStatus register. Rev. 5.00 Dec 12, 2005 page 745 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.17 HcPeriodicStart HcPeriodicStart Register(H'04000440) The HcPeriodicStart register has a 14-bit programmable value, which determines the earliest time when the host controller should start to process the periodic list. Register: HcPeriodicStart Bits 31-14 13-0 Reset 0h 0b R/W -- R/W Offset: 40-43 Description Reserved. PeriodicStart (PS) This field is cleared after the hardware has reset. Then this field is set by HCD while the host controller performs initial settings. The value is roughly calculated as the value of the HcFmInterval register minus 10%. When the HcFm Remaining register reaches the specified value, the processing of the periodic list has a higher priority than the control/bulk processing. Consequently, the host controller starts to process the interrupt list after the completion of the current control/bulk transaction. 24.2.18 HcLSThreshold HcLSThreshold Register (H'04000444) The HcLSIThreshold register includes an 11-bit value that is used by the host controller to determine whether or not to authorize the transfer of the LS packed 8 bytes in maximum before EOF. The host controller and host controller driver cannot change this value. Register: HcLSThreshold Bits 31-12 11-0 Reset 0h 628h R/W -- R/W Offset: 44-47 Description Reserved. LSThreshold (LST) This field contains a value to be compared with the FrameRemaining bit prior to the beginning of low-speed transaction. The transaction is started only when the Frame Remaining bit value is beyond the value of the list. The value is calculated by HCD considering the transmission and set-up overhead. Rev. 5.00 Dec 12, 2005 page 746 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.19 HcRhDescriptorA HcRhDescriptorA Register (H'04000448) The HcRhDescriptorA register is the first register of two registers describing the features of the root hub. The reset value is implementation specific. The descriptor length (11), descriptor type (TBD), the hub controller current bit (0) of Class Descriptor of the hub are emulated by HCD. All other bits are placed in the HcRhDescriptorA register and HcRhDescriptorB register. Register: HcRhDescriptorA Bits 31-24 Reset 02h R/W R/W Offset: 48-4B Description PowerOnToPowerGoodTime (POTPGT) These bits specify the time required for waiting before accessing the power-on port of the root hub. These bits are implementation specific. The unit of time is 2 ms. The time is calculated as POTPGT x 2 ms. 23-13 12 0h 1 -- R/W Reserved. NoOverCurrentProtection (NOCP) This bit selects how the over-current status of the root hub is reported. When this bit is cleared, the OverCureentProtectionMode bit specifies global report or report at each port. 0: Over-current status is collectively reported for all downstream ports. 1: Over-current protection is not supported. (initial value) 11 0 R/W OverCurrentProtectionMode (OCPM) This bit selects how the over-current status in the root-hub port is reported. At reset, this bit reflects the same mode of PowerSwitchingMode. When the NoOverCureentProtection bit is cleared, this bit is valid. 0: Over-current status is collectively reported for all downstream ports. (initial value) 1: Over-current protection is not supported. 10 0 R DeviceType (DT) USB Host Controller is not a compound device. Always set to 0. Rev. 5.00 Dec 12, 2005 page 747 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcRhDescriptorA Bits 9 Reset 1 R/W R/W Offset: 48-4B Description NoPowerSwitching (NPS) This bit selects whether the power switching is supported or ports are always power-supplied. This bit is implementation specific. When this bit is cleared, Power-SwitchingMode specifies the global/port switching. 0: Ports can be power-switched. 1: Ports are always powered on when the host controller is powered on. (initial value) Note: Because the initial value is 1, first clear this bit (write 0 with the HCD) to enable power switching of the port. 8 0 R/W PowerSwitchingMode (PSM) This bit specifies how the power switching of the root-hub port is controlled. This bit is implementation specific. This bit is valid only when the NoPowerSwitching bit is cleared. 0: All ports are simultaneously power-supplied. (initial value) 1: Each port is power-supplied individually. In this mode, the port power is controlled with either of global/port switching. When the PortPowerControlMask bit is set, the port is reacted only to the port-power command (set/clear port power). When the port mask is cleared, the port is controlled only by the global power-switch (set/clear global power). 7-0 02h R NumberDownstreamPorts (NDP) These bits specify the number of downstream ports supported by the root hub. These bits are implementation specific. In the SH7727 their value is H'2. Rev. 5.00 Dec 12, 2005 page 748 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.20 HcRhDescriptorB HcRhDescriptorB Register (H'0400044C) The HcRhDescriptorB register is the second register of two registers describing the features of the root hub. These bits are written during the initial setting so as to correspond to the system implementation. The reset value is implementation specific. Register: HcRhDescriptorB Bits 31-16 Reset 0h R/W R/W Offset: 4C-4F Description PortPowerControlMask (PPCM) This bit indicates that the port is influenced by the global powercontrol command when the PowerSwitchingMode bit is set. When this bit is set, the power state of the port is affected by the power control at each port (set/clear port power). When this bit is cleared, the port is controlled by the global power switch (set/clear global power). If the device is placed in the global switching mode (PowerSwitchingMode = 0), this bit is not valid. Bit 15: Assured Bit 16: Port#1 power mask Bit 17: Port#2 power mask ... Bit 31: Port#15 power mask Note: Clear the No Power Switching of the RhDescriptorA register so that the power to all ports is OFF (Port Power Status = 0), then set this bit. 15-0 0h R/W DeviceRemoveable (DR) These bits are dedicated to the ports of the root hub. When these bits are cleared, the set device becomes removable. When these bits are set, do not remove the set device. Bit 0: Assured Bit 1: Device affixed to Port#1 Bit 2: Device affixed to Port#2 ... Bit 15: Device affixed to Port#15 Rev. 5.00 Dec 12, 2005 page 749 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.2.21 HcRhStatus HcRhStatus Register (H'04000450) The HcRhStatus register is divided into two parts. The lower word of a long word indicates the hub status bits and the upper word indicates the hub status change bit. Reserved bits should be set to 0. Register: HcRhStatus Bits 31 Reset 0 R/W W Offset: 50-53 Description ClearRemoteWakeupEnable (CRWE) Writing a 1 to this bit clears DeviceRemoteWakeupEnable. Writing a 0 has no effect. 30-18 17 0h 0 -- R/W Reserved. Read/Write 0's OverCurrentIndicatorChange (OCIC) This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing a 0 has no effect. 16 0 R/W (read) LocalPowerStatusChange (LPSC) The root hub does not support the local power status function. Therefore, this bit is always read 0. (write) SetGlobalPower This bit is written to 1 to power on (clears the PortPowerStatus bit) all ports in global power mode (PowerSwitchingMode = 0). This bit sets the PortPowerStatus bit only to the port in which the PortPowerControlMask bit is not set in power mode at each port. When 0 is written to, this bit is not cleared. 15 0 R/W (read) DeviceRemoteWakeupEnable (DRWE) This bit enables the ConnectStatusChange bit as a resume event and generates the state transition from UsbSuspend to UsbResume and ResumeDetected interrupt. 0: ConnectStatusChange is not the remote wakeup event (initial value) 1: ConnectStatusChange is the remote wakeup event. (write) SetRemoteWakeupEnable Writing a 1 sets DeviceRemoteWakeupEnable. Writing a 0 has no effect. 14-2 0h -- Reserved. Rev. 5.00 Dec 12, 2005 page 750 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcRhStatus Bits 1 Reset 0 R/W R Offset: 50-53 Description OverCurrentIndicator (OCI) This bit reports the over-current condition. When this bit is set, an over-current condition exists. When this bit is cleared, all power operations are normal. This bit is always 0 when the over-current protection at each port is carried out. 0: All power operations are normal. (initial value) 1: An over-current condition exists. 0 0 R/W (read) LocalPowerStatus (LPS) The root hub does not support the local power status function. Therefore, the bit is always read 0. (write) ClearGlobalPower This bit is written to 1 to power on (leaves the PortPowerStatus bit) all ports in global power mode (Power Switching Mode = 0). This bit clears the PortPowerStatus bit only to the port in which the PortPowerControlMask bit is not set. Writing a "0" has no effect. In the power mode at each port, the PortpowerStatus bit is cleared to the port in which the PortPowerControlmask bit is not set. Writing 0, has no effect. 24.2.22 HcRhPortStatus[1:2] HcRhPortStatus Register ([1]:04000454 [2]:04000458) This register is reset by the USBRESET state. HcRhPortStatus 1, 2 registers are used for base-controlling each port and to report the port event. The lower word is used to reflect the port status while the upper word reflects the status change. Some status bits have special writing (see below). If an attempt to write to a bit indicating a change in port status occurs when a transaction in which a token is passed via a handshake is in progress, the writing to the bit is delayed until the transaction is completed. Always write reserved bits to 0. Rev. 5.00 Dec 12, 2005 page 751 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcRhPortStatus[1:2] Bits 31-21 20 Reset 0h 0 R/W -- R/W Offset: 54-57, 58-5B Description Reserved. PortResetStatusChange (PRSC) This bit is set when the 10 ms port reset signal has completed. Writing a 1 clears this bit writing a 0 has no effect. 0 = Port reset is not complete. 1 = Port reset is complete. 19 0 R/W PortOverCurrentIndicatorChange (OCIC) This bit is valid when an over-current condition is reported on the base of each port. This bit is set when the root hub changes the PortOverCurrentIndicator bit. Writing a 1 clears this bit. Writing a 0 has no effect. 0: PortOverCurrentIndicator has not changed. (initial value) 1: PortoverCurrentIndicator has changed. 18 0 R/W PortSuspendStatusChange (PSSC) This bit is set when all resume sequences have completed. These sequences include 20 ms resume pulse, LS EOP, and 3 ms resychronization delay. Writing a 1 clears this bit. Writing a 0 has no effect. This bit is cleared also when ResetStatusChange is set. 0: Port resume has not completed. (initial value) 1: Port resume has completed. 17 0 R/W PortEnableStatusChange (PESC) This bit is set when the PortEnableStatus bit is cleared due to a hardware event . This bit is not set by the change of writing of HCD. Writing a 1 clears this bit. Writing a 0 has no effect. 0: PortEnableStatus has not changed (initial value) 1: PortEnableStatus has changed Rev. 5.00 Dec 12, 2005 page 752 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcRhPortStatus[1:2] Bits 16 Reset 0 R/W R/W Offset: 54-57, 58-5B Description ConnectStatusChange (CSC) This bit is set whenever the connection or disconnection event occurs. Writing a 1 clears this bit. Writing a 0 has no effect. If CurrentConnectStatus is cleared when SetPortReset, SetPortEnable, or SetPortSuspend is written to, writing when the power supply of the port is disconnected does not occur, so this bit is set to enforce the driver to re-evaluate the connection status. 0: CurrentConnectionStatus has not changed (initial value) 1: CurrentConnectionStatus has changed Note: If the Device Removable bit is set, this bit is set only after the root hub reset to inform that the system that a device can be attached. 15-10 9 0h 0 -- R/W Reserved. (read) LowSpeedDeviceAttached (LSDA) This bit indicates the speed of the device attached to this port. When this bit is set, a low-seed device is attached to this port. When this bit is cleared, a full-speed device is attached to this port. This bit is valid only when the CurrentConnectStatus bit is set. 0: A full-speed device is set. (initial value) 1: A low-speed device is set. (write) ClearPortPower Writing a 1 clears PortPowerStatus. Writing a 0 has no effect Rev. 5.00 Dec 12, 2005 page 753 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcRhPortStatus[1:2] Bits 8 Reset 1 R/W R/W Offset: 54-57, 58-5B Description (read) PortPowerStatus (PPS) This bit reflects the power state of the port regardless of the power switching mode to be executed. However, because the initial value of the No Power Switching bit of the HcRhDescriptorA register is 1, this bit is first fixed to 1. No Power Switching bit must first be cleared before the power is switched, as shown below. When an over-current condition is detected, this bit is cleared. Writing SetPortPower or SetGlovalPower sets this bit. Writing ClearPortPower or ClearGlobalPower clears this bit. PowerSwitchingMode and PortPowerControlMask determine which power control switch can be used. Only Set/ClearGlobalPower controls this bit in global switching mode (PowerSwitchingMode= 0). If the PortPowerControlMask bit of that port is set in power switching mode (PowerSwitchingMode = 1). Only the Set/ClearGlobalPower command is enabled if the mask is not set. When the port power is disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and portResetStatus are reset. 0 = Port power is off. 1 = Port power is on. (initial value) Note: If NoPowerSwitching is set, this bit is always read as 1. (write) SetPortPower Writing a 1 sets PortPowerStatus. Writing a 0 has no effect. 7-5 4 0h 0 -- R/W Reserved. (read) PortResetStatus (PRS) When this bit is set by writing to SetPortReset, the port reset signal is output. This bit is cleared when PortResetStatusChange is set upon completion of a reset. When CurrentConnectStatus is cleared, this bit is not set. 0 = Port reset signal is not active. (initial value) 1 = Port reset signal is active. (write) SetPortReset Writing a 1 sets PortReset signal. Writing a 0 has no effect. When CurrentConnectStatus is cleared, this write does not set PortResetStatus, instead, sets ConnectStatusChange. This reports a reset of the power disconnection port to the driver. Rev. 5.00 Dec 12, 2005 page 754 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcRhPortStatus[1:2] Bits 3 Reset 0 R/W R/W Offset: 54-57, 58-5B Description (read) PortOverCurrentIndicator (POCI) This bit is valid only when a root hub is placed in such a way that an over-current condition is reported on the base of each port. If the over-current report at each port is not supported, this bit is set to 0. If this bit is cleared, all power controls are normal in this port. If this bit is set, an over-current status exists in this port. This bit always reflects an over-current input signal. 0 = No over-current condition (initial value) 1 = Over-current condition is detected (write) ClearSuspendStatus Writing a 1 initiates a resume. Writing a 0 has no effect. If PortSuspendStatus is set, a resume is initiated. 2 0 R/W (read) PortSuspendStatus (PSS) This bit indicates that the port is suspended or during the resume sequence. Writing SetSuspendState sets this bit and setting PortSuspendStatusChange clears this bit at the end of the resume interval. If CurrentConnectStatus is cleared, this bit cannot be set. When portResetStatusChange is set upon completion of the port reset or HC is placed in the UsbResume state, this bit is cleared. If an upstream resume is in progress, it is transmitted to the host controller. 0 = Port is not suspended 1 = Port is selectively suspended (write) SetPortSuspend Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect. In addition, when CurrentConnectStatus is cleared, PortSuspendStatus is not set by this writing. Instead, ConnectStatusChange is set. This reports the suspended state of the power disconnection to the driver. Rev. 5.00 Dec 12, 2005 page 755 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Register: HcRhPortStatus[1:2] Bits 1 Reset 0 R/W R/W Offset: 54-57, 58-5B Description (read) PortEnableStatus (PES) This bit indicates whether the port is enabled or disabled. The root hub clears this bit when the over-current condition and a operational bus error such as disconnect event, power-off switch, or babble is detected. PortEnabledStatusChange is set by this change. This bit is set by writing SetPortEnable and cleared by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus is cleared. In addition, this bit is set upon completion of the port reset by which ResetStatusChange is set, or uponcompletion of the port suspend by which SuspendStatusChange is set. 0 = Port disabled. (initial value) 1 = Port enabled. (write) SetPortEnable Writing a 1 sets PortEnableStatus. Writing a 0 has no effect. If CurrentConnectStatus is cleared, this writing does not set PortEnableStatus, instead, sets ConnectStatusChange. This reports the driver that the power disconnection port has been tried to be enabled. 0 0 R/W (read) CurrentConnectStatus (CCS) This bit indicates the status of the downstream port. 0 = No device connected. 1 = Device connected. Note: If DeviceRemoveable is set (not removable) this bit is always 1. (write) ClearPortEnable Writing a 1 clears PortEnableStatus. Writing a 0 has no effect. CurrentConnectStatus is not affected by any writing. Rev. 5.00 Dec 12, 2005 page 756 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.3 24.3.1 Data Storage Format which Required by USB Host Controller Storage Format of the Transferred Data USB Host Controller expects that data are compiled from lower address to upper address regardless endian setting of the CPU. Below figure shows data read operation which is done by USB Host Controller. Program DATA.L DATA.L DATA.L H'11223344 H'55667788 H'00000099 Memory (Area 3) +3 +2 11 22 +7 +6 55 66 +11 +10 00 00 +1 33 +5 77 +9 00 +0 44 +4 88 8 99 USB host LW read H'11223344 LW read H'55667788 LW read H'00000099 The correspondence between data in memory and data read by USB Host Controller must be equal. When USB Host Controller reads data from external memory, USB Host Controller reads data by long word read operation every time regardless that the read data are written in byte ,word or long word. USB Host Controller uses data in byte from lower address in long word which it reads regardless the endian mode. Even endian mode is set as big or little, set the data from down addresses. Below program flow is the example of failure. 1st In program , set transfer address A to register R0 at big endian 2nd In program , "MOV.B #H'12,@R0" 3rd In program , set transfer start address A to USB Host Controller , and set 1byte as transfer size. Memory +3 12 +2 00 +1 00 +0 00 Data expected to be transferred LW read H'12000000 Actually transferred data This example show that above operation transfers expected data #H'12. Rev. 5.00 Dec 12, 2005 page 757 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Data is filled from the lower bits of the memory in writing so that the data is read/written in bidirection consistently regardless of the endian type. That is, the data is always aligned with the little endian specification. 24.3.2 Storage Format of the Descriptor ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of USB Host Controller must be aligned so that each Dword corresponds to the long-word boundary (addresses 4n to 4n + 3) of the memory. 24.4 24.4.1 Data Alignment Restriction of USB Host Controller Restriction on the Line Boundary of the Synchronous DRAM The transferred data is stored in shared system memory with CPU. The data alignment in system memory are restricted depends on synchronous DRAM specification which is used as system memory. DRAM Row address Memory area n (1) Row address n+1 (2) Row address n+2 (3) In above figure , transfer data 1 and 3 are able to be read or written by USB Host Controller. But transfer data 2 are possibly unable to be read or written by USB Host controller. Any data which have possibility to be accessed by USB Host Controller must be aligned in synchronous DRAM not to cross row address alignment. Rev. 5.00 Dec 12, 2005 page 758 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.4.2 Restriction on the Memory Access Address MPS in ED, CBP in General TD, and BP0 and OFFSET0 to 7 in Ischoronous TD must be set in multiples of 4 (4n). In the OpenHCI standard, 1 packet is transferred by ITD in General TD and 1 packet by 1 offset in Ischronous TD. In addition, when the amount of the data specified by TD during OUT transfer exceeds MAXPACKETSIZE (MPS), a packet transmission is carried out in MAXPACKETSIZE. Therefore, the setting value can be made as above. This restriction is due to the difference between the specifications of the HCI interface which is the standard of the IP bus interface of USB and of the bus interface of SH7727. Data might be correctly written to if data is transferred from addresses other than 4n address. For example, when a two-byte transfer is carried out from the address that terminates at 1, a long-word transfer is carried out and an unexpected data is written to starting address 0. 24.5 24.5.1 Restrictions on the Data Transfer of USB Controller Restriction of the Data Size in IN Transfer When a data packet shorter than MAXPACKETSIZE (short packet) is transferred in the IN data transfer other than the isochronous transfer, following usages are restricted. 1. Usage when a dribble bit is added When HUB are connected in multiple steps, a dribble bit may be added at the end of the packet. 2. When receiving the data with final 6 bits in CRC are all 1 (in this case, bit stuffing occurs) In this case, this USB controller may write IN data in the memory with one byte additionally. Therefore, usage of 1 is prohibited. In usage of 2, the software must be written to so that no problem occurs even additional data of 1 byte is written to. In concrete, in the usage to connect the received short packets are connected in the memory, 1 byte of unnecessary data might be inserted. Be sure to transfer MAXPACKETSIZE mainly and the processed data will be used so that the end of the data or head can be recognized when a short packet is sent. 24.5.2 Restrictions on the Hub Connection on NAK/STALL Reception When NAK or STALL is received as a handshake from the USB function module, the following usage is restricted. 1. Usage where a dribble bit is added When HUBs are connected in multiple steps, a dribble bit may be added at the end of the packet. In this case, this USB controller might not correctly recognize the NAK/STALL handshake. Be sure not to connect HUB to decrease steps so that no dribble bit occurs. Rev. 5.00 Dec 12, 2005 page 759 of 1034 REJ09B0254-0500 Section 24 USB HOST Module 24.5.3 Restrictions when a Low-Speed Device is Disconnected When a low-speed device connected to the root port is disconnected while the data is transmitted to the host, this USB controller might hung. Therefore, be sure not to disconnect the low-speed device while the data is transmitted. If that disconnection is detected, reset USB (write 00 to the HCFS bit in the HcControl register). 24.6 Restrictions on the Software Reset and USB Reset The operation of the controller might become stuck if a software reset (1 written to the HCR bit in the HcCommandStatus register) or USB reset (00 written to the HCFS bit in the HcControl register) is performed while the USB host controller is carrying out a master memory write. Master memory write operations are performed at the start of frame (SOF) and during data transfer. To prevent the host controller from becoming stuck, use one of the following methods: 1. Write the program so that the SDF timing is derived from the HcFmRemaining value and a software reset or USB reset is applied around the middle of a frame in which all list processing is disabled. 2. If you issue a reset for the USBH module after applying a software reset or USB reset, no stack will occur. (Set the module software reset register (SRSTR).) 24.7 Notes on Using USB Host with Versions Previous to the SH7727C The USB host controller of the SH7727 and SH7727B may erroneously recognize an SE0 state during data transfer. As a result, the controller incorrectly detects a device not connected state (erroneous device not connected detection) even though the device actually is connected. The following methods may be used to work around this problem. 1. Use the low speed (1.5 Mbps) mode. Erroneous device not connected detection does not occur during low speed data transfer. 2. When using the full speed (12 Mbps) mode, use method (a) or (b) below to avoid erroneous device not connected detection. a. Ensure that the D+, D- crossover voltage output by the USB function device exceeds SH7727 AVcc_USB x 0.55 (V). b. Ensure that received data strings do not contain more than 28 consecutive 0 bits. Note: The prohibition on consecutive 0 bits applies to all bits of SYNC + PID + DATA + CRC16 + EOP. EOP is counted as 2 bits. Rev. 5.00 Dec 12, 2005 page 760 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Explanation of Terms * SE0: USB data transfer uses a D+/D- differential signal. Consequently, D+/D- is normally a reciprocal signal. However, in some special cases D+ and D- are both defined as low. This state is referred to as SE0. * Device not connected detection: Detection of a USB device not connected state when SE0 continues beyond the device not connected detection duration. Rev. 5.00 Dec 12, 2005 page 761 of 1034 REJ09B0254-0500 Section 24 USB HOST Module Rev. 5.00 Dec 12, 2005 page 762 of 1034 REJ09B0254-0500 Section 25 LCD Controller Section 25 LCD Controller 25.1 Overview A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data for display is stored in system memory. The LCDC module reads data from system memory, uses the pallet memory to determine the colors, then puts the display on the LCD panel. It is possible to connect the LCDC to the LCD module of most types other than microcomputer bus interface types and NTSC/PAL types and those that apply the LVDS interface. Note: * An LVDS-conversion LSI can be connected to the LCDC to allow connection to an LVDS interface. 25.1.1 Features The LCDC has the following features. * Panel interface Serial interface method Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width) * Supports 4/8/15/16-bpp (bit per pixel) color modes * Supports 1/2/4/6-bpp grayscale modes * Supports LCD-panel sizes from 16 x 1 to 1024 x 1024 * 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5) * STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker. * Dedicated display memory is unnecessary because the controller uses synchronous DRAM which is connected to area 3 of the CPU's memory map * The display is stable because of the large 2.4-kbyte line buffer * Supports the inversion of the output signal to suit the LCD panel's signal polarity * Supports variation of the burst length in reading from the synchronous DRAM, to realize highspeeds in the reading of data * Supports the selection of data formats (the endian setting for bytes, backed pixel method) by register settings * A hardware-rotation mode is included to support the use of landscape-format LCD panels as portrait-format LCD panels (the horizontal width of the panel before rotation must be within 320 pixels--see table 25.3). Rev. 5.00 Dec 12, 2005 page 763 of 1034 REJ09B0254-0500 Section 25 LCD Controller Note: When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower-order bit lines should be connected to GND or to the lowest bit from which data is output. 25.1.2 Block Diagram Figure 25.1 shows a block diagram of LCDC. 512 bytes LCLK Bus clock (B) Peripheral clock (P) Clock generator clk CL1 CL2 FLM LCD 15-0 DON VCPWC VEPWC M/DISP Pallet ram Bus interface Peripheral bus Register LCDC Power control Li bus interface Line buffer 2.4 kbytes Li bus Figure 25.1 Block Diagram Rev. 5.00 Dec 12, 2005 page 764 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.1.3 Pin Configuration Table 25.1 summarizes the LCDC's pin configuration. Table 25.1 Pin Configuration Name LCD 15-0 DON CL1 CL2 M/DISP FLM VCPWC VEPWC LCLK I/O O O O O O O O O I Function Data for LCD panel Display-on signal (DON) Shift-clock 1 (STN/DSTN)/Horizontal sync signal (HSYNC) (TFT) Shift-clock 2 (STN/DSTN)/dot clock (DOTCLOCK) (TFT) LCD current-alternation signal/(STN/DSTN), Display enable BLANK (TFT)/DISP signal First line marker/Vertical sync signal (VSYNC) (TFT) LCD-module power control (Vcc) LCD-module power control (VEE) LCD clock-source input Note: Check the LCD module specifications carefully in section 25.4, Clock and LCD Data Signal Examples, before deciding on the wiring specifications for the LCD module. 25.1.4 Register Configuration Table 25.2 summarizes the configuration of the LCDC's registers. Table 25.2 Register Configuration Register Name LCDC input clock register LCDC module type register LCDC data format register LCDC scan mode register LCDC data fetch start address register for upper portion of display panel LCDC data fetch start address register for lower portion of display panel Abbreviation LDICKR LDMTR LDDFR LDSMR LDSARU LDSARL Initial Value H'0101 H'0109 H'000C H'0000 H'0C000000 H'0C000000 Address H'04000C00 (H'A4000C00)* H'04000C02 (H'A4000C02)* H'04000C04 (H'A4000C04)* H'04000C06 (H'A4000C06)* H'04000C08 (H'A4000C08)* H'04000C0C (H'A4000C0C)* Access Size 16 16 16 16 32 32 Rev. 5.00 Dec 12, 2005 page 765 of 1034 REJ09B0254-0500 Section 25 LCD Controller Register Name LCDC fetch data line address offset register for display panel LCDC palette control register LCDC palette data registers 00 to FF Abbreviation LDLAOR LDPALCR LDPR00-FF Initial Value H'0280 H'0000 Undefined Address H'04000C10 (H'A4000C10)* H'04000C12 (H'A4000C12)* H'04000800 to H'04000BFC (H'A4000800 to H'A4000BFC)* H'04000C14 (H'A4000C14)* H'04000C16 (H'A000C16)* H'04000C18 (H'A4000C18)* H'04000C1A (H'A4000C1A)* H'04000C1C (H'A4000C1C)* H'04000C1E (H'A4000C1E)* H'04000C20 (H'A4000C20)* H'04000C24 (H'A4000C24)* H'04000C26 (H'A4000C26)* H'04000C28 (H'A4000C28)* Access Size 16 16 32 LCDC horizontal character number register LCDC horizontal synchronization signal register LCDC vertical displayed line number register LCDC vertical total line number register LCDC vertical synchronization signal register LCDC ac modulation signal toggle line number register LCDC interrupt control register LCDC power management mode register LCDC power supply sequence period register LCDC control register LDHCNR LDHSYNR LDVDLNR LDVTLNR LDVSYNR LDACLNR LDINTR LDPMMR LDPSPR LDCNTR H'4F52 H'0050 H'01DF H'01DF H'01DF H'000C H'0000 H'0010 H'F60F H'0000 16 16 16 16 16 16 16 16 16 16 Note: * When the LCDC is not a target for address conversion by the MMU, use the addresses in parentheses. Rev. 5.00 Dec 12, 2005 page 766 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2 25.2.1 Register Descriptions LCDC Input Clock Register (LDICKR) This LCDC can select the bus clock (B), the peripheral clock (P), or the external clock as its operation clock source. The selected clock source can be divided using an internal divider into a clock of 1/1 to 1/16 and be used as the LCDC operating clock (DOTCLOCK). The clock output from the LCDC is used to generate the synchronous clock output (CL2) for the LCD panel from the operating clock selected in this register. The average frequency of CL2 can be calculated using the formula below. The actual frequency, however, will differ depending on the type of LCD panel and the bus width of the data output to the LCD panel. See section 25.4, Clock and LCD Data Signal Examples, for details. TFT panel CL2 = DOTCLOCK STN or DSTN panel Monochrome: CL2 = (DOTCLOCK/data bus width of output to LCD panel) Color: CL2 = 3 x (DOTCLOCK/data bus width of output to LCD panel) Set this register so that the clock input to the LCDC is 50 MHz or less regardless of CL2. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 1 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 3 2 1 0 ICKSEL ICKSEL 1 0 0 R/W 0 R/W DCDR4 DCDR3 DCDR2 DCDR1 DCDR0 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W Bits 15, 14, and 11 to 5--Reserved Bits 13 and 12--Input Clock Select (ICKSEL1 and ICKSEL0): Set the clock source for DOTCLOCK. Bit 13 ICKSEL1 0 1 Bit 12 ICKSEL0 0 1 0 1 Description Bus clock (B) is selected Peripheral clock (P) is selected External clock (LCLK) is selected Reserved (setting prohibited) (Initial value) Rev. 5.00 Dec 12, 2005 page 767 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bits 4 to 0--Denominator of Clock Division Ratio (DCDR4 to DCDR0): Set denominator of the input clock division ratio. I/O Clock Frequency (MHz) DCDR[4:0] 00001 00010 00100 01000 10000 Clock Division Ratio 1/1 1/2 1/4 1/8 1/16 50.000 50.000 25.000 12.500 6.250 3.125 (Initial value) Any setting other than above is handled as a clock division ratio of 1/1 (initial value). Note: The access size indicates the size the CPU uses to access (read from or write to) the register. When accessing this register in a size other than the displayed one, LCDC operation is not guaranteed. Only 0 can be written to a reserved bit. When a setting not allowed is made, e.g. a reserved bit is written to, though the LCDC operates with its initial values, normal operation is not guaranteed. This is the common rule to all registers in this LCDC. 25.2.2 LCDC Module Type Register (LDMTR) LDMTR sets the control signals output from this LCDC and the polarity of the data signals, according to the polarity of the signals for the LCD module connected to the LCDC. Bit: 15 FLM POL Initial value: R/W: 0 R/W 14 CL1 POL 0 R/W 13 DISP POL 0 R/W 12 DPOL 0 R/W 11 -- 0 R 10 MCNT 0 R/W 9 CL1 CNT 0 R/W 8 CL2 CNT 1 R/W 7 -- 0 R 6 -- 0 R 5 MIF TYP5 0 R/W 4 MIF TYP4 0 R/W 3 MIF TYP3 1 R/W 2 MIF TYP2 0 R/W 1 MIF TYP1 0 R/W 0 MIF TYP0 1 R/W Bits 11, 7, and 6--Reserved Bit 15--FLM (Vertical Sync Signal) Polarity Select (FLMPOL): Selects the polarity of the FLM (vertical sync signal, first line marker) for the LCD module. Bit 15 FLMPOL 0 1 Description FLM pulse is high active FLM pulse is low active (Initial value) Rev. 5.00 Dec 12, 2005 page 768 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bit 14--CL1 (Horizontal Sync Signal) Polarity Select (CL1POL): Selects the polarity of the CL1 (horizontal sync signal) for the LCD module. Bit 14 CL1POL 0 1 Description CL1 pulse is high active CL1 pulse is low active (Initial value) Bit 13--DISP (Display Enable) Polarity Select (DISPPOL): Selects the polarity of the DISP (display enable) for the LCD module. Valid for TFT panels only. Bit 13 DISPPOL 0 1 Description DISP is high active DISP is low active (Initial value) Bit 12--Display Data Polarity Select (DPOL): Selects the polarity of the LCDD (display data) for the LCD module. This bit supports inversion of the LCD module. Bit 12 DPOL 0 1 Description LCDD is high active, transparent-type LCD panel LCDD is low active, can be used for reflective-type LCD panels (Initial value) Bit 10--M Signal Control (MCNT): Sets whether or not to output the LCD's current-alternating signal of the LCD module. Valid for STN/DSTN. Bit 10 MCNT 0 1 Description M (AC line modulation) signal is output M signal is fixed low (Initial value) Rev. 5.00 Dec 12, 2005 page 769 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bit 9--CL1 (Horizontal Sync Signal) Control (CL1CNT): Sets whether or not to enable CL1 output during the vertical retrace period. Bit 9 CL1CNT 0 1 Description CL1 is output during vertical retrace period CL1 is inactive during vertical retrace period (Initial value) Bit 8--CL2 (Data Latch Clock of LCD Module) Control (CL2CNT): Sets whether or not to enable CL2 output during the vertical retrace period. Bit 8 CL2CNT 0 1 Description CL2 is output during vertical retrace period CL2 is inactive during vertical and horizontal retrace periods (Initial value) Bits 5 to 0--Module Interface Type Select (MIFTYP5 to MIFTYP0): Set the LCD panel type and data bus width for output to the LCD panel. There are three LCD panel types: STN, DSTN, and TFT. There are four data bus widths for output to the LCD panel: 4, 8, 12, and 16 bits. When the required data bus width for a TFT panel is 16 bits or less, connect the LCDC and LCD panel according to the data bus size of the LCD panel. Unlike in a TFT panel, in an STN or DSTN panel, the data bus width setting does not have a 1:1 correspondence with the number of display colors and display resolution, e.g., an 8-bit data bus can be used for 16 bpp, and a 12-bit data bus can be used for 4 bpp. This is because the number of display colors in an STN or DSTN panel is determined by how data is placed on the bus, and not by the bus width. For data specifications for an STN or DSTN panel, see the specifications of the LCD panel used. The output data bus width should be set according to the mechanical interface specifications of the LCD panel. If an STN or DSTN panel is selected, display control is performed using a 24-bit spacemodulation FRC (Frame Rate Controller) consisting of the 8-bit R, G, and B included in the LCDC, regardless of the color and gradation settings. Accordingly, the color and gradation specified by DSPCOLOR is selected from 16 million colors in an STN or DSTN panel. If a palette is used, the color specified in the palette is displayed. Rev. 5.00 Dec 12, 2005 page 770 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bit 5 MIFTYP5 0 Bit 4 MIFTYP4 0 Bit 3 MIFTYP3 0 1 Bit 2 MIFTYP2 0 0 Bit 1 MIFTYP1 0 0 Bit 0 MIFTYP0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 1 1 Other than above Description STN monochrome 4-bit data bus module STN monochrome 8-bit data bus module STN color 4-bit data bus module STN color 8-bit data bus module (Initial value) STN color 12-bit data bus module STN color 16-bit data bus module DSTN monochrome 8-bit data bus module DSTN monochrome 16-bit data bus module DSTN color 8-bit data bus module DSTN color 12-bit data bus module DSTN color 16-bit data bus module TFT color 16-bit data bus module Reserved 25.2.3 LCDC Data Format Register (LDDFR) LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of colors used for display so as to match the display driver software specifications. Bit: 15 -- 14 -- 13 -- 12 -- 11 -- 10 -- 9 -- 8 PABD 7 -- 6 5 4 3 2 1 0 DSP DSP DSP DSP DSP DSP DSP COLOR COLOR COLOR COLOR COLOR COLOR COLOR 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R Bits 15 to 9 and 7--Reserved Rev. 5.00 Dec 12, 2005 page 771 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bit 8--Byte Data Pixel Alignment (PABD): Sets the pixel data alignment type in one byte of data. The contents of aligned data per pixel are the same regardless of this bit's setting. For example, data H'05 should be expressed as 0101 (binary) which is the normal style handled by a MOV instruction of the SH7727 CPU, and should not be selected between 0101 (binary) and 1010 (binary). Bit 8 PABD 0 1 Description Big endian for byte data Little endian for byte data (Initial value) Bits 6 to 0--Display Color Select (DSPCOLOR6 to DSPCOLOR0): Set the number of display colors for the display (0 is written to upper bits of for unpacked 4, 5, and 6 bpp). For display colors to which the description (via palette) is added below, the color set by the color palette is actually selected by the display data and displayed. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DSP DSP DSP DSP DSP DSP DSP COLOR6 COLOR5 COLOR4 COLOR3 COLOR2 COLOR1 COLOR0 Description 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 Other than above 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 Monochrome, 2 grayscales, 1 bpp (via palette) Monochrome, 4 grayscales, 2 bpp (via palette) Monochrome, 16 grayscales, 4 bpp (via palette) Monochrome, 64 grayscales, 6 bpp (via palette) Color, 16 colors, 4 bpp (via palette) Color, 256 colors, 8 bpp (via palette) Color, 32k colors (RGB: 555), 15 bpp Color, 64k colors (RGB: 565), 16 bpp Reserved Note: The number of colors that can be selected in rotation mode is restricted by the display resolution. For details, see table 25.3, in section 25.3, Operation. Rev. 5.00 Dec 12, 2005 page 772 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.4 LCDC Scan Mode Register (LDSMR) LDSMR selects whether or not to enable the hardware rotation function that is used to rotate the LCD panel, and sets the burst length for the system memory (VRAM) obtained for display. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 ROT 0 R/W 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 AU1 0 R/W 8 AU0 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R Bits 15, 14, 12 to 10, and 7 to 0--Reserved Bit 13--Rotation Module Select (ROT): Selects whether or not to rotate the display by hardware. Note that the following restrictions are applied to rotation. * An STN or TFT panel must be used. A DSTN panel is not allowed. * The maximum horizontal (internal scan direction of the LCD panel) width of the LCD panel is 320. * Set a binary exponential that exceeds the display size in LDLAOR. (For example, select 256 when a 320 x 240 panel is rotated to be used as a 240 x 320 panel and the horizontal width of the image is 240 bytes.) Bit 13 ROT 0 1 Description Not rotated (Initial value) Rotated 90 degrees rightwards (left side of image is displayed on the upper side of the LCD module) Bits 9 and 8--Access Unit Select (AU1 and AU0): Select the unit for accessing VRAM. This bit is valid only when the ROT bit is set to 1 (rotation is performed). When the ROT bit is cleared to 0, 16-burst operation is performed regardless of the AU bits. Bit 9 AU1 0 1 Bit 8 AU0 0 1 0 1 Description 4-burst operation 8-burst operation 16-burst operation 32-burst operation (Initial value) Rev. 5.00 Dec 12, 2005 page 773 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) LDSARU sets the start address from which data is fetched by the LCDC for upper display of the LCDC panel. When a DSTN panel is used, this register specifies the fetch start address for the upper side of the panel. Bit: 31 -- Initial value: R/W: 0 R/W 30 -- 0 R/W 29 -- 0 R/W 28 -- 0 R/W 27 -- 1 R/W 26 -- 1 R/W 25 24 23 22 21 20 19 18 17 16 SAU25 SAU24 SAU23 SAU22 SAU21 SAU20 SAU19 SAU18 SAU17 SAU16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 SAU8 0 R/W 7 SAU7 0 R/W 6 SAU6 0 R/W 5 SAU5 0 R/W 4 SAU4 0 R/W 3 SAU3 0 R/W 2 SAU2 0 R/W 1 SAU1 0 R/W 0 SAU0 0 R/W SAU15 SAU14 SAU13 SAU12 SAU11 SAU10 SAU9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 31 to 26--Reserved Bits 25 to 0--Start Address for Upper Display Data Fetch (SAU31 to SAU0): The start address for data fetch of the display data must be set within the synchronous DRAM area of area 3. Notes: 1. When using the hardware rotation function (ROT = 1), set the LDSARU value so that the upper-left address of the image is aligned with the 512-byte boundary. 2. When the hardware rotation function is used (ROT = 1), set the upper-left address of the image which can be calculated from the display image size in this register. The equation below shows how to calculate the LDSARU value when the image size is 240 x 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but from the memory size of the image to be displayed. Note that LDLAOR must be a binary exponential at least as large as the horizontal width of the image. Calculate backwards using the LDSARU value (LDSARU - 256 (LDLAOR value) x (320 - 1)) to ensure that the upper-left address of the image is aligned with the 512-byte boundary. LDSARU = (upper-left address of image) + 256 (LDLAOR value) x 319 (line) Rev. 5.00 Dec 12, 2005 page 774 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) LDSARL sets the start address from which data is fetched by the LCDC for lower display of the LCD panel. When a DSTN panel is used, this register specifies the fetch start address for the lower side of the panel. Bit: 31 -- Initial value: R/W: 0 R/W 30 -- 0 R/W 29 -- 0 R/W 28 -- 0 R/W 27 -- 1 R/W 26 -- 1 R/W 25 24 23 22 21 20 19 18 17 16 SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 SAL8 0 R/W 7 SAL7 0 R/W 6 SAL6 0 R/W 5 SAL5 0 R/W 4 SAL4 0 R/W 3 SAL3 0 R/W 2 SAL2 0 R/W 1 SAL1 0 R/W 0 SAL0 0 R/W SAL15 SAL14 SAL13 SAL12 SAL11 SAL10 SAL9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 31 to 26--Reserved Bits 25 to 0--Start Address for Lower Panel Display Data Fetch (SAL31 to SAL0): The start address for data fetch of the display data must be set within the synchronous DRAM area of area 3. STN and TFT: Cannot be used DSTN: Start address for fetching display data corresponding to the lower panel Note: The minimum alignment unit of LDSARU and LDSARL is four bytes. Because the LCDC handles these values as longword data, the values written to the lower two bits of each register are always treated as 0. The lower two bits of each register are always read as 0. For 1 or 2 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits). (Data at the start of each line is always valid.) Data that exceeds the longword boundary at the end of each line (1, 2, or 3 bytes) will be discarded. For 4, 8, 15, 16, or 32 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits). Rev. 5.00 Dec 12, 2005 page 775 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) LDLAOR sets the address width of the Y-coordinates increment used for LCDC to read the image recognized by the graphics driver. This register specifies how many bytes the address from which data is to be read should be moved when the Y coordinates (vertical direction) have been incremented by 1. This register does not have to be equal to the horizontal width of the LCD panel. When the memory address of a point (X, Y) in the two-dimensional image is calculated by Ax + By+ C, this register becomes equal to B in this equation. Bit: 15 14 13 12 11 10 9 8 LAO8 0 R/W 7 LAO7 1 R/W 6 LAO6 0 R/W 5 LAO5 0 R/W 4 LAO4 0 R/W 3 LAO3 0 R/W 2 LAO2 0 R/W 1 LAO1 0 R/W 0 LAO0 0 R/W LAO15 LAO14 LAO13 LAO12 LAO11 LAO10 LAO9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W Bits 15 to 0--Line Address Offset (LDLAOR) Notes: 1. The minimum alignment unit of LDLAOR is four bytes. Because the LCDC handles these values as longword data, the values written to the lower two bits of the register are always treated as 0. The lower two bits of the register are always read as 0. The initial values (x resolution = 640) will continuously and accurately place the VGA (640 x 480 dots) display data without skipping an address between lines. For details, see table 25.3, in section 25.3, Operation. 2. A binary exponential at least as large as the horizontal width of the image is recommended for the LDLAOR value, taking into consideration the software operation speed. When the hardware rotation function is used (ROT = 1), the LDLAOR value should be a binary exponential (in this example, 256) at least as large as the horizontal width of the image (after rotation, it becomes 240 in a 240 x 320 panel) instead of the horizontal width of the LCD panel (320 in a 320 x 240 panel). Rev. 5.00 Dec 12, 2005 page 776 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.8 LCDC Palette Control Register (LDPALCR) LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette memory is being used for display operation, display mode should be selected. When the palette memory is being written to, CPU access mode should be selected. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PALS 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PALEN 0 R/W Bits 15 to 5 and 3 to 1--Reserved Bit 4--Palette State (PALS): Indicates the access right state of the palette. Bit 4 PALS 0 1 Description Display mode: LCDC uses the palette CPU access mode: The host (CPU) uses the palette (Initial value) Bit 0--Palette Read/Write Enable (PALEN): Controls CPU accesses to the palette. Bit 0 PALEN 0 1 Description Display mode: LCDC uses the palette CPU access mode: The host (CPU) uses the palette (Initial value) Rev. 5.00 Dec 12, 2005 page 777 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) These registers are for accessing palette data directly allocated (4 bytes x 256 addresses) to the memory space. To access the palette memory, access the corresponding register among this register group (LDPR00 to LDPRFF). Each palette register is a 32-bit register including three 8-bit areas for R, G, and B. For details on the color palette specifications, see section 25.3.3, Color Palette Specification. Bit: 31 -- Initial value: R/W: * R 30 -- * R 29 -- * R 28 -- * R 27 -- * R 26 -- * R 25 -- * R 24 -- * R 23 22 21 20 19 18 17 16 PAL PAL PAL PAL PAL PAL PAL PAL D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF D00-FF Initial value: R/W: *: Undefined * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Bits 31 to 24--Reserved Bits 18 to 16, 9, 8, and 2 to 0--Reserved Bits in Palettes R, G, and B (Though they cannot be changed, they are extended according to the upper bits.) Bits 23 to 19, 15 to 10, 7 to 3--Palette Data (PALD00 to PALDFF): PALD00: H'10008000 PALDnn: (H'10008000+4xnn) PALDFF: H'100083FC Rev. 5.00 Dec 12, 2005 page 778 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.10 LCDC Horizontal Character Number Register (LDHCNR) LDHCNR specifies the LCD module's horizontal size (in the scan direction) and the entire scan width including the horizontal retrace period. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDCN7 HDCN6 HDCN5 HDCN4 HDCN3 HDCN2 HDCN1 HDCN0 HTCN7 HTCN6 HTCN5 HTCN4 HTCN3 HTCN2 HTCN1 HTCN0 Initial value: R/W: 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 1 R/W 0 R/W Bits 15 to 8--Horizontal Display Character Number (HDCN): Set the number of horizontal display characters (unit: character = 8 dots). Subtract 1 from the setting (0 to 252 (H'FC)). Example: For an LCD module with a width of 640 pixels HDCN = (640/8) - 1 = 79 = H'4F Bits 7 to 0--Horizontal Total Character Number (HTCN): Set the number of total horizontal characters (unit: character = 8 dots). Subtract 1 from the setting (3 to 255 (H'FF)). The minimum horizontal retrace period is three characters (24 dots). The values set in HDCN and HTCN must satisfy the relationship of HTCN HDCN + 3. HTCN should be set to an odd number value when using a color STN 16-bit I/F module. Example: For an LCD module with a width of 640 pixels HTCN = [(640/8) - 1] + 3 = 82 = H'52 Rev. 5.00 Dec 12, 2005 page 779 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.11 LCDC Horizontal Sync Signal Register (LDHSYNR) LDHSYNR specifies the timing of the generation of the horizontal (scan direction) sync signals (CL1/Hsync) for the LCD module. Bit: 15 14 13 12 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 6 5 4 3 2 1 0 HSYN HSYN W3 W2 Initial value: R/W: 0 R/W 0 R/W HSYN HSYN W1 W0 0 R/W 0 R/W HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP 7 6 5 4 3 2 1 0 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 to 12--Horizontal Sync Signal Width (HSYNW): Sets the width in characters of the horizontal sync signals (CL1 and Hsync). Subtract 1 from the setting (0 to 15 (H'F)). Example: For a horizontal sync signal width of 8 dots HSYNW = (8 dots/8 dots/character) - 1 = 0 = H'0 Bits 7 to 0--Horizontal Sync Signal Output Position (HSYNP): Sets the output position in characters of the horizontal sync signals. Subtract 1 from the setting (0 to 255 (H'FF)). The following conditions must be satisfied: HTCN >= HSYNP + HSYNW + 1 HSYNP >= HDCN + 1 Example: For an LCD module with a width of 640 pixels HSYNP = [(640/8) + 1] - 1 = 80 = H'50 In this case, the horizontal sync signal is active from the 648th through the 655th dot. Rev. 5.00 Dec 12, 2005 page 780 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.12 LCDC Vertical Display Line Number Register (LDVDLNR) LDVDLNR specifies the LCD module's vertical size (for both scan direction and vertical direction). For a DSTN panel, specify an even number at least as large as the LCD panel's vertical size regardless of the size of the up and down panels, e.g. 480 for a 640 x 480 panel. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 VDLN 10 0 R/W 9 VDLN 9 0 R/W 8 VDLN 8 1 R/W 7 VDLN 7 1 R/W 6 VDLN 6 1 R/W 5 VDLN 5 0 R/W 4 VDLN 4 1 R/W 3 VDLN 3 1 R/W 2 VDLN 2 1 R/W 1 VDLN 1 1 R/W 0 VDLN 0 1 R/W Bits 15 to 11--Reserved Bits 10 to 0--Vertical Display Line Number (VDLN): Set the number of vertical display lines (unit: line). Subtract 1 from the setting (0 to 2047 (H'7FF)). Example: For an 480-line LCD module VDLN = 480 - 1 = H'1DF Rev. 5.00 Dec 12, 2005 page 781 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.13 LCDC Vertical Total Line Number Register (LDVTLNR) LDVTLNR specifies the LCD panel's entire vertical size including the vertical retrace period. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 VTLN 10 0 R/W 9 VTLN 9 0 R/W 8 VTLN 8 1 R/W 7 VTLN 7 1 R/W 6 VTLN 6 1 R/W 5 VTLN 5 0 R/W 4 VTLN 4 1 R/W 3 VTLN 3 1 R/W 2 VTLN 2 1 R/W 1 VTLN 1 1 R/W 0 VTLN 0 1 R/W Bits 15 to 11--Reserved Bits 10 to 0--Vertical Total Line Number (VTLN): Set the total number of vertical display lines (unit: line). Subtract 1 from the setting (1 to 2047 (H'7FF)). The minimum for the total number of vertical lines is 2 lines. The following conditions must be satisfied: VTLN >= VDLN, VTLN >= 1 Example: For an 480-line LCD module and a vertical retrace period of 0 lines VTLN = (480 + 0) - 1 = 479 = H'1DF Rev. 5.00 Dec 12, 2005 page 782 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.14 LCDC Vertical Sync Signal Register (LDVSYNR) LDVSYNR specifies the timing of the generation of the vertical (scan direction and vertical direction) sync signals (FLM/Vsync) for the LCD module. Bit: 15 VSYN W3 Initial value: R/W: 0 R/W 14 VSYN W2 0 R/W 13 VSYN W1 0 R/W 12 VSYN W0 0 R/W 11 -- 0 R 10 9 8 7 6 5 4 3 2 1 0 VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 11--Reserved Bits 15 to 12--Vertical Sync Signal Width (VSYNW): Set the width of the vertical sync signals (FLM and Vsync) (unit: line). Subtract 2 from the setting (0 to 15 (H'F)). Example: For a vertical sync signal width of 1 line VSYNW = (1 - 1) = 0 = H'0 Bits 10 to 0-- Vertical Sync Signal Output Position (VSYNP): Set the output position of the vertical sync signals (FLM and Vsync) (unit: line). Subtract 2 from the setting (0 to 2046 (H'7FE)). DSTN should be set to an odd number value. It is handled as (setting value + 1)/ 2. Example: For an 480-line LCD module and a vertical retrace period of 0 lines (in other words, VTLN = 479 and the vertical sync signal is active for the first line): * Single display VSYNP=[(1-1)+VTLN] mod (VTLN+1) = [(1-1)+479] mod (479+1) = 479 mod 480 = 479 = H'1DF * Dual displays VSYNP=[(1-1)x2+VTLN] mod (VTLN+1) = [(1-1)x2+479] mod (479+1) = 479 mod 480 = 479 = H'1DF Rev. 5.00 Dec 12, 2005 page 783 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) LDACLNR specifies the timing to toggle the AC modulation signal (LCD current-alternating signal) of the LCD module. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 3 2 1 0 ACLN4 ACLN3 ACLN2 ACLN1 ACLN0 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W Bits 15 to 5--Reserved Bits 4 to 0--AC Line Number (ACLN): Set the line number where the LCD current-alternating signal of the LCD module is toggled (unit: line). Subtract 1 from the setting (0 to 31 (H'1F)). Note: When the total line number of the LCD panel is even, set an even number so that toggling is performed at an odd line. Example: For toggling every 13 lines ACLN = 13 - 1 = 12 = H'0C 25.2.16 LCDC Interrupt Control Register (LDINTR) LDINTR specifies where to start the Vsync interrupt (LCDCI). Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 VINT SEL 0 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 VINTE 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 VINTS 0 R/W Bits 15 to 13, 11 to 9, and 7 to 1--Reserved Rev. 5.00 Dec 12, 2005 page 784 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bit 12--Vsync Interrupt Select (VINTSEL): Sets the starting point of the LCDC's Vsync interrupt. Bit 12 VINTSEL 0 1 Description Vsync interrupt is generated at starting point of vertical retrace period for memory access (Initial value) Vsync interrupt is generated at starting point of vertical retrace period for LCD display Bit 8--Vsync Interrupt Enable (VINTE): Sets whether or not to enable LCDC's Vsync interrupts. Bit 8 VINTE 0 1 Description Vsync interrupts are disabled Vsync interrupts are enabled (Initial value) Bit 0--Vsync Interrupt State (VINTS): Indicates the LCDC's Vsync interrupt handling state. This bit is set to 1 at the time a Vsync interrupt is generated. During the Vsync interrupt handling routine, this bit should be cleared by writing 0 to it. Bit 0 VINTS 0 1 Description LCDC did not generate a Vsync interrupt or has been informed that the generated Vsync interrupt has completed (Initial value) LCDC has generated a Vsync interrupt and has not yet been informed that the generated Vsync interrupt has completed Notes: * Interrupt Handling Flow: 1. An interrupt signal is input to the CPU. 2. The CPU reads from VINTS. 3. If VINTS is set to 1, a Vsync interrupt has occurred, and the Vsync interrupt handling is carried out. 4. If VINTS is cleared to 0, no Vsync interrupt has occurred and another processing is carried out. * When Vsync interrupts are enabled, the VINTE bit must be set to 1 before the DON bit is set to 1, and the VINTE bit must not be cleared to 0. Rev. 5.00 Dec 12, 2005 page 785 of 1034 REJ09B0254-0500 Section 25 LCD Controller Hsync signal Vsync signal H total time Hsync Back Left porch border time H addressable video Right border Front porch Vsync time Back porch Top border V total time V addressable video Bottom border Front porch Active video = top/left border + addressable video + bottom/right border Total H blank = Hsync time + back porch + front porch Total V blank = Vsync time + back porch + front porch HTCN = H total time HDCN = H addressable video HSYNP = H addressable video + right border + front porch HSYNW = Hsync time VTLN = V total time CDLN = V addressable video VSYNP = V addressable video + bottom border + front porch VSYNW = Vsync time Figure 25.2 Valid Display and Retrace Period 25.2.17 LCDC Power Management Mode Register (LDPMMR) LDPMMR controls the power supply circuit that provides power to the LCD module. The usage of two types of power-supply control pins, VCPWC and VEPWC, and turning on or off the power supply are selected. Bit: 15 14 13 12 11 10 9 8 7 -- 0 R 6 VCPE 0 R/W 5 VEPE 0 R/W 4 DONE 1 R/W 3 -- 0 R 2 -- 0 R 1 LPS1 0 R 0 LPS0 0 R ONC3 ONC2 Initial value: R/W: 0 R/W 0 R/W ONC1 ONC0 OFFD3 OFFD2 OFFD1 OFFD0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 5.00 Dec 12, 2005 page 786 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bits 7, 3, and 2--Reserved Bits 15 to 12--LCDC Power-On Sequence Period (ONC): Set the period from VEPWC assertion to DON assertion in the power-on sequence of the LCD module in frame units. This period is the (c) period in figures 25.4 to 25.7. For details on setting this register, see table 25.4. (The setting method is common for ONC, ONA, ONB, OFFD, OFFE, and OFFF.) 1 is to be subtracted from the setting. Bits 11 to 8--LCDC Power-Off Sequence Period (OFFD): Set the period from DON negation to VEPWC negation in the power-off sequence of the LCD module in frame units. This period is the (d) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. Bit 6--VCPWC Pin Enable (VCPE): Sets whether or not to enable a power-supply control sequence using the VCPWC pin. Bit 6 VCPE 0 1 Description Disabled: VCPWC pin is masked and fixed low (Initial value) Enabled: VCPWC pin output is asserted and negated according to the power-on or power-off sequence Bit 5--VEPWC Pin Enable (VEPE): Sets whether or not to enable a power-supply control sequence using the VEPWC pin. Bit 5 VEPE 0 1 Description Disabled: VEPWC pin is masked and fixed low (Initial value) Enabled: VEPWC pin output is asserted and negated according to the power-on or power-off sequence Bit 4--DON Pin Enable (DONE): Sets whether or not to enable a power-supply control sequence using the DON pin. Bit 4 DONE 0 1 Description Disabled: DON pin is masked and fixed low Enabled: DON pin output is asserted and negated according to the power-on or poweroff sequence (Initial value) Rev. 5.00 Dec 12, 2005 page 787 of 1034 REJ09B0254-0500 Section 25 LCD Controller Bits 1 and 0--LCD Module Power-Supply Input State (LPS1 and LPS0): Indicate the powersupply input state of the LCD module when using the power-supply control function. Bit 1 LPS1 0 1 Bit 0 LPS0 0 1 Description LCD module power off LCD module power on (Initial value) 25.2.18 LCDC Power-Supply Sequence Period Register (LDPSPR) LDPSPR controls the power supply circuit that provides power to the LCD module. The timing to start outputting the timing signals to the VEPWC and VCPWC pins is specified. Bit: 15 ONA3 Initial value: R/W: 1 R/W 14 ONA2 1 R/W 13 ONA1 1 R/W 12 ONA0 1 R/W 11 ONB3 0 R/W 10 ONB2 1 R/W 9 ONB1 1 R/W 8 7 6 5 4 3 2 1 0 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bits 15 to 12--LCDC Power-On Sequence Period (ONA): Set the period from VCPWC assertion to starting output of the display data (LCDD) and timing signals (FLM, CL1, CL2, and M/DISP) in the power-on sequence of the LCD module in frame units. This period is the (a) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. Bits 11 to 8--LCDC Power-On Sequence Period (ONB): Set the period from starting output of the display data (LCDD) and timing signals (FLM, CL1, CL2, and DISP/M) to the VEPWC assertion in the power-on sequence of the LCD module in frame units. This period is the (b) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. Bits 7 to 4--LCDC Power-Off Sequence Period (OFFE): Set the period from VEPWC negation to stopping output of the display data (LCDD) and timing signals (FLM, CL1, CL2, and DISP/M) in the power-off sequence of the LCD module in frame units. This period is the (e) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. Bits 3 to 0--LCDC Power-Off Sequence Period (OFFF): Set the period from stopping output of the display data (LCDD) and timing signals (FLM, CL1, CL2, and DISP/M) to VCPWC negation to in the power-off sequence of the LCD module in frame units. This period is the (f) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. Rev. 5.00 Dec 12, 2005 page 788 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.2.19 LCDC Control Register (LDCNTR) LDCNTR specifies start and stop of display by the LDCD. Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 DON2 0 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 DON 0 R/W Bits 15 to 1--Reserved Bit 4-- Display start auxiliary bit (DON2): Specifies the start of display operation using LCDC. LCDC operation cannot be guaranteed if 0 is written to this bit at any time other than the start of display operation. Note that a 1 written to this bit is automatically cleared to 0, so it is not necessary to write 0 to it in order to clear it. Bit 0--Display On (DON): Specifies the start and stop of the LCDC display operation. The control sequence state can be checked by referencing the LPS value in bit 0 of the LCDC power management mode register (LDPMMR). Bit 4 DON2 0 1 Bit 0 DON 0 1 Description Display-off mode: LCDC is stopped Display-on mode: LCDC operates (Initial value) Starting LCDC Display Operation (DON2 and DON bits change from B'00 to B'11): 1. Start LCDC operation. 2. Turn on the LCD module following the sequence set in the LCDC power management mode register (LDPMMR) and LCDC control register (LDCNTR). The sequence ends when the LPS value changes from B'00 to B'11. Do not make any action to the DON bit until the sequence ends. Stopping LCDC Display Operation (DON2 and DON bits change from B'01 to B'00): 1. Turn off the LCD module following the sequence set in the LCDC power management mode register (LDPMMR) and LCDC control register (LDCNTR). 2. Stop LCDC operation. The sequence ends when the LPS value changes from B'11 to B'00. Do not make any action to the DON bit until the sequence ends. Rev. 5.00 Dec 12, 2005 page 789 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.3 25.3.1 Operation LCD Module Sizes which can be Displayed in this LCDC This LCDC is capable of controlling displays with up to 1024 x 1024 dots and 16 bpp (bits per pixel). The image data for display is stored in system memory, which is shared with the CPU. This LCDC should read the data from system memory between display periods. The SH7727 has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so although a complete breakdown of the display is unlikely, there may be some problems with the display depending on the combination. The bus-occupancy rate described below should not, as a rule, exceed 40%. Overhead coefficient x total number of display pixels ((HDCN + 1) x 8 x (VDLN + 1)) x frame rate (Hz) x number of colors (bpp) x 100 CKIO (Hz) x bus width (bits) Bus-occupancy rate (%) = The overhead coefficient depends on the bus used by the SDRAM in CL2, as indicated below. If the hardware rotation function is not used (ROT = 0), the overhead coefficient is 1.375 if a 32bit bus is used and 1.188 if a 16-bit bus is used. If the hardware rotation function is used (ROT = 1), the overhead coefficient is determined by the access unit select (AU) setting and the bus width, as follows. Access Unit Select (AU) Setting 4-burst operation 8-burst operation 16-burst operation 32-burst operation 32-Bit Bus 2.500 1.750 1.375 1.188 16-Bit Bus 1.750 1.375 1.188 1.094 Rev. 5.00 Dec 12, 2005 page 790 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.3.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (SDRAM) This LCDC is capable of displaying a landscape-format image on a LCD module by rotating a portrait format image for display by 90 degrees. Only the numbers of colors for each resolution are supported as shown in tables 25.3 and 25.4. The size of the SDRAM (the number of column address bits) and its burst length are limited to read the SDRAM continuously. The number of colors for display, SDRAM column addresses, and LCDC burst length are shown table 25.3 and 25.4. A monochromatic LCD module is necessary for the display of images in the above monochromatic formats. A color LCD module is necessary for the display of images in the above color formats. Rev. 5.00 Dec 12, 2005 page 791 of 1034 REJ09B0254-0500 Section 25 LCD Controller Table 25.3 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (32-bit Bus SDRAM) Image for Display LCD Module in Memory (X-Resolution x (X-Resolution x Y-Resolution) Y-Resolution) 240 x 320 320 x 240 Number of Colors for Display Monochrome 4 bpp (packed) Number of Column Address Bits of SDRAM 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 6 bpp 8 bits 9 bits 10 bits Color 8 bpp 8 bits 9 bits 10 bits 16 bpp 8 bits 9 bits 10 bits 234 x 320 320 x 234 Monochrome 6 bpp 8 bits 9 bits 10 bits Color 16 bpp 8 bits 9 bits 10 bits 4 bursts Not more than 8 bursts Not more than 16 bursts 4 bursts Not more than 8 bursts Not more than 16 bursts 4 bursts Not more than 8 bursts Not more than 16 bursts Unusable 4 bursts Not more than 8 bursts 4 bursts Not more than 8 bursts Not more than 16 bursts Unusable 4 bursts Not more than 8 bursts Burst Length of LCDC (LDSMR*) Not more than 8 bursts Not more than 16 bursts -- Rev. 5.00 Dec 12, 2005 page 792 of 1034 REJ09B0254-0500 Section 25 LCD Controller Image for Display LCD Module in Memory (X-Resolution x (X-Resolution x Y-Resolution) Y-Resolution) 80 x 160 160 x 80 Number of Column Address Bits of SDRAM 8 bits 9 bits 10 bits 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 6 bpp 8 bits 9 bits 10 bits Color 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 8 bpp 8 bits 9 bits 10 bits 16 bpp 8 bits 9 bits 10 bits 4 bursts Not more than 8 bursts Not more than 16 bursts Number of Colors for Display Monochrome 2 bpp Burst Length of LCDC (LDSMR*) -- -- -- Not more than 16 bursts -- -- Not more than 8 bursts Not more than 16 bursts -- Not more than 8 bursts Not more than 16 bursts -- Not more than 16 bursts -- -- Not more than 8 bursts Not more than 16 bursts -- Not more than 8 bursts Not more than 16 bursts -- Rev. 5.00 Dec 12, 2005 page 793 of 1034 REJ09B0254-0500 Section 25 LCD Controller Image for Display LCD Module in Memory (X-Resolution x (X-Resolution x Y-Resolution) Y-Resolution) 64 x 128 128 x 64 Number of Column Address Bits of SDRAM 8 bits 9 bits 10 bits 2 bpp 8 bits 9 bits 10 bits 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 6 bpp 8 bits 9 bits 10 bits Color 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 8 bpp 8 bits 9 bits 10 bits Number of Colors for Display Monochrome 1 bpp Burst Length of LCDC (LDSMR*) -- -- -- -- -- -- -- -- -- Not more than 16 bursts -- -- Not more than 16 bursts -- -- -- -- -- Not more than 16 bursts -- -- Not more than 16 bursts -- -- Note: * Specify the data of the number of line specified as burst length can be stored in address of SDRAM same as that of ROW. Rev. 5.00 Dec 12, 2005 page 794 of 1034 REJ09B0254-0500 Section 25 LCD Controller Table 25.4 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (16-bit Bus SDRAM) Image for Display LCD Module in Memory (X-Resolution x (X-Resolution x Y-Resolution) Y-Resolution) 240 x 320 320 x 240 Number of Colors for Display Monochrome 4 bpp (packed) Number of Column Address Bits of SDRAM 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 6 bpp 8 bits 9 bits 10 bits Color 8 bpp 8 bits 9 bits 10 bits 16 bpp 8 bits 9 bits 10 bits 234 x 320 320 x 234 Monochrome 6 bpp 8 bits 9 bits 10 bits Color 16 bpp 8 bits 9 bits 10 bits Burst Length of LCDC (LDSMR*) Not more than 4 bursts Not more than 8 bursts Not more than 16 bursts Unusable 4 bursts Not more than 8 bursts Unusable 4 bursts Not more than 8 bursts Unusable 4 bursts Not more than 8 bursts Unusable Unusable 4 bursts Unusable 4 bursts Not more than 8 bursts Unusable Unusable 4 bursts Rev. 5.00 Dec 12, 2005 page 795 of 1034 REJ09B0254-0500 Section 25 LCD Controller Image for Display LCD Module in Memory (X-Resolution x (X-Resolution x Y-Resolution) Y-Resolution) 80 x 160 160 x 80 Number of Column Address Bits of SDRAM 8 bits 9 bits 10 bits 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 6 bpp 8 bits 9 bits 10 bits Color 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 8 bpp 8 bits 9 bits 10 bits 16 bpp 8 bits 9 bits 10 bits 4 bursts Not more than 8 bursts Not more than 16 bursts 4 bursts Not more than 8 bursts Not more than 16 bursts Unusable 4 bursts Not more than 8 bursts 4 bursts Not more than 8 bursts Not more than 16 bursts 4 bursts Not more than 8 bursts Not more than 16 bursts Not more than 8 bursts Not more than 16 bursts -- Number of Colors for Display Monochrome 2 bpp Burst Length of LCDC (LDSMR*) Not more than 16 bursts -- -- Not more than 8 bursts Not more than 16 bursts -- Rev. 5.00 Dec 12, 2005 page 796 of 1034 REJ09B0254-0500 Section 25 LCD Controller Image for Display LCD Module in Memory (X-Resolution x (X-Resolution x Y-Resolution) Y-Resolution) 64 x 128 128 x 64 Number of Column Address Bits of SDRAM 8 bits 9 bits 10 bits 2 bpp 8 bits 9 bits 10 bits 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 6 bpp 8 bits 9 bits 10 bits Color 4 bpp (packed) 8 bits 9 bits 10 bits 4 bpp (unpacked) 8 bits 9 bits 10 bits 8 bpp 8 bits 9 bits 10 bits Number of Colors for Display Monochrome 1 bpp Burst Length of LCDC (LDSMR*) -- -- -- -- -- -- Not more than 16 bursts -- -- Not more than 8 bursts Not more than 16 bursts -- Not more than 8 bursts Not more than 16 bursts -- Not more than 16 bursts -- -- Not more than 8 bursts Not more than 16 bursts -- Not more than 8 bursts Not more than 16 bursts -- Note: * Specify the data of the number of line specified as burst length can be stored in address of SDRAM same as that of ROW. 25.3.3 Color Palette Specification Color Palette Register: This LCDC has a color palette which outputs 24 bits of data per entry and is able to simultaneously hold 256 entries. The color palette thus allows the simultaneous display of 256 colors chosen from among 16-M colors. The below procedure may be used to set up color palettes at any time. Rev. 5.00 Dec 12, 2005 page 797 of 1034 REJ09B0254-0500 Section 25 LCD Controller 1. The PALEN bit in the LCDC color palette register is 0 (initial value); normal display operation 2. Access LDPALCR and set the PALEN bit to 1; enter color-palette setting mode 3. Access LDPALCR and confirm that the PALS bit is 1. 4. Access LDPR00 to LDPRFF and write the required values to the PALD00 to PALDFF bits. 5. Access LDPALCR and clear the PALEN bit to 0; return to normal display mode 0 is output on the LCDC display data output (LCDD) while the controller is in color palette setting mode. 31 23 15 7 0 Color R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 Monochrome M7 M6 M5 M4 M3 M2 M1 M0 Figure 25.3 Color-Palette Data Format PALDnn color and gradation data should be set as above, using 256-gradation values for R, G, B, and M. For a color display, PALDnn [23:16], PALDnn [15:8], and PALDnn [7:0] respectively hold the R, G, and B data. Although the bits PALDnn [18:16], PALDnn [9:8], and PALDnn [2:0] exist, no memory is associated with these bits. PALDnn [18:16], PALDnn [9:8], and PALDnn [2:0] are thus not available for storing palette data. The numbers of valid bits are thus R: 5, G: 6, and B: 5.24-bit (R: 8 bits, G: 8 bits, and B: 8 bits) data should, however, be written to the palette-data registers. When the values for PALDnn [23:19], PALDnn [15:10], or PALDnn [7:3] are not 0, 1s should be written to PALDnn [18:16], PALDnn [9:8], or PALDnn [2:0], respectively. When the values of PALDnn [23:19], PALDnn [15:10], or PALDnn [7:3] are 0, 0 should be written to PALDnn [18:16], PALDnn [9:8], or PALDnn [2:0], respectively. Then 24 bits are extended. Grayscale data for a monochromatic display should be set in PALDnn [7:3]. PALDnn [23:8] are all `don't care'. When the value in PALDnn [7:3] is not 0, 1s should be written to PALDnn [2:0]. When the value in PALDnn [7:3] is 0, 0s should be written to PALDnn [2:0]. Then 8 bits are extended. Rev. 5.00 Dec 12, 2005 page 798 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.3.4 Data Format 1. Packed 1bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format] MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... P18 ... LAO: Line Address Offset Unused bits should be 0 ... P10 P11 P12 P13 P14 P15 P16 P17 Pn: Put 1bit data 7 P08 6 5 4 3 2 1 LSB 0 [Bit] (Byte1) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... P00 P01 P02 P03 P04 P05 P06 P07 (Byte0) Display Memory 2. Packed 2bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format] MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... P10 P14 ... P11 P15 ... P12 P16 P13 P17 LAO: Line Address Offset Unused bits should be 0 Pn=Pn[1:0]: Put 2bit data 7 P00 P04 6 5 P01 P05 4 3 P02 P06 2 1 P03 P07 LSB 0 [Bit] (Byte0) (Byte1) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... Display Memory 3. Packed 4bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format] MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... P00 P02 P04 ... Display Memory 7 6 P00 P02 P04 ... P01 P03 P05 LAO: Line Address Offset Unused bits should be 0 Pn=Pn[3:0]: Put 4bit data 5 4 3 2 P01 P03 P05 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... 4. Packed 1bpp (Pixel Alignment in Byte is Little Endian) MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... ... LAO: Line Address Offset Unused bits should be 0 ... P17 P16 P15 P14 P13 P12 P11 P10 P18 Pn: Put 1bit data 7 6 5 4 3 2 1 LSB 0 [Bit] P08 (Byte1) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... P07 P06 P05 P04 P03 P02 P01 P00 (Byte0) Display Memory Rev. 5.00 Dec 12, 2005 page 799 of 1034 REJ09B0254-0500 Section 25 LCD Controller 5. Packed 2bpp (Pixel Alignment in Byte is Little Endian) MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... P13 P17 ... P12 P16 ... P11 P15 P10 P14 LAO: Line Address Offset Unused bits should be 0 Pn = Pn[1:0]: Put 2bit data 7 P03 P07 6 5 P02 P06 4 3 P01 P05 2 1 P00 P04 LSB 0 [Bit] (Byte0) (Byte1) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... Display Memory 6. Packed 4bpp (Pixel Alignment in Byte is Little Endian) MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... P11 P13 P15 ... Display Memory 7 6 P01 P04 P06 ... P10 P12 P14 LAO: Line Address Offset Unused bits should be 0 Pn = Pn[3:0]: Put 4bit data 5 4 3 2 P00 P03 P05 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... 7. Unpacked 4bpp [Windows CE Recommended Format] MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... ... Display Memory ... P10 P11 P12 LAO: Line Address Offset Unused bits should be 0 Pn = Pn[3:0]: Put 4bit data 7 6 5 4 3 2 P00 P01 P02 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... 8. Unpacked 5bpp [Windows CE Recommended Format] MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... ... Display Memory ... P10 P11 P12 LAO: Line Address Offset Unused bits should be 0 Pn = Pn[4:0]: Put 5bit data 7 6 5 4 3 2 P00 P01 P02 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... Rev. 5.00 Dec 12, 2005 page 800 of 1034 REJ09B0254-0500 Section 25 LCD Controller 9. Unpacked 6bpp [Windows CE Recommended Format] MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... ... Display Memory ... P10 P11 P12 LAO: Line Address Offset Unused bits should be 09 Pn = Pn[5:0]: Put 6bit data 7 6 5 4 3 P00 P01 P02 2 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... 10. Packed 8bpp [Windows CE Recommended Format] MSB Address +00 +01 +02 +03 ... +LAO+00 +LAO+01 +LAO+02 +LAO+03 ... 7 6 5 4 P00 P01 P02 ... P10 P11 P12 ... Display Memory LAO: Line Address Offset Unused bits should be 0 Pn = Pn[7:0]: Put 8bit data 3 2 1 LSB 0 [Bit] (Byte0) (Byte1) (Byte2) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display ... ... 11. Unpacked color 15bpp (RGB 555) [Windows CE Recommended Format] MSB Address +00 +02 +04 +06 ... +LAO +LAO+02 +LAO+04 +LAO+06 ... P10R P11R P12R ... Display Memory 15 14 13 12 P00R P01R P02R ... P10G P11G P12G P10B P11B P12B 11 10 9 8 7 P00G P01G P02G 6 5 4 3 2 P00B P01B P02B 1 LSB 0 [Bit] (Word0) (Word2) (Word4) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... Display Pr = (PrR, PrG, PrB). Pr 15bit data PrR = PrR[4.0]. Pr 5bit RED data PrG = PrG[4.0]. Pr 5bit GREEN data PrB = PrB[4.0]. Pr 5bit BLUE data LAO: Line Address Offset Unused bits should be 0 ... ... 12. Packed color 16bpp (RGB 565) [Windows CE Recommended Format] MSB Address +00 +02 +04 +06 ... +LAO +LAO+02 +LAO+04 +LAO+06 ... P10R P11R P12R 15 14 13 P00R P01R P02R 12 11 10 9 8 P00G P01G P02G ... P10G P11G P12G ... Display Memory P10B P11B P12B 7 6 5 4 3 2 P00B P01B P02B 1 LSB 0 [Bit] (Word0) (Word2) (Word4) Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... Display Pr = (PrR, PrG, PrB). Pr 16bit data PrR = PrR[4.0]. Pr 5bit RED data PrG = PrG[5.0]. Pr 6bit GREEN data PrB = PrB[4.0]. Pr 5bit BLUE data LAO: Line Address Offset Unused bits should be 0 ... ... Rev. 5.00 Dec 12, 2005 page 801 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.3.5 Timing Controller Register The timing controller register is used to run the controller in a way that matches the display resolution of the LCD module. The display resolution is set up in the LCDC horizontal number character number register, LCDC horizontal synchronization signal register, LCDC vertical line displayed number register, LCDC vertical total line number register, and LCDC vertical synchronization signal register. The LCD current-alternating period for an STN or DSTN display is set by using the LCDC ac modulation signal toggle line number register. The initial values in these registers are typical settings for VGA (640 x 480 dots) on an STN or DSTN display. The clock to be used is set with the LCD input clock register. The LCD module frame rate is determined by the display interval + retrace line interval (non-display interval) for one screen set in a size related register and the frequency of the clock used. This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last line of the display). This function is set up by using the LCDC interrupt control register. 25.3.6 Power Management Registers An LCD module normally requires a specific sequence for processing to do with the cutoff of the input power supply. Settings in the LCDC power management mode register, LCDC power supply sequence period register, and LCDC control register, in conjunction with the LCD power-supply control pins (VCPWC, VEPWC, and DON), are used to provide processing of power-supply control sequences that suits the requirements of the LCD module. Figures 25.4 to 25.7 are summary timing charts for power-supply control sequences and table 25.5 is a summary of available power-supply control sequence periods. Rev. 5.00 Dec 12, 2005 page 802 of 1034 REJ09B0254-0500 Section 25 LCD Controller (1) STN, DSTN Power-Supply Control (in) DON register Start power supply (out) VCPWC pin (out) Display data, timing signal Start power cutoff VCPE = ON Undefined Arbitrary Undefined (out) VEPWC pin VEPE = ON (out) DON pin (c) 1 frame (d) 1 frame DONE = ON Register control sequence (a) 0 frame (b) 1 frame (e) 1 frame (f) 0 frame (out) LPS register 00b LCD module stopped 11b LCD module active 00b LCD module stopped Figure 25.4 Power-Supply Control Sequence and States of the LCD Module (2) Power-Supply Control for LCD Panels other than STN or DSTN (in) DON register Start power supply (out) VCPWC pin Start power cutoff (Internal signal) VCPE = OFF (out) Display data, timing signal Undefined Arbitrary (Internal signal) Undefined (out) VEPWC pin VEPE = OFF (out) DON pin DONE = ON Register control sequence (out) LPS register (a) 0 frame (b) 0 frame 00b LCD module stopped (c) 1 frame (d) 1 frame (f) 0 frame (e) 0 frame 00b LCD module stopped 11b LCD module active Figure 25.5 Power-Supply Control Sequence and States of the LCD Module Rev. 5.00 Dec 12, 2005 page 803 of 1034 REJ09B0254-0500 Section 25 LCD Controller (3) Power-Supply Control for TFT Panels (in) DON register Start power supply (out) VCPWC pin (out) Display data, timing signal Start power cutoff VCPE = ON Undefined Arbitrary Undefined (out) VEPWC pin (Internal signal) (out) DON pin (a) 1 frame (f) 1 frame VEPE = ON DONE = OFF Register control sequence (out) LPS register 00b LCD module stopped (b) 6 frame (c) 0 frame 11b (d) 0 frame (e) 1 frame 00b LCD module stopped LCD module active Figure 25.6 Power-Supply Control Sequence and States of the LCD Module (4) Power Supply Control for LCD panels other than TFT (in) DON register Start power supply (out) VCPWC pin (Internal signal) Start power cutoff VCPE = OFF (out) Display data, timing signal Undefined Arbitrary (Internal signal) Undefined (out) VEPWC pin (Internal signal) (out) DON pin Register control sequence (a) 0 frame (b) 0 frame (c) 0 frame 00b LCD module stopped 11b LCD module active (f) 0 frame (e) 0 frame (d) 0 frame 00b LCD module stopped VEPE = OFF DONE = OFF (out) LPS register Figure 25.7 Power-Supply Control Sequence and States of the LCD Module Rev. 5.00 Dec 12, 2005 page 804 of 1034 REJ09B0254-0500 Section 25 LCD Controller Table 25.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates ONX, OFFX Register Value H'F H'0 H'1 H'2 H'3 H'4 H'5 H'6 H'7 H'8 H'9 H'A H'B H'C H'D H'E Frame Rate 120 Hz (-1+1)/120 = 0.00 (ms) (0+1)/120 = 8.33 (ms) (1+1)/120 = 16.67 (ms) (2+1)/120 = 25.00 (ms) (3+1)/120 = 33.33 (ms) (4+1)/120 = 41.67 (ms) (5+1)/120 = 50.00 (ms) (6+1)/120 = 58.33 (ms) (7+1)/120 = 66.67 (ms) (8+1)/120 = 75.00 (ms) (9+1)/120 = 83.33 (ms) (10+1)/120 = 91.67 (ms) (11+1)/120 = 100.00 (ms) (12+1)/120 = 108.33 (ms) (13+1)/120 = 116.67 (ms) (14+1)/120 = 125.00 (ms) 60 Hz (-1+1)/60 = 0.00 (ms) (0+1)/60 = 16.67 (ms) (1+1)/60 = 33.33 (ms) (2+1)/60 = 50.00 (ms) (3+1)/60 = 66.67 (ms) (4+1)/60 = 83.33 (ms) (5+1)/60 = 100.00 (ms) (6+1)/60 = 116.67 (ms) (7+1)/60 = 133.33 (ms) (8+1)/60 = 150.00 (ms) (9+1)/60 = 166.67 (ms) (10+1)/60 = 183.33 (ms) (11+1)/60 = 200.00 (ms) (12+1)/60 = 216.67 (ms) (13+1)/60 = 233.33 (ms) (14+1)/60 = 250.00 (ms) ONA, ONB, ONC, OFFD, OFFE, and OFFF are used to set the power-supply control-sequence periods, in units of frames, from 0 to 15. 1 is subtracted from each register. H'0 to H'E settings select from 1 to15 frames. The setting H'F selects 0 frames. Actual sequence periods depend on the register values and the frame frequency of the display. The following table gives power-supply control-sequence periods for display frame frequencies used by typical LCD modules. When ONB is Set to 6h and Display's Frame Frequency is 120 Hz: The display's frame frequency is 120 Hz. 1 frame period is thus 8.33 (ms) = 1/120 (sec). The power-supply input sequence period is 7 frames because ONB setting is subtracted by 1. As a result, the sequence period is 58.33 (ms) = 8.33 (ms) x 7. Rev. 5.00 Dec 12, 2005 page 805 of 1034 REJ09B0254-0500 Section 25 LCD Controller Table 25.6 LCDC Operating Modes Mode Display on (LCDC active) Display off (LCDC stopped) Register setting: DON = 1 DON = 2 Register setting: DON = 0 DON2 = 0 Function Fixed resolution, the format of the data for display is determined by the number of colors, timing signals are output to the LCD module. Register access is enabled. Fixed resolution, the format of the data for display is determined by the number of colors, timing signals are not output to the LCD module. Table 25.7 LCD Module Power-Supply States (STN, DSTN module) Power Supply for Logic VCPWC Supply Supply Supply Supply Stopped State Display Data, Timing Signal CL2, CL1, FLM, M/DISP, LCD Supply Supply Supply Power Supply for High-Voltage DON Signal Systems VEPWC Supply Supply DON Supply State Control Pin Operating State (Transitional State) (TFT module) State Control Pin Operating State (Transitional State) Stopped State Power Supply for Logic VCPWC Supply Supply Supply Display Data, Timing Signal CL2, CL1, FLM, M/DISP, LCD Supply Supply Power Supply for High-Voltage Systems VEPWC Supply Rev. 5.00 Dec 12, 2005 page 806 of 1034 REJ09B0254-0500 Section 25 LCD Controller The above table shows the states of the power supply, display data, and timing signals for the typical LCD module in its active and stopped states. Some of the supply voltages described may not be necessary, because some modules internally generate the power supply required for highvoltage systems from the logic-level power-supply voltage. Notes on display-off mode (LCDC stopped): If LCD-module power-supply control-sequence processing is in use by the LCDC or the supply of power is cut off while the LCDC is in its display-on mode, normal operation is not guaranteed. In the worst case, the connected LCD module may be damaged. 25.3.7 Operation for Hardware Rotation Operation in hardware-rotation mode is described below. Hardware-rotation mode can be thought of as using a landscape-format LCD panel instead of a portrait-format LCD panel by placing the landscape-format LCD panel as if it were a portrait-format panel. Whether the panel is intended for use in landscape or portrait format is thus no problem. The panel must, however, be within 320 pixels wide. When making settings for hardware rotation, the following five differences from the setting for no hardware rotation must be noted. (The following example is for a display at 8 bpp. At 16 bpp, the amount of memory per dot will be doubled. The image size and register values used for rotation will thus be different.) 1. The image data must be prepared for display in the rotated panel. (If 240 x 320 pixels will be required after rotation, 240 x 320 pixel image data must be prepared.) 2. The register settings for the address of the image data must be changed (LDSARU and LDLAOR). 3. LDLAOR should be power of 2 (when the horizontal width after rotation is 240 pixels, LDLAOR should be set to 256). 4. Graphics software should be set up for the number 3 setting. 5. LDSARU should be changed to represent the address of the data for the lower-left pixel of the image rather than of the data for the upper-left pixel of the image. Rev. 5.00 Dec 12, 2005 page 807 of 1034 REJ09B0254-0500 Section 25 LCD Controller 1) Normal mode LDSARU (start point) Picture image LDSARU + LDLAOR - 1 Picture image Scanning starts from LDSARU. Scanning is done from small address to large address of X coordination. LDSARU + LDLAOR x LDVDLNR - 1(end point) Start point LCD panel Picture image End point For example, the registers have been set up for the display of image data in landscape format (320 x 240), which starts from LDSARU = 0x0c001000, on a 320 x 240 LCD panel. The graphics driver software is complete. Some changes are required to apply hardware rotation and use the panel as a 240 x 320 display. If LDLAOR is 512, the graphics driver software uses this power of 2 as the offset for the calculation of the addresses of Y coordinates in the image data. Before setting ROT to 1, the image data must be redrawn to suit the 240 x 320 LCD panel. LDLAOR will then be 256 because the size has changed and the graphics driver software must be altered accordingly. The point that corresponds to LDSARU moves from the upper left to the lower left of the display, so LDSARU should be changed to 0x0c001000 + 256 * 319. Note: Hardware rotation allows the use of an LCD panel that has been rotated by 90 degrees. The settings in relation to the LCD panel should match the settings for the LCD panel before rotation. Rotation is possible regardless of the drawing processing carried out by the graphics driver software. However, the sizes in the image data and address offset values which are managed by the graphics driver software must be altered. Rev. 5.00 Dec 12, 2005 page 808 of 1034 REJ09B0254-0500 Section 25 LCD Controller 2) Rotation mode LDSARU - LDLAOR x (HDCN x 8 - 2) - 1(end point) Picture image Scanning starts from LDSARU. Scanning is done from large address to small address of Y coordination. LDSARU (start point) Start point LCD panel End point 25.4 Clock and LCD Data Signal Examples 1) STN monochrome 4-bit data bus module Dot CLK CL2 LCD3 LCD2 LCD1 LCD0 LCD5 to 15 Low b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 Figure 25.8 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 809 of 1034 REJ09B0254-0500 Section 25 LCD Controller 2) STN monochrome 8-bit data bus module DOTCLOCK CL2 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 LCD8 to 15 Low Figure 25.9 Clock and LCD Data Signal Example 3) STN color 4-bit data bus module DOTCLOCK CL2 LCD3 LCD2 LCD1 LCD0 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G13 G12 B13 B12 R14 R13 G14 B14 R15 G15 B15 LCD4 to 15 Low Figure 25.10 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 810 of 1034 REJ09B0254-0500 Section 25 LCD Controller 4) STN color 8-bit data bus module DOTCLOCK CL2 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15 LCD8 to 15 Low Figure 25.11 Clock and LCD Data Signal Example 5) STN color 12-bit data bus module DOTCLOCK CL2 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 LCD12 to 15 Low R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15 Figure 25.12 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 811 of 1034 REJ09B0254-0500 Section 25 LCD Controller 6) STN color 16-bit data bus module DOTCLOCK CL2 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15 Figure 25.13 Clock and LCD Data Signal Example 7) DSTN monochrome 8-bit data bus module DOTCLOCK CL2 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 ub0 ub1 ub2 ub3 lb0 lb1 lb2 lb3 ub4 ub5 ub6 ub7 lb4 lb5 lb6 lb7 LCD8 to 15 Low Figure 25.14 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 812 of 1034 REJ09B0254-0500 Section 25 LCD Controller 8) DSTN monochrome 16-bit data bus module DOTCLOCK CL2 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 ub0 ub1 ub2 ub3 ub4 ub5 ub6 ub7 lb0 lb1 lb2 lb3 lb4 lb5 lb6 lb7 Figure 25.15 Clock and LCD Data Signal Example 9) DSTN color 8-bit data bus module DOTCLOCK CL2 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 UR0 UG0 UB0 UR1 LR0 LG0 LB0 LR1 UG1 UB1 UR2 UG2 LG1 LB1 LR2 LG2 UB2 UR3 UG3 UB3 LB2 LR3 LG3 LB3 UR4 UG4 UB4 UR5 LR4 LG4 LB4 LR5 UG5 UB5 UR6 UG6 LG5 LB5 LR6 LG6 UB6 UR7 UG7 UB7 LB6 LR7 LG7 LB7 LCD8 to 15 Low Figure 25.16 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 813 of 1034 REJ09B0254-0500 Section 25 LCD Controller 10) DSTN color 12-bit data bus module DOTCLOCK CL2 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 UR0 UG0 UB0 UR1 UG1 UB1 LR0 LG0 LB0 LR1 LG1 LB1 UR2 UG2 UB2 UR3 UG3 UB3 LR2 LG2 LB2 LR3 LG3 LB3 UR4 UG4 UB4 UR5 UG5 UB5 LR4 LG4 LB4 LR5 LG5 LB5 UR6 UG6 UB6 UR7 UG7 UB7 LR6 LG6 LB6 LR7 LG7 LB7 LCD12 to 15 Low Figure 25.17 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 814 of 1034 REJ09B0254-0500 Section 25 LCD Controller 11) DSTN color 16-bit data bus module DOTCLOCK CL2 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 UR0 UG0 UB0 UR1 UG1 UB1 UR2 UG2 LR0 LG0 LB0 LR1 LG1 LB1 LR2 LG2 UB2 UR3 UG3 UB3 UR4 UG4 UB4 UR5 LB2 LR3 LG3 LB3 LR4 LG4 LB4 LR5 UG5 UB5 UR6 UG6 UB6 UR7 UG7 UB7 LG5 LB5 LR6 LG6 LB6 LR7 LG7 LB7 Figure 25.18 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 815 of 1034 REJ09B0254-0500 Section 25 LCD Controller 12) TFT color 12-bit data bus module DOTCLOCK CL2 LCD12 to 15 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 Low R03 R02 R01 R00 G03 G02 G01 G00 B03 B02 B01 B00 R13 R12 R11 R10 G13 G12 G11 G10 B13 B12 B11 B10 R23 R22 R21 R20 G23 G22 G21 G20 B23 B22 B21 B20 R33 R32 R31 R30 G33 G32 G31 G30 B33 B33 B32 B31 Figure 25.19 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 816 of 1034 REJ09B0254-0500 Section 25 LCD Controller 13) TFT color 16-bit data bus module DOTCLOCK CL2 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 R05 R04 R03 R02 R01 G05 G04 G03 G02 G01 G00 B05 B04 B03 B02 B01 R15 R14 R13 R12 R11 G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 R25 R24 R23 R22 R21 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 R35 R34 R33 R32 R31 G35 G34 G33 G32 G31 G30 B35 B34 B33 B32 B31 Figure 25.20 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 817 of 1034 REJ09B0254-0500 Section 25 LCD Controller 14) 8-bit I/F color 640 x 840 STN-LCD Horizontal wave DOTCLOCK CL2 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 LCD8 to 15 CL1 One horizontal display time (640 x DCLK) Horizontal synchronization position Horizontal retrace time Horizontal synchronization width R0 G0 B0 R1 G1 B1 R2 G2 Low B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 G637 B637 R638 G638 B638 R639 G639 B639 R0 G0 B0 R1 G1 B1 R2 G2 One horizontal time ( ex. 640 + 8 x 3 (:3 character) = 664 DCLK) No vertical retrace CL2 CL1 Valid Valid Valid Valid Valid Valid LCD FLM 1st line data One horizontal time One vertical retrace CL2 CL1 Valid 2nd line data One frame time (480 x CL1) 480th line data 1st line data 2nd line data Next frame time (480 x CL1) LCD FLM Valid Valid Valid Valid 1st line data One horizontal time 2nd line data 480th line data One frame time (481 x CL1) Vertical retrace time (One horizontal time) 1st line data 2nd line data Next frame time (480 x CL1) Figure 25.21 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 818 of 1034 REJ09B0254-0500 Section 25 LCD Controller 15) 16-bit I/F color 640 x 480 TFT-LCD Horizontal wave DOTCLOCK CL2 LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 CL1 DISP One horizontal display time (640 x DCLK) Horizontal synchronization position Horizontal retrace time Horizontal synchronization width B0, 3 B0, 4 B0, 5 B0, 6 B0, 7 G0, 2 G0, 3 G0, 4 G0, 5 G0, 6 G0, 7 R0, 3 R0, 4 R0, 5 R0, 6 R0, 7 B1, 3 B1, 4 B1, 5 B1, 6 B1, 7 G1, 2 G1, 3 G1, 4 G1, 5 G1, 6 G1, 7 R1, 3 R1, 4 R1, 5 R1, 6 R1, 7 B639,3 B639,4 B639,5 B639,6 B639,7 G639,2 G639,3 G639,4 G639,5 G639,6 G639,7 R639,3 R639,4 R639,5 R639,6 R639,7 B0, 3 B0, 4 B0, 5 B0, 6 B0, 7 G0, 2 G0, 3 G0, 4 G0, 5 G0, 6 G0, 7 R0, 3 R0, 4 R0, 5 R0, 6 R0, 7 8DCLK 8DCLK 8DCLK One horizontal time ( ex. 640 + 8 x 3 (:3 character) = 664 DCLK) No vertical retrace CL2 CL1 LCD DISP FLM 1st line data One horizontal time One frame time (480 x CL1) Next frame time (480 x CL1) 2nd line data 480th line data 1st line data 2nd line data Valid Valid Valid Valid Valid Valid Figure 25.22 Clock and LCD Data Signal Example Rev. 5.00 Dec 12, 2005 page 819 of 1034 REJ09B0254-0500 Section 25 LCD Controller 25.5 Usage Notes Note the following points when using the LCDC. The following steps should be performed to prohibit access to the system memory used for LCDC module display (synchronous DRAM in area 3). (1) Confirm that bits LPS1 and LPS0 in the LDPMMR register are set to 1. (2) Clear the DON bit in LDCNTR to 0 (display off mode). (3) Confirm that bits LPS1 and LPS0 in LDPMMR are cleared to 0. (4) Wait the display duration of one frame. The above steps to prohibit access are necessary before entering standby mode or using the LCDC module's standby function. Rev. 5.00 Dec 12, 2005 page 820 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Section 26 Pin Function Controller (PFC) 26.1 Overview The pin function of the SH7727 can be changed by the pin function controller (switch of the I/O port function), PC card controller (described in section 30), USB pin multiplexed controller (described in section 22), and user debugging interface (described in section 31). Figure 26.1 shows the overview of the pin selection function. I/O port External pin (I/O port and pin multiplex) Pin function controller Other functions PC card controller A6PCM PCC/USB selection POUSE USB_TRANS USB pin multiplexed controller External pin (Not I/O port and pin multiplex) Figure 26.1 Overview of the Pin Selection Function Table 26.1 List of Multiplexed Pins Port A A A A A A A A Port Function (Related Module) PTA7 in/out (port) PTA6 in/out (port) PTA5 in/out (port) PTA4 in/out (port) PTA3 in/out (port) PTA2 in/out (port) PTA1 in/out (port) PTA0 in/out (port) Other Function 1 (Related Module) D23 in/out (data bus) D22 in/out (data bus) D21 in/out (data bus) D20 in/out (data bus) D19 in/out (data bus) D18 in/out (data bus) D17 in/out (data bus) D16 in/out (data bus) Other Function 2 (Related Module) Rev. 5.00 Dec 12, 2005 page 821 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Port Function (Related Module) PTB7 in/out (port) PTB6 in/out (port) PTB5 in/out (port) PTB4 in/out (port) PTB3 in/out (port) PTB2 in/out (port) PTB1 in/out (port) PTB0 in/out (port) PTC7 in/out (port)/PINT3 in (INTC) PTC6 in/out (port)/PINT2 in (INTC) PTC5 in/out (port)/PINT1 in (INTC) PTC4 in/out (port)/PINT0 in (INTC) PTC3 in/out (port) PTC2 in/out (port) PTC1 in/out (port) PTC0 in/out (port) PTD7 in/out (port) PTD6 in (port) PTD5 in/out (port) PTD4 in (port) PTD3 in/out (port) PTD2 in/out (port) PTD1 in/out (port) PTD0 in/out (port) Other Function 1 (Related Module) D31 in/out (data bus) D30 in/out (data bus) D29 in/out (data bus) D28 in/out (data bus) D27 in/out (data bus) D26 in/out (data bus) D25 in/out (data bus) D24 in/out (data bus) LCD11 out (LCDC) LCD10 out (LCDC) LCD9 out (LCDC) LCD8 out (LCDC) LCD5 out (LCDC) LCD4 out (LCDC) LCD3 out (LCDC) LCD2 out (LCDC) DON out (LCDC) LCLK in (LCDC)/UCLK (USB) CL1 out (LCDC) DREQ0 in (DMAC) LCD7 out (LCDC) LCD6 out (LCDC) LCD1 out (LCDC) LCD0 out (LCDC) Other Function 2 (Related Module) Port B B B B B B B B C C C C C C C C D D D D D D D D Rev. 5.00 Dec 12, 2005 page 822 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Port Function (Related Module) PTE7 in/out (port) PTE6 in/out (port) PTE5 in/out (port) PTE4 in/out (port) PTE3 in/out (port) PTE2 in/out (port) PTE1 in/out (port) PTE0 in/out (port) PTF7 in (port)/PINT15 in (INTC) PTF6 in (port)/PINT14 in (INTC) PTF5 in (port)/PINT13 in (INTC) PTF4 in (port)/PINT12 in (INTC) PTF3 in (port)/PINT11 in (INTC) PTF2 in (port) PTF1 in (port) PTF0 in (port) PTG7 in (port) PTG5 in (port) PTG4 in (port) PTG3 in (port) PTG2 in (port) PTG1 in (port) PTG0 in (port) PTH7 in/out (port) PTH6 in (port) PTH5 in (port) PTH4 in (port)/IRQ4 in (INTC) Other Function 1 (Related Module) AUDSYNC out (AUD)*3 M/DISP out (LCDC) CE2B out (PCMCIA) CE2A out (PCMCIA) FLM out (LCDC) USB1_pwr_en out (USB) USB2_pwr_en out (USB) TDO out (H-UDI)*2 TRST in (AUD, H-UDI)*3 TMS in (H-UDI)*3 TD1 in (H-UDI)*3 TCK in (H-UDI)*3 Reserved Reserved Reserved Reserved IOIS16 in (PCMCIA) ASEBRKAK out (AUD)*3 -- AUDATA3 out (AUD)*3 AUDATA2 out (AUD) *3 AUDATA1 out (AUD)*3 AUDATA0 out (AUD)*3 CL2 out (LCDC) AUDCK in (AUD)*1 ADTRG in (ADC) IRQ4 in (INTC) PCC0WAIT (PCC) PCC0BVD2 (PCC)*2 PCC0BVD1 (PCC)*2 PCC0CD2 (PCC)*2 PCC0CD1 (PCC)*2 PCCOREG out (PCC)*2 PCCOVS1 in (PCC)*2 PCCOVS2 in (PCC)*2 Other Function 2 (Related Module) PCC0RDY in (PCC)*2 Port E E E E E E E E F F F F F F F F G G G G G G G H H H H H H H H PTH3 in (port)/IRQ3 in IRL3 in (INTC) IRQ3 in IRL3 in (INTC) PTH2 in (port)/IRQ2 in IRL2 in (INTC) IRQ2 in IRL2 in (INTC) PTH1 in (port)/IRQ1 in IRL1 in (INTC) IRQ1 in IRL1 in (INTC) PTH0 in (port)/IRQ0 in IRL0 in (INTC) IRQ0 in IRL0 in (INTC) Rev. 5.00 Dec 12, 2005 page 823 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Port Function (Related Module) PTJ7 in/out (port) PTJ6 in/out (port) PTJ5 in/out (port) PTJ4 in/out (port) PTJ3 in/out (port) PTJ2 in/out (port) PTJ1 in/out (port) PTJ0 in/out (port) PTK7 in/out (port) PTK6 in/out (port) PTK5 in/out (port) PTK4 in/out (port) PTK3 in/out (port) PTK2 in/out (port) PTK1 in/out (port) PTK0 in/out (port) PTL7 in (port) PTL6 in (port) PTL5 in (port) PTL4 in (port) PTL3 in (port) PTL2 in (port) PTM7 in (port)/PINT7 in (INTC) PTM6 in (port)/PINT6 in (INTC) PTM5 in (port)/PINT5 in (INTC) PTM4 in (port)/PINT4 in (INTC) PTM3 in (port)/ PINT10 in (INTC) PTM2 in (port)/PINT9 in (INTC) PTM1 in (port)/PINT8 in (INTC) PTM0 in (port) Other Function 1 (Related Module) STATUS1 out (CPG) STATUS0 out (CPG) Reserved Reserved Reserved CAS out (BSC) Reserved RAS3 out (BSC) WE3 out (BSC)/DQMUU out (BSC)/ICIOWR out (BSC) WE2 out (BSC)/DQMUL out (BSC)/ICIORD out (BSC) CKE out (BSC) BS out (BSC) CS5 out (BSC)/CE1A out (BSC) CS4 out (BSC) AFE_RLYCNT out (AFE) AFE_HC1 out (AFE) AN7 in (ADC)/DA0 out (DAC) AN6 in (ADC)/DA1 out (DAC) AN5 in (ADC) AN4 in (ADC) AN3 in (ADC) AN2 in (ADC) AFE_FS in (AFE) AFE_RXIN in (AFE) AFE_TXOUT out (AFE) AFE_RDET in (AFE) LCD15 out (LCDC) LCD14 out (LCDC) LCD13 out (LCDC) LCD12 out (LCDC) USB1d_RCV in (USB)*2 USB1d_SPEED out (USB)*2 USB1d_TXSE0 out (USB)*2 USB1d_DMNS in (USB)*2 USB1d_DPLS in (USB)*2 Reserved Other Function 2 (Related Module) Port J J J J J J J J K K K K K K K K L L L L L L M M M M M M M M Rev. 5.00 Dec 12, 2005 page 824 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Port Function (Related Module) SCPT7 in (port)/IRQ5 in (INTC) SCPT6 in/out (port) SCPT5 in/out (port) SCPT4 in (port)*1 SCPT4 out (port)*1 SCPT SCPT SCPT3 in/out (port) SCPT2 in (port) *1 SCPT2 out (port)*1 SCPT SCPT SCPT1 in/out (port) SCPT0 in (port)*1 SCPT0 out (port)*1 -- -- -- -- -- -- -- -- -- -- Other Function 1 (Related Module) CTS2 in (SCIF)/IRQ5 in (INTC) SIOFSYNC in/out (SIOF) SCK_SIO in/out (SIOF) RxD2 in (SCIF) TxD2 out (SCIF) SIOMCLK in (SIOF) RxD_SIO in (SIOF) TxD_SIO out (SIOF) SCK0 in/out (SCI) RxD0 in (SCI) TxD0 out (SCI) AFE_SCLK in (AFE) Reserved RTS2 out (SCIF) DRAK0 out (DMAC) DACK0 out (DMAC) USB1d_TXDPLS out (USB) USB1d_SUSPEND out (USB) USB1d_TXENL out (USB) PCC0RESET out (PCC) PCC0DRV out (PCC) Other Function 2 (Related Module) Port SCPT SCPT SCPT SCPT Notes: 1. SCPT0, SCPT2, and SCPT4 are different input pins and output pins, but the accessed data register is the same. 2. For pins with which PCC or USB pin multiplex controller related pins are multiplexed, other functions (in normal operation) and other functions (with special settings) are switched according to the setting of the P0USE bit in PCC, the A6PCM bit in BSC, and a USB pin multiplex controller register setting. To enable a PCC pin, set A6PCM and P0USE to use of a PC card. Switching to the PCC pin is performed automatically according to the value of the two bits. For I/O ports with which PCC or USB pin multiplex controller related pins are multiplexed, do not change the P0USE bit in PCC, the A6PCM bit in BSC, or the USB pin multiplex controller register, after switching to the other function. 3. Enabled when ASEMD0 is low. Rev. 5.00 Dec 12, 2005 page 825 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.2 Register Configuration Table 26.2 summarizes the registers of the pin function controller (PFC). Table 26.2 Pin Function Controller Registers Name Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port J control register Port K control register Port L control register SC port control register Port M control register Abbreviation PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR PLCR SCPCR PMCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'AAAA H'AAAA Address Access Size H'04000100 16 (H'A4000100)* H'04000102 16 (H'A4000102)* H'04000104 16 (H'A4000104)* 16 H'04000106 (H'A4000106)* H'AAAA/H'2AA8 H'04000108 16 (H'A4000108)* 16 H'AAAA/H'00AA H'0400010A (H'A400010A)* H'AAAA/H'A200 H'0400010C 16 (H'A400010C)* H'AAAA/H'8AAA H'0400010E 16 (H'A400010E)* H'0000 H'0000 H'0000 H'8008 H'AAAA H'04000110 16 (H'A4000110)* H'04000112 16 (H'A4000112)* 16 H'04000114 (H'A4000114)* H'04000116 16 (H'A4000116)* H'04000118 16 (H'A4000118)* Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered. See section 31, User-Debugging Interface (H-UDI), for more information on the H-UDI. The initial value of the port E, F, G, and H control registers depends on the state of the ASEMD0 pin. * When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 826 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3 26.3.1 Register Descriptions Port A Control Register (PACR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA7 PA7 PA6 PA6 PA5 PA5 PA4 PA4 PA3 PA3 PA2 PA2 PA1 PA1 PA0 PA0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port A Control Register (PACR) is a 16-bit read/write register that selects the pin functions. PACR is initialized to H'0000 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PA7 Mode 1, 0 (PA7MD1, PA7MD0) Bits 13, 12: PA6 Mode 1, 0 (PA6MD1, PA6MD0) Bits 11, 10: PA5 Mode 1, 0 (PA5MD1, PA5MD0) Bits 9, 8: PA4 Mode 1, 0 (PA4MD1, PA4MD0) Bits 7, 6: PA3 Mode 1, 0 (PA3MD1, PA3MD0) Bits 5, 4: PA2 Mode 1, 0 (PA2MD1, PA2MD0) Bits 3, 2: PA1 Mode 1, 0 (PA1MD1, PA1MD0) Bits 1, 0: PA0 Mode 1, 0 (PA0MD1, PA0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PAnMD1 0 0 1 1 Bit 2n PAnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00 Dec 12, 2005 page 827 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.2 Port B Control Register (PBCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB7 PB7 PB6 PB6 PB5 PB5 PB4 PB4 PB3 PB3 PB2 PB2 PB1 PB1 PB0 PB0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port B Control Register (PBCR) is a 16-bit read/write register that selects the pin functions. PBCR is initialized to H'0000 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PB7 Mode 1, 0 (PB7MD1, PB7MD0) Bits 13, 12: PB6 Mode 1, 0 (PB6MD1, PB6MD0) Bits 11, 10: PB5 Mode 1, 0 (PB5MD1, PB5MD0) Bits 9, 8: PB4 Mode 1, 0 (PB4MD1, PB4MD0) Bits 7, 6: PB3 Mode 1, 0 (PB3MD1, PB3MD0) Bits 5, 4: PB2 Mode 1, 0 (PB2MD1, PB2MD0) Bits 3, 2: PB1 Mode 1, 0 (PB1MD1, PB1MD0) Bits 1, 0: PB0 Mode 1, 0 (PB0MD1, PB0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PBnMD1 0 0 1 1 Bit 2n PBnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00 Dec 12, 2005 page 828 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.3 Port C Control Register (PCCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC7 PC7 PC6 PC6 PC5 PC5 PC4 PC4 PC3 PC3 PC2 PC2 PC1 PC1 PC0 PC0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port C Control Register (PCCR) is a 16-bit read/write register that selects the pin functions. PCCR is initialized to H'AAAA by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PC7 Mode 1, 0 (PC7MD1, PC7MD0) Bits 13, 12: PB6 Mode 1, 0 (PC6MD1, PC6MD0) Bits 11, 10: PC5 Mode 1, 0 (PC5MD1, PC5MD0) Bits 9, 8: PC4 Mode 1, 0 (PC4MD1, PC4MD0) Bits 7, 6: PC3 Mode 1, 0 (PC3MD1, PC3MD0) Bits 5, 4: PC2 Mode 1, 0 (PC2MD1, PC2MD0) Bits 3, 2: PC1 Mode 1, 0 (PC1MD1, PC1MD0) Bits 1, 0: PC0 Mode 1, 0 (PC0MD1, PC0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PCnMD1 0 0 1 1 Bit 2n PCnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00 Dec 12, 2005 page 829 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.4 Port D Control Register (PDCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD7 PD7 PD6 PD6 PD5 PD5 PD4 PD4 PD3 PD3 PD2 PD2 PD1 PD1 PD0 PD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port D Control Register (PDCR) is a 16-bit read/write register that selects the pin functions. PDCR is initialized to H'AAAA by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PD7 Mode 1, 0 (PD7MD1, PD7MD0) Bits 13, 12: PD6 Mode 1, 0 (PD6MD1, PD6MD0) Bits 11, 10: PD5 Mode 1, 0 (PD5MD1, PD5MD0) Bits 9, 8: PD4 Mode 1, 0 (PD4MD1, PD4MD0) Bits 7, 6: PD3 Mode 1, 0 (PD3MD1, PD3MD0) Bits 5, 4: PD2 Mode 1, 0 (PD2MD1, PD2MD0) Bits 3, 2: PD1 Mode 1, 0 (PD1MD1, PD1MD0) Bits 1, 0: PD0 Mode 1, 0 (PD0MD1, PD0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PDnMD1 0 0 1 1 Bit 2n PDnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output (n = value other than 4 or 6), reserved (n = 4 or 6) Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00 Dec 12, 2005 page 830 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.5 Port E Control Register (PECR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE7 PE7 PE6 PE6 PE5 PE5 PE4 PE4 PE3 PE3 PE2 PE2 PE1 PE1 PE0 PE0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1/0 0 1 0 1 0 1 0 1 0 1 0 1 0 1/0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port E Control Register (PECR) is a 16-bit read/write register that selects the pin functions. PECR is initialized to H'AAAA (ASEMD0 = 1) or H'2AA8 (ASEMD0 = 0) by power-on resets; however, it is not initialized by manual resets, in software standby mode, or in sleep mode. Bits 15, 14: PE7 Mode 1, 0 (PE7MD1, PE7MD0) Bits 13, 12: PE6 Mode 1, 0 (PE6MD1, PE6MD0) Bits 11, 10: PE5 Mode 1, 0 (PE5MD1, PE5MD0) Bits 9, 8: PE4 Mode 1, 0 (PE4MD1, PE4MD0) Bits 7, 6: PE3 Mode 1, 0 (PE3MD1, PE3MD0) Bits 5, 4: PE2 Mode 1, 0 (PE2MD1, PE2MD0) Bits 3, 2: PE1 Mode 1, 0 (PE1MD1, PE1MD0) Bits 1, 0: PE0 Mode 1, 0 (PE0MD1, PE0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PEnMD1 0 0 1 1 Bit 2n PEnMD0 0 1 0 1 Pin Function Reserved (n = 0, 7) (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0, 7) (Initial value) ASEMD0 = 1 (Initial value) ASEMD0 = 0 If ASEMD0 = 0, port function cannot be selected with any PE7MD1, PE7MD0 value. Bit (2n + 1) PEnMD1 0 0 1 1 Bit 2n PEnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) (n = 1 to 6) Rev. 5.00 Dec 12, 2005 page 831 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.6 Port F Control Register (PFCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF7 PF7 PF6 PF6 PF5 PF5 PF4 PF4 PF3 PF3 PF2 PF2 PF1 PF1 PF0 PF0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1/0 0 1/0 0 1/0 0 1/0 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port F Control Register (PFCR) is a 16-bit read/write register that selects the pin functions. PFCR is initialized to H'AAAA (ASEMD0 = 1) or H'00AA (ASEMD0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PF7 Mode 1, 0 (PF7MD1, PF7MD0) Bits 13, 12: PF6 Mode 1, 0 (PF6MD1, PF6MD0) Bits 11, 10: PF5 Mode 1, 0 (PF5MD1, PF5MD0) Bits 9, 8: PF4 Mode 1, 0 (PF4MD1, PF4MD0) Bits 7, 6: PF3 Mode 1, 0 (PF3MD1, PF3MD0) Bits 5, 4: PF2 Mode 1, 0 (PF2MD1, PF2MD0) Bits 3, 2: PF1 Mode 1, 0 (PF1MD1, PF1MD0) Bits 1, 0: PF0 Mode 1, 0 (PF0MD1, PF0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PFnMD1 0 0 1 1 Bit 2n PFnMD0 0 1 0 1 Pin Function Reserved (see table 26.1) Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 4 to7) Bit (2n + 1) PFnMD1 0 0 1 1 Bit 2n PFnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 3) (Initial value) (Initial value) ASEMD0 = 1 (Initial value) ASEMD0 = 0 Rev. 5.00 Dec 12, 2005 page 832 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.7 Port G Control Register (PGCR) For details on using versions previous to the SH7727B please refer to appendix F, Specifications for Using Port G Control Register (PGCR) with Versions Previous to the SH7727B. Bit: 15 14 13 1 R 12 0 R 11 10 9 8 7 6 5 4 3 2 1 0 PG7 PG7 MD1 MD0 Initial value: 1 0 PG5 PG5 PG4 PG4 PG3 PG3 PG2 PG2 PG1 PG1 PG0 PG0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 1/0 0 1 0 1/0 0 1/0 0 1/0 0 1/0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port G Control Register (PGCR) is a 16-bit read/write register that selects the pin functions. PGCR is initialized to H'AAAA (ASEMD0 = 1) or H'A200 (ASEMD0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PG7 Mode 1, 0 (PG7MD1, PG7MD0) Bits 13, 12: Reserved Bits 11, 10: PG5 Mode 1, 0 (PG5MD1, PG5MD0) Bits 9, 8: PG4 Mode 1, 0 (PG4MD1, PG4MD0) Bits 7, 6: PG3 Mode 1, 0 (PG3MD1, PG3MD0) Bits 5, 4: PG2 Mode 1, 0 (PG2MD1, PG2MD0) Bits 3, 2: PG1 Mode 1, 0 (PG1MD1, PG1MD0) Bits 1, 0: PG0 Mode 1, 0 (PG0MD1, PG0MD0) These bits select the pin functions and the input pullup MOS control. Rev. 5.00 Dec 12, 2005 page 833 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Bit (2n + 1) PGnMD1 0 0 1 1 Bit (2n + 1) PGnMD1 0 0 1 1 Bit 2n PGnMD0 0 1 0 1 Bit 2n PGnMD0 0 1 0 1 Pin Function Other function (n = 7) (see table 26.1), Reserved (n = 4) Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 4, 7) (Initial value) Pin Function Other function (n = 1, 2, 3, 5) (see table 26.1) (Initial value) ASEMD0 = 0 Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 3, 5) (Initial value) ASEMD0 = 1 Rev. 5.00 Dec 12, 2005 page 834 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.8 Port H Control Register (PHCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PH7 PH7 PH6 PH6 PH5 PH5 PH4 PH4 PH3 PH3 PH2 PH2 PH1 PH1 PH0 PH0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1/0 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port H Control Register (PHCR) is a 16-bit read/write register that selects the pin functions. PHCR is initialized to H'AAAAA(ASEMD0 = 1) or H'8AAA (ASEMD0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PH7 Mode 1, 0 (PH7MD1, PH7MD0) Bits 13, 12: PH6 Mode 1, 0 (PH6MD1, PH6MD0) Bits 11, 10: PH5 Mode 1, 0 (PH5MD1, PH5MD0) Bits 9, 8: PH4 Mode 1, 0 (PH4MD1, PH4MD0) Bits 7, 6: PH3 Mode 1, 0 (PH3MD1, PH3MD0) Bits 5, 4: PH2 Mode 1, 0 (PH2MD1, PH2MD0) Bits 3, 2: PH1 Mode 1, 0 (PH1MD1, PH1MD0) Bits 1, 0: PH0 Mode 1, 0 (PH0MD1, PH0MD0) These bits select the pin functions and the input pullup MOS control. Bit 15 PH7MD1 0 0 1 1 Bit 13 PH6MD1 0 0 1 1 Bit 14 PH7MD0 0 1 0 1 Bit 12 PH6MD0 0 1 0 1 Pin Function Other function (see table 26.1) Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) ASEMD0 = 1 (Initial value) ASEMD0 = 0 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) Rev. 5.00 Dec 12, 2005 page 835 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Bit (2n + 1) PHnMD1 0 0 1 1 Bit 2n PHnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 5) (Initial value) 26.3.9 Port J Control Register (PJCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ7 PJ7 PJ6 PJ6 PJ5 PJ5 PJ4 PJ4 PJ3 PJ3 PJ2 PJ2 PJ1 PJ1 PJ0 PJ0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port J Control Register (PJCR) is a 16-bit read/write register that selects the pin functions. PJCR is initialized to H'0000 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PJ7 Mode 1, 0 (PJ7MD1, PJ7MD0) Bits 13, 12: PJ6 Mode 1, 0 (PJ6MD1, PJ6MD0) Bits 11, 10: PJ5 Mode 1, 0 (PJ5MD1, PJ5MD0) Bits 9, 8: PJ4 Mode 1, 0 (PJ4MD1, PJ4MD0) Bits 7, 6: PJ3 Mode 1, 0 (PJ3MD1, PJ3MD0) Bits 5, 4: PJ2 Mode 1, 0 (PJ2MD1, PJ2MD0) Bits 3, 2: PJ1 Mode 1, 0 (PJ1MD1, PJ1MD0) Bits 1, 0: PJ0 Mode 1, 0 (PJ0MD1, PJ0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PJnMD1 0 0 1 1 Bit 2n PJnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00 Dec 12, 2005 page 836 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.10 Port K Control Register (PKCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PK7 PK7 PK6 PK6 PK5 PK5 PK4 PK4 PK3 PK3 PK2 PK2 PK1 PK1 PK0 PK0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port K Control Register (PKCR) is a 16-bit read/write register that selects the pin functions. PKCR is initialized to H'0000 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PK7 Mode 1, 0 (PK7MD1, PK7MD0) Bits 13, 12: PK6 Mode 1, 0 (PK6MD1, PK6MD0) Bits 11, 10: PK5 Mode 1, 0 (PK5MD1, PK5MD0) Bits 9, 8: PK4 Mode 1, 0 (PK4MD1, PK4MD0) Bits 7, 6: PK3 Mode 1, 0 (PK3MD1, PK3MD0) Bits 5, 4: PK2 Mode 1, 0 (PK2MD1, PK2MD0) Bits 3, 2: PK1 Mode 1, 0 (PK1MD1, PK1MD0) Bits 1, 0: PK0 Mode 1, 0 (PK0MD1, PK0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PKnMD1 0 0 1 1 Bit 2n PKnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00 Dec 12, 2005 page 837 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.11 Port L Control Register (PLCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 0 R 2 0 R 1 0 R 0 0 R PL7 PL7 PL6 PL6 PL5 PL5 PL4 PL4 PL3 PL3 PL2 PL2 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port L Control Register (PLCR) is a 16-bit read/write register that selects the pin functions. PLCR is initialized to H'0000 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PL7 Mode 1, 0 (PL7MD1, PL7MD0) Bits 13, 12: PL6 Mode 1, 0 (PL6MD1, PL6MD0) Bits 11, 10: PL5 Mode 1, 0 (PL5MD1, PL5MD0) Bits 9, 8: PL4 Mode 1, 0 (PL4MD1, PL4MD0) Bits 7, 6: PL3 Mode 1, 0 (PL3MD1, PL3MD0) Bits 5, 4: PL2 Mode 1, 0 (PL2MD1, PL2MD0) Bits 3 to 0: Reserved These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PLnMD1 0 0 1 Bit 2n PLnMD0 0 1 Pin Function Other function (see table 26.1) Reserved Port input (n = 2 to 7) (Initial value) When the DA0 and DA1 pins are used as the D/A converter outputs or when PTL7 and PTL6 are used as the other function states, PLCR should remain at its initial value. Rev. 5.00 Dec 12, 2005 page 838 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.12 Port M Control Register (PMCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PM7 PM7 PM6 PM6 PM5 PM5 PM4 PM4 PM3 PM3 PM2 PM2 PM1 PM1 PM0 P0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port M Control Register (PMCR) is a 16-bit read/write register that selects the pin functions. PMCR is initialized to H'AAAA by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bits 15, 14: PM7 Mode 1, 0 (PM7MD1, PM7MD0) Bits 13, 12: PM6 Mode 1, 0 (PM6MD1, PM6MD0) Bits 11, 10: PM5 Mode 1, 0 (PM5MD1, PM5MD0) Bits 9, 8: PM4 Mode 1, 0 (PM4MD1, PM4MD0) Bits 7, 6: PM3 Mode 1, 0 (PM3MD1, PM3MD0) Bits 5, 4: PM2 Mode 1, 0 (PM2MD1, PM2MD0) Bits 3, 2: PM1 Mode 1, 0 (PM1MD1, PM1MD0) Bits 1, 0: PM0 Mode 1, 0 (PM0MD1, PM0MD0) These bits select the pin functions and the input pullup MOS control. Bit (2n + 1) PMnMD1 0 0 1 1 Bit 2n PMnMD0 0 1 0 1 Pin Function Other function (see table 26.1) Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (n = 0 to 7) (Initial value) Rev. 5.00 Dec 12, 2005 page 839 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) 26.3.13 SC Port Control Register (SCPCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 Initial value: 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SC Port Control Register (SCPCR) is a 16-bit read/write register that selects the pin functions. The setting of SCPCR is valid only when the transmit/receive operation is disabled in the setting of the SCSCR register. SCPCR is initialized to H'8008 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. When the TE bit in SCSCR is set to 1, the other function output state has a higher priority than the SCPCR setting of the TxD[2:0] pin. When the RE bit in SCSCR is set to 1, the input state has a higher priority than the SCPCR setting of the RxD[2:0] pin. Bits 15, 14--SCP7 Mode 1, 0 (SCP7MD1, SCP7MD0): These bits select the pin functions and the input pullup MOS control. Bit 15 SCP7MD1 0 0 1 1 Bit 14 SCP7MD0 0 1 0 1 Pin Function Other function (see table 26.1) Reserved Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) Bits 13, 12--SCP6 Mode 1, 0 (SCP6MD1, SCP6MD0): These bits select the pin functions and the input pullup MOS control. Bit 13 SCP6MD1 0 0 1 1 Bit 12 SCP6MD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) Rev. 5.00 Dec 12, 2005 page 840 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Bits 11, 10--SCP5 Mode 1, 0 (SCP5MD1, SCP5MD0): These bits select the pin functions and the input pullup MOS control. Bit 11 SCP5MD1 0 0 1 1 Bit 10 SCP5MD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) Bits 9, 8--SCP4 Mode 1, 0 (SCP4MD1, SCP4MD0): These bits select the pin functions and the input pullup MOS control. Bit 9 SCP4MD1 0 0 1 1 Bit 8 SCP4MD0 0 1 0 1 Pin Function Transmit data output 2 (TxD2) Receive data input 2 (RxD2) General output (SCPT[4] output pin) Receive data input 2 (RxD2) SCPT[4] input pin pullup (input pin) Transmit data output 2 (TxD2) General input (SCPT[4] input pin) Transmit data output 2 (TxD2) (Initial value) Note: There is no combination of simultaneous I/O of SCPT[4] because one bit (SCP4DT) is accessed using two pins of TxD2 and RxD2. When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD2 pin is in the output state. When the TE bit is cleared to 0, the TxD2 pin is in the highimpedance state. Rev. 5.00 Dec 12, 2005 page 841 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Bits 7, 6--SCP3 Mode 1, 0 (SCP3MD1, SCP3MD0): These bits select the pin functions and the input pullup MOS control. Bit 7 SCP3MD1 0 0 1 1 Bit 6 SCP3MD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) Bits 5, 4--SCP2 Mode 1, 0 (SCP2MD1, SCP2MD0): These bits select the pin functions and the input pullup MOS control. Bit 5 SCP2MD1 0 0 1 1 Bit 4 SCP2MD0 0 1 0 1 Pin Function Transmit data output 1 (TxD_SIO) Receive data input 1 (RxD_SIO) General output (SCPT[2] output pin) Receive data input 1 (RxD_SIO) SCPT[2] input pin pullup (input pin) Transmit data output 1 (TxD_SIO) General input (SCPT[2] input pin) Transmit data output 1 (TxD_SIO) (Initial value) Note: There is no combination of simultaneous I/O of SCPT[2] because one bit (SCP2DT) is accessed using two pins of TxD_SIO and RxD_SIO. When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD_SIO pin is in the output state. When the TE bit is cleared to 0, the TxD_SIO pin is in the high-impedance state. Rev. 5.00 Dec 12, 2005 page 842 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Bits 3, 2--SCP1 Mode 1, 0 (SCP1MD1, SCP1MD0): These bits select the pin functions and the input pullup MOS control. Bit 3 SCP1MD1 0 0 1 1 Bit 2 SCP1MD0 0 1 0 1 Pin Function Other function (see table 26.1) Port output Port input (Pullup MOS: on) Port input (Pullup MOS: off) (Initial value) Bits 1, 0--SCP0 Mode 1, 0 (SCP0MD1, SCP0MD0): These bits select the pin functions and the input pullup MOS control. Bit 1 SCP0MD1 0 0 1 1 Bit 0 SCP0MD0 0 1 0 1 Pin Function Transmit data output 0 (TxD0) Receive data input 0 (RxD0) General output (SCPT[0] output pin) Receive data input 0 (RxD0) SCPT[0] input pin pullup (input pin) Transmit data output 0 (TxD0) General input (SCPT[0] input pin) Transmit data output 0 (TxD0) (Initial value) Note: There is no combination of simultaneous I/O of SCPT[0] because one bit (SCP0DT) is accessed using two pins of TxD0 and RxD0. When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD0 pin is in the output state. When the TE bit is cleared to 0, the TxD0 pin is in the highimpedance state. Rev. 5.00 Dec 12, 2005 page 843 of 1034 REJ09B0254-0500 Section 26 Pin Function Controller (PFC) Rev. 5.00 Dec 12, 2005 page 844 of 1034 REJ09B0254-0500 Section 27 I/O Ports Section 27 I/O Ports 27.1 Overview This LSI has thirteen 8-bit ports (ports A to M and SC). All port pins are multiplexed with other pin functions (Pin Function Controller (PFC) selects the pin functions and pullup MOS control). Each port has a data register which stores data for the pins. Rev. 5.00 Dec 12, 2005 page 845 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.2 Register Configuration Table 27.1 summarizes the registers of the pin function controller. Table 27.1 Pin Function Controller Registers Name Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port J data register Port K data register Port L data register Abbreviation PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR PLDR R/W R/W R/W R/W R/W or R R/W R R R/W or R R/W R/W R R/W or R R Initial Value H'00 H'00 H'00 B'0*0*0000 H'00 H'** H'** B'0******* H'00 H'00 H'** B'*0000000 B'******** Address H'04000120 1 (H'A4000120)* H'04000122 1 (H'A4000122)* H'04000124 1 (H'A4000124)* H'04000126 1 (H'A4000126)* H'04000128 1 (H'A4000128)* H'0400012A 1 (H'A400012A)* H'0400012C 1 (H'A400012C)* H'0400012E 1 (H'A400012E)* H'04000130 1 (H'A4000130)* H'04000132 (H'A4000132)* H'04000134 1 (H'A4000134)* Access Size 8 8 8 8 8 8 8 8 8 8 8 SC port data register SCPDR Port M data register PMDR H'04000136 8 1 (H'A4000136)* H'04000138 8 1 (H'A4000138)* Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. * Means no value. 1. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 846 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.3 Ports A to C, E, J, K Each pin has an input pullup MOS, which is controlled by Port A to C, E, J, K Control Register in PFC. 27.3.1 Ports A to C, E, J, K Data Rgister (PADR, PBDR, PCDR, PEDR, PJDR, PKDR) Bit: Initial value: R/W: 7 Px7DT 0 R/W 6 Px6DT 0 R/W 5 Px5DT 0 R/W 4 Px4DT 0 R/W 3 Px3DT 0 R/W 2 Px2DT 0 R/W 1 Px1DT 0 R/W 0 Px0DT 0 R/W Ports A to C, E, J, K Data Register (PADR, PBDR, PCDR, PEDR, PJDR, PKDR) is an 8-bit read/write register that stores data for pins PTx7 to PTx0. Px7DT to Px0DT bit corresponds to PTx7 to PTx0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PADR, PBDR, PCDR, PEDR, PJDR and PKDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 27.2 shows the function of PADR, PBDR, PCDR, PEDR, PJDR, PKDR. PADR, PBDR, PCDR, PEDR, PJDR, PKDR is initialized to H'00 by a power-on reset. When ASEMD0 is equal to 1, after PDCR and PEDR are initialized to H'00, the general input port function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are fetched. It retains its previous value in standby mode and sleep mode, and by a manual reset. Table 27.2 Read/Write Operation of the Ports A to C, E, J, K Data Register PxnMD1 0 PxnMD0 0 1 1 0 1 Pin State Read Write Value is written to PxDR, but does not affect pin state. Write value is output from pin. Value is written to PxDR, but does not affect pin state. Value is written to PxDR, but does not affect pin state. (n = 0 to 7) (x = A to C, E, J, K) Other function PxDR value Output Input (Pullup MOS: on) Input (Pullup MOS: off) PxDR value Pin state Pin state Rev. 5.00 Dec 12, 2005 page 847 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.4 Port D Each pin has an input pullup MOS, which is controlled by Port D Control Register (PDCR) in PFC. 27.4.1 Port D Data Register (PDDR) Bit: Initial value: R/W: Note: * Undefined 7 PD7DT 0 R/W 6 PD6DT * R 5 PD5DT 0 R/W 4 PD4DT * R 3 PD3DT 0 R/W 2 PD2DT 0 R/W 1 PD1DT 0 R/W 0 PD0DT 0 R/W Port D Data Register (PDDR) is a 6-bit read/write and 2-bit read register that stores data for pins PTD7 to PTD0. PD7DT to PD0DT bit corresponds to PTD7 to PTD0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PDDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 27.3 shows the function of PDDR. PDDR is initialized to B'0*0*0000 by a power-on reset. After initialization, the general input port function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are fetched. It retains its previous value in standby mode and sleep mode, and by a manual reset. Rev. 5.00 Dec 12, 2005 page 848 of 1034 REJ09B0254-0500 Section 27 I/O Ports Table 27.3 Read/Write Operation of the Port D Data Register (PDDR) Read Write Value is written to PDDR, but does not affect pin state. Write value is output from pin. Value is written to PDDR, but does not affect pin state. Value is written to PDDR, but does not affect pin state. (n = 0 to 3, 5, 7) PDnMD1 PDnMD0 Pin State 0 0 1 1 0 1 Other function PDDR value Output Input (Pullup MOS: on) Input (Pullup MOS: off) PDDR value Pin state Pin state PDnMD1 PDnMD0 Pin State 0 1 0 1 0 1 Reserved* Input (Pullup MOS: on) Input (Pullup MOS: off) Read Pin state Pin state Write Ignored (no affect on pin state) Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 4, 6) Other function H'00 Note: * Operation cannot be guaranteed when this bit it set to "reserved." Rev. 5.00 Dec 12, 2005 page 849 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.5 Ports F, M Each pin has an input pullup MOS, which is controlled by Ports F, M Control Register (PFDR, PMDR) in PFC. 27.5.1 Ports F, M Data Register (PFDR, PMDR) Bit: Initial value: R/W: Note: * Undefined 7 Px7DT * R 6 Px6DT * R 5 Px5DT * R 4 Px4DT * R 3 Px3DT * R 2 Px2DT * R 1 Px1DT * R 0 Px0DT * R Ports F, M Data Register (PFDR, PMDR) is an 8-bit read register that stores data for pins PTx7 to PTx0. Px7DT to Px0DT bit corresponds to PTx7 to PTx0 pin. When the pin function is general input port, if the port is read, the corresponding pin level is read. Table 27.4 shows the function of PFDR and PMDR. PFDR and PMDR are initialized by a power-on reset. After initialization, the general input port function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are read. Table 27.4 Read/Write Operation of the Ports F, M Data Register (PFDR, PMDR) PxnMD1 0 1 PxnMD0 0 1 0 1 Pin State Reserved* Input (Pullup MOS on) Input (Pullup MOS off) Read Pin state Pin state Write Ignored (no affect on pin state) Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 0 to 7) (x = F, M) Other function H'00 Note: * Operation cannot be guaranteed when this bit it set to "reserved." Rev. 5.00 Dec 12, 2005 page 850 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.6 Port G Each pin has an input pullup MOS, which is controlled by Port G Control Register (PGCR) in PFC. 27.6.1 Port G Data Register (PGDR) Bit: Initial value: R/W: Note: * Undefined 7 PG7DT * R 6 -- * R 5 PG5DT * R 4 PG4DT * R 3 PG3DT * R 2 PG2DT * R 1 PG1DT * R 0 PG0DT * R Port G Data Register (PGDR) is an 8-bit read register that stores data for pins PTG7 and PTG5 to PTG0. PG7DT and PTG5DT to PG0DT bit corresponds to PTG7 and PTG5 to PTG0 pin. When the pin function is general input port, if the port is read, the corresponding pin level is read. Table 27.5 shows the function of PGDR. When ASEMD0 is equal to 1, after PGDR is initialized by a power-on reset, the general input port function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are fetched. Table 27.5 Read/Write Operation of the Port G Data Register (PGDR) PGnMD1 PGnMD0 Pin State 0 1 0 1 0 1 Reserved* Input (Pullup MOS: on) Input (Pullup MOS: off) Read Pin state Pin state Write Ignored (no affect on pin state) Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 0 to 5, 7) Other function H'00 Note: * Operation cannot be guaranteed when this bit it set to "reserved." Rev. 5.00 Dec 12, 2005 page 851 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.7 Port H Each pin has an input pullup MOS, which is controlled by Port H Control Register (PHCR) in PFC. 27.7.1 Port H Data Register (PHDR) Bit: Initial value: R/W: Note: * Undefined 7 PH7DT 0 R/W 6 PH6DT * R 5 PH5DT * R 4 PH4DT * R 3 PH3DT * R 2 PH2DT * R 1 PH1DT * R 0 PH0DT * R Port H Data Register (PHDR) is a 1-bit read/write and 7-bit read register that stores data for pins PTH7 to PTH0. PH7DT to PH0DT bit corresponds to PTH7 to PTH0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PHDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 27.6 shows the function of PHDR. When ASEMD0 is equal to 1, after PHDR is initialized to B'0******* by a power-on reset, the general input port function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are fetched. It retains its previous value in standby mode and sleep mode, and by a manual reset. Rev. 5.00 Dec 12, 2005 page 852 of 1034 REJ09B0254-0500 Section 27 I/O Ports Table 27.6 Read/Write Operation of the Port H Data Register (PHDR) Read Write Value is written to PHDR, but does not affect pin state. Write value is output from pin. Value is written to PHDR, but does not affect pin state. Value is written to PHDR, but does not affect pin state. (n = 7) PHnMD1 PHnMD0 Pin State 0 0 1 1 0 1 Other function PHDR value Output Input (Pullup MOS: on) Input (Pullup MOS: off) PHDR value Pin state Pin state PHnMD1 PHnMD0 Pin State 0 1 0 1 0 1 Reserved* Input (Pullup MOS: on) Input (Pullup MOS: off) Read Pin state Pin state Write Ignored (no affect on pin state) Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 0 to 6) Other function H'00 Note: * Operation cannot be guaranteed when this bit it set to "reserved." Rev. 5.00 Dec 12, 2005 page 853 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.8 27.8.1 Port L Port L Data Register (PLDR) Bit: Initial value: R/W: 7 PL7DT * R 6 PL6DT * R 5 PL5DT * R 4 PL4DT * R 3 PL3DT * R 2 PL2DT * R 1 -- * R 0 -- * R Note: * Undefined Port L Data Register (PLDR) is an 8-bit read register that stores data for pins PTL7 to PTL2. PL7DT to PL2DT bit corresponds to PTL7 to PTL2 pin. When the pin function is general input port, if the port is read, the corresponding pin level is read. Table 27.7 shows the function of PLDR. PLDR is initialized to a power-on reset. It retains its previous value in software standby mode and sleep mode, and by a manual reset. Table 27.7 Read/Write Operation of the Port L Data Register (PLDR) PLnMD1 PLnMD0 Pin State 0 1 0 1 * Read Write Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 2 to 7) Other function H'00 1 Reserved* Input Pin state Notes: * Undefined 1. Operation cannot be guaranteed when this bit it set to "reserved." Rev. 5.00 Dec 12, 2005 page 854 of 1034 REJ09B0254-0500 Section 27 I/O Ports 27.9 SC Port Each pin has an input pullup MOS, which is controlled by SC port control register (SCPCR) in PFC. 27.9.1 Port SC Data Register (SCPDR) Bit: Initial value: R/W: Note: * Undefined 7 * R 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SCP7DT SCP6DT SP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Port SC Data Register (SCPDR) is a 7-bit read/write and 1-bit read register that stores data for pins SCPT7 to SCPT0. SCP7DT to SCP0DT bit corresponds to SCPT7 to SCPT0 pin. When the pin function is general output port, if the port is read, the value of the corresponding SCPDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 27.8 shows the function of SCPDR. SCPDR is initialized to B'*0000000 by a power-on reset. After initialization, the general input port function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are read from bits SCP7DT to SCP5DT, SCP3DT, and SCP1DT. It retains its previous value in standby mode and sleep mode, and by a manual reset. Note that the low level is read if bit 7 is read except in general-purpose input. Set the RE bit in SCSCR to 1, when reading RxD2 to RxD0 pin states of the SCP4DT, SCP2DT, and SCP0DT bits in SDPDR while the TE or RE bit in SCSCR is not cleared to 0. When the RE bit is set to 1, the RxD pins function as input pins and their states are read in preference to the SCPCR setting. Rev. 5.00 Dec 12, 2005 page 855 of 1034 REJ09B0254-0500 Section 27 I/O Ports Table 27.8 Read/Write Operation of the SC Port Data Register (SCPDR) SCPnMD1 SCPnMD0 Pin State 0 0 1 1 0 1 Read Write Other function SCPDR value Value is written to SCPDR, but does not affect pin state. Output Input (Pullup MOS: on) Input (Pullup MOS: off) SCPDR value Write value is output from pin. Pin state Pin state Value is written to SCPDR, but does not affect pin state. Value is written to SCPDR, but does not affect pin state. (n = 0 to 6) SCPnMD1 SCPnMD0 Pin State 0 1 0 1 0 1 Reserved* Input (Pullup MOS: on) Input (Pullup MOS: off) Read Pin state Pin state Write Ignored (no affect on pin state) Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 7) Other function H'00 Note: * Operation cannot be guaranteed when this bit it set to "reserved." Rev. 5.00 Dec 12, 2005 page 856 of 1034 REJ09B0254-0500 Section 28 A/D Converter Section 28 A/D Converter 28.1 Overview This LSI includes a 10-bit successive-approximation A/D converter with a selection of up to six analog input channels. 28.1.1 Features A/D converter features are listed below. * 10-bit resolution * Six input channels * High-speed conversion Conversion time: maximum 15 s per channel (with 33-MHz peripheral clock) * Three conversion modes Single mode: A/D conversion of one channel Multi mode: A/D conversion on one to four channels Scan mode: Continuous A/D conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * A/D conversion can be externally triggered * A/D interrupt requested at the end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. Rev. 5.00 Dec 12, 2005 page 857 of 1034 REJ09B0254-0500 Section 28 A/D Converter 28.1.2 Block Diagram Figure 28.1 shows a block diagram of the A/D converter. Peripheral data bus AVCC 10-bit D/A Successive approximation register ADDRC ADDRD ADDRA ADDRB ADCSR AVSS AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer + /8 - Control circuit Comparator Sample-andhold circuit ADI interrupt signal A/D converter /16 ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 28.1 A/D Converter Block Diagram Rev. 5.00 Dec 12, 2005 page 858 of 1034 REJ09B0254-0500 ADCR Bus interface Internal data bus Section 28 A/D Converter 28.1.3 Input Pins Table 28.1 summarizes the A/D converter's input pins. The six analog input pins are divided into two groups: group 0 (AN2 , AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage. Table 28.1 A/D Converter Pins Pin Name Analog power-supply pin Analog ground pin Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation AVcc AVss AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog power supply and A/D converter standard voltage Analog ground and reference voltage Group 0 analog inputs Rev. 5.00 Dec 12, 2005 page 859 of 1034 REJ09B0254-0500 Section 28 A/D Converter 28.1.4 Register Configuration Table 28.2 summarizes the A/D converter's registers. Table 28.2 A/D Converter Registers Name A/D data register A (high) A/D data register A (low) A/D data register B (high) A/D data register B (low) A/D data register C (high) A/D data register C (low) A/D data register D (high) A/D data register D (low) A/D control/status register A/D control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R/W R R R R R R R R 1 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address Access size 16, 8 H'04000080 2 (H'A4000080)* H'04000082 8 2 (H'A4000082)* H'04000084 16, 8 2 (H'A4000084)* H'04000086 8 2 (H'A4000086)* H'04000088 16, 8 2 (H'A4000088)* H'0400008A 8 2 (H'A400008A)* H'0400008C 16, 8 2 (H'A400008C)* H'0400008E 8 2 (H'A400008E)* H'04000090 8 2 (H'A4000090)* H'04000092 8 2 (H'A4000092)* R/(W)* H'00 R/W H'07 Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Only 0 can be written to bit 7, to clear the flag. 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 860 of 1034 REJ09B0254-0500 Section 28 A/D Converter 28.2 28.2.1 Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) Upper register: H Bit: Initial value: R/W: Lower register: L Bit: Initial value: R/W: 7 AD1 0 R 6 AD0 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R 15 AD9 0 R 14 AD8 0 R 13 AD7 0 R 12 AD6 0 R 11 AD5 0 R 10 AD4 0 R 9 AD3 0 R 8 AD2 0 R The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the converted data are transferred to upper register H (bits 7 to 0) of the A/D data register, and the lower 2 bits are transferred to lower register L (bits 7 and 6), for storage. Lower register L (bits 5 to 0) is always read as 0. Table 28.3 indicates the pairings of analog input channels and A/D data registers. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 28.3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 reserved reserved AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 5.00 Dec 12, 2005 page 861 of 1034 REJ09B0254-0500 Section 28 A/D Converter 28.2.2 A/D Control/Status Register (ADCSR) Bit: Initial value: R/W: 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 MULTI 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Write 0 to clear the flag. ADCSR is an 8-bit read/write register that controls the A/D converter and indicates the status. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF 0 Description [Clear condition] (1) Cleared by reading ADF while ADF = 1, then writing 0 in ADF (2) Cleared when DMAC is activated by ADI interrupt and ADDR is read 1 [Set conditions] Single mode: A/D conversion ends Multi mode and scan mode: A/D conversion ends in all selected channels (Initial value) Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6: ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value) Rev. 5.00 Dec 12, 2005 page 862 of 1034 REJ09B0254-0500 Section 28 A/D Converter Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5: ADST 0 1 Description A/D conversion is stopped (Initial value) Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. Multi mode: A/D conversion starts, cycling among the selected channels. After the cycling has been completed, ADST is cleared to 0. Scan mode: A/D conversion starts and continues, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode. Bit 4--Multi Mode (MULTI): Selects single mode, multi mode or scan mode. For further information on operation in these modes, see section 28.4, Operation. Bit 4: MULTI 0 1 ADCR: Bit 5: SCN 0 1 0 1 Multi mode scan mode Description Single mode (Initial value) Bit 3--Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3:CKS 0 1 Description Conversion time = 536 states (maximum) Conversion time = 266 states (maximum)* (Initial value) Note: * The CKS value should be set so that the A/D conversion time is 16 s (minimum). Rev. 5.00 Dec 12, 2005 page 863 of 1034 REJ09B0254-0500 Section 28 A/D Converter Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Channel Selection CH2 0 CH1 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 Description Single Mode (MULTI = 0) reserved reserved AN2 AN3 AN4 AN5 AN6 AN7 Multi Mode (MULTI = 1) reserved reserved AN2 AN2, AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 28.2.3 A/D Control Register (ADCR) Bit: 7 TRGE1 0 R/W 6 TRGE0 0 R/W 5 SCN 0 R/W 4 0 R/W 3 0 R/W 2 -- 1 R 1 -- 1 R 0 -- 1 R RESVD1 RESVD2 Initial value: R/W: ADCR is an 8-bit read/write register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'07 by a reset and in standby mode. Bits 7 and 6--Trigger Enable (TRGE1, TRGE0): Enables or disables external triggering of A/D conversion. Bit 7: TRGE1 0 0 1 1 Bit 6: TRGE0 0 1 0 1 The A/D conversion starts at the falling edge of an input signal from the external trigger pin (ADTRG). Description When an external trigger is input, the A/D conversion does not start (Initial value) Rev. 5.00 Dec 12, 2005 page 864 of 1034 REJ09B0254-0500 Section 28 A/D Converter Bit 5--Scan Mode (SCN): Selects multi mode or scan mode when the MULTI bit is set to 1. See the description of bit 4 in section 28.2.2, A/D Control/Status Register (ADCSR). Bits 4 and 3--Reserved (RESVD1, RESVD2): These bits always read 0. The write value should always be 0. Bits 2 to 0--Resrved: These bits are always read as 0. The write value should always be 0. 28.3 Bus Master Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the bus master. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed. Figure 28.2 shows the data flow for access to an A/D data register. See section 28.7.3, Access Size and Read Data. Rev. 5.00 Dec 12, 2005 page 865 of 1034 REJ09B0254-0500 Section 28 A/D Converter Upper byte read Module internal data bus CPU (H'AA) Bus interface TEMP (H'40) Upper byte of Lower byte of A/D data register A/D data register [H'AA] [H'40] Lower byte read Module internal data bus CPU (H'40) Bus interface TEMP (H'40) Upper byte of Lower byte of A/D data register A/D data register [H'AA] [H'40] Figure 28.2 A/D Data Register Access Operation (Reading H'AA40) Rev. 5.00 Dec 12, 2005 page 866 of 1034 REJ09B0254-0500 Section 28 A/D Converter 28.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 28.4.1 Single Mode (MULTI = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADF, then write 0 in ADF. When the mode or analog input channel must be switched during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN2) is selected in single mode are described next. Figure 28.3 shows a timing diagram for this example. 1. Single mode is selected (MULTI = 0), input channel AN2 is selected (CH2 = CH0 = 0, CH1 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRC. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt processing routine starts. 5. The routine reads ADF, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRC = 0). 7. Execution of the A/D interrupt processing routine ends. Then, when the ADST bit is set to 1, A/D conversion starts to execute 2 to 7 above. Rev. 5.00 Dec 12, 2005 page 867 of 1034 REJ09B0254-0500 Set* Set* Clear* Clear* Set* ADIE ADST A/D conversion starts Section 28 A/D Converter ADF Waiting Waiting A/D conversion 1 Waiting Waiting Waiting A/D conversion result 2 Channel 0 operating Rev. 5.00 Dec 12, 2005 page 868 of 1034 REJ09B0254-0500 Waiting Read result A/D conversion result 1 Read result A/D conversion result 2 Channel 1 operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRC ADDRB ADDRD Figure 28.3 Example of A/D Converter Operation (Single Mode, Channel 2 Selected) Note: * Downward arrows ( ) indicate instruction execution. Section 28 A/D Converter 28.4.2 Multi Mode (MULTI = 1, SCN = 0) Multi mode should be selected when performing multi channel A/D conversions on one or more channels including channel 1. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN2 when CH2 = 0, and AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel (AN2 or AN4) ends, conversion of the second channel (AN3 or AN5) starts immediately. Finally, all of the specified channels are converted in a loop. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 1 (AN4 to AN6) are selected in multi mode are described next. Figure 28.4 shows a timing diagram for this example. 1. Multi mode is selected (MULTI = 1), channel group 1 is selected (CH2 = 1), analog input channels AN4 to AN6 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN4) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN5) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN6). 4. When conversion of all selected channels (AN4 to AN6) is completed, the ADF flag is set to 1 and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI interrupt is requested after A/D conversion. Rev. 5.00 Dec 12, 2005 page 869 of 1034 REJ09B0254-0500 A/D conversion Set* Clear* Clear* ADST Section 28 A/D Converter ADF Channel 0 (AN4) operating Waiting A/D conversion 1 Waiting A/D conversion 2 Waiting A/D conversion 3 Waiting Transfer A/D conversion result 1 Waiting Waiting Rev. 5.00 Dec 12, 2005 page 870 of 1034 REJ09B0254-0500 Waiting A/D conversion result 2 A/D conversion result 3 Channel 1 (AN5) operating Channel 2 (AN6) operating Channel 3 (AN3) operating ADDRA ADDRB Figure 28.4 Example of A/D Converter Operation (Multi Mode, Channels AN4 to AN6 Selected) ADDRC ADDRD Note: * Downward arrows ( ) indicate instruction executed by software. Section 28 A/D Converter 28.4.3 Scan Mode (MULTI = 1, SCN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels including channel 1. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN2 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN3 or AN5) starts immediately. A/D conversion is repeated continuously on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN4 to AN6) are selected in scan mode are described next. Figure 28.5 shows a timing diagram for this example. 1. Scan mode is selected (MULTI = 1, SCN = 1), channel group 1 is selected (CH2 = 1), analog input channels AN4 to AN6 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN4) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN5) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN6). 4. When conversion of all the selected channels (AN4 to AN6) is completed, the ADF flag is set to 1 and conversion of the first channel (AN4) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN4). Rev. 5.00 Dec 12, 2005 page 871 of 1034 REJ09B0254-0500 Continuous A/D conversion Set* Clear* ADST Clear* Section 28 A/D Converter ADF Waiting Waiting A/D conversion 1 Waiting Waiting A/D conversion 2 Waiting A/D conversion 3 Waiting Transfer A/D conversion result 1 A/D conversion result 4 A/D conversion 5 Waiting A/D conversion 4 Waiting Waiting Channel 0 (AN0) operating Rev. 5.00 Dec 12, 2005 page 872 of 1034 REJ09B0254-0500 A/D conversion result 2 A/D conversion result 3 Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC Figure 28.5 Example of A/D Converter Operation (Scan Mode, Channels AN4 to AN6 Selected) ADDRD Note: * Downward arrow indicates instruction executed by software. Section 28 A/D Converter 28.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit of ADCSR is set to 1, then starts conversion. Figure 28.6 shows the A/D conversion timing. Table 28.4 indicates the A/D conversion time. As indicated in figure 28.6, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 28.4. In multi mode and scan mode, the values given in table 28.4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 536 states when CKS = 0 or 266 states when CKS = 1. In all cases, the CKS bit in ADCSR should be set according to the frequency of P so that the conversion time is within the range shown in table 32.16 in section 32, Electrical Characteristics. (1) P Address (2) Write signal Input sampling timing ADF tD tSPL tCONV (1) (2) tD tSPL tCONV : ADCSR write cycle : ADCSR address : A/D conversion start delay : Input sampling time : A/D conversion time Figure 28.6 A/D Conversion Timing Rev. 5.00 Dec 12, 2005 page 873 of 1034 REJ09B0254-0500 Section 28 A/D Converter Table 28.4 A/D Conversion Time (Single Mode) CKS = 0 Symbol A/D conversion start delay Input sampling time A/D conversion time tD tSPL tCONV Min 17 -- 514 Typ -- 129 -- Max 28 -- 525 Min 10 -- 259 CKS = 1 Typ -- 65 -- Max 17 -- 266 Note: Values in the table are numbers of states (tcyc). 28.4.5 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE1, TRGE0 bits are set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software. Figure 28.7 shows the timing. P ADTRG External trigger signal ADST A/D conversion Figure 28.7 External Trigger Input Timing Rev. 5.00 Dec 12, 2005 page 874 of 1034 REJ09B0254-0500 Section 28 A/D Converter 28.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 28.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel to its analog reference value and converts it into 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: * Offset error * Full-scale error * Quantization error * Nonlinearity error These four error quantities are explained below using figure 28.8. In the figure, the 10 bits of the A/D converter have been simplified to 3 bits. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 28.8, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 28.8, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 28.8, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 28.8, item (4)). Note that it does not include offset, full-scale or quantization error. Rev. 5.00 Dec 12, 2005 page 875 of 1034 REJ09B0254-0500 Section 28 A/D Converter Digital output Ideal A/D conversion characteristics Digital output Ideal A/D conversion characteristics (2) Full-scale error 111 110 101 100 011 010 001 000 (4) Nonlinearity error (3) Quantization error 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS: Full-scale voltage Actual A/D convertion characteristics FS Analog input voltage (1) Offset error Figure 28.8 Definitions of A/D Conversion Accuracy 28.7 Usage Notes When using the A/D converter, note the points listed in section 28.7.1 below. 28.7.1 Setting Analog Input Voltage * Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVSS ANn AVCC (n = 2 to 7). * Set the AVCC and AVSS input voltages as defined in section 32, Electrical Characteristics. 28.7.2 Processing of Analog Input Pins To prevent damage from voltage surges at the analog input pins (AN2 to AN7), connect an input protection circuit like the one shown in figure 28.9. The circuit shown also includes an RC filter to suppress noise. This circuit is shown as an example; The circuit constants should be selected according to actual application conditions. Table 28.5 lists the analog input pin specifications and figure 28.10 shows an equivalent circuit diagram of the analog input ports. Rev. 5.00 Dec 12, 2005 page 876 of 1034 REJ09B0254-0500 Section 28 A/D Converter 28.7.3 Access Size and Read Data Table 28.6 shows the relationship between access size and read data. Note the read data obtained with different access sizes, bus widths, and endian modes. The case is shown here in which H'3FF is obtained when AVCC is input as an analog input. FF is the data containing the upper 8 bits of the conversion result, and C0 is the data containing the lower 2 bits. AVCC 100 * 0.1 F SuperH microprocessor AN2 to AN7 AVSS Note: * 10 F 0.01 F Figure 28.9 Example of Analog Input Protection Circuit 1.0 k AN2 to AN7 20 pF 1 M Figure 28.10 Analog Input Pin Equivalent Circuit Rev. 5.00 Dec 12, 2005 page 877 of 1034 REJ09B0254-0500 Section 28 A/D Converter Table 28.5 Analog Input Pin Ratings Item Analog input capacitance Allowable signal-source impedance Min -- -- Max 20 5 Unit pF k Table 28.6 Relationship between Access Size and Read Data Access Size Byte access Bus Width Command Endian MOV.L MOV.B MOV.L MOV.B MOV.L MOV.W MOV.L MOV.W Longword MOV.L access MOV.L 32 Bits (D31--D0) Big Little 16 Bits (D15--D0) Big Little FFFF C0C0 FFxx 8 Bits (D7--D0) Big FF C0 FF xx C0 xx FF xx C0 xx Little FF C0 xx FF xx C0 xx C0 xx FF #ADDRAH,R9 FFFFFFFF FFFFFFFF FFFF @R9,R8 #ADDRAL,R9 @R9,R8 C0C0C0C0 C0C0C0C0 C0C0 #ADDRAH,R9 @R9,R8 FFxxFFxx #ADDRAL,R9 @R9,R8 C0xxC0xx #ADDRAH,R9 @R9,R8 FFxxC0xx FFxxFFxx FFxx Word access C0xxC0xx C0xx C0xx FFxxC0xx FFxx C0xx C0xx FFxx In this table: #ADDRAH .EQU H'04000080 #ADDRAL .EQU H'04000082 Values are shown in hexadecimal for the case where read data is output to an external device via R8. Rev. 5.00 Dec 12, 2005 page 878 of 1034 REJ09B0254-0500 Section 29 D/A Converter Section 29 D/A Converter 29.1 Overview This LSI includes a D/A converter with two channels. 29.1.1 Features D/A converter features are listed below. * Eight-bit resolution * Two output channels * Conversion time: maximum 10 s (with 20-pF capacitive load) * Output voltage: 0 V to AVcc 29.1.2 Block Diagram Figure 29.1 shows a block diagram of the D/A converter. Module data bus AVCC DADR0 DADR1 DA0 AVSS 8-bit D/A Control circuit Legend: DACR: D/A control Register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 29.1 D/A Converter Block Diagram Rev. 5.00 Dec 12, 2005 page 879 of 1034 REJ09B0254-0500 DACR DA1 Bus interface On-chip data bus Section 29 D/A Converter 29.1.3 I/O Pins Table 29.1 summarizes the D/A converter's input and output pins. Table 29.1 D/A Converter Pins Pin Name Analog power-supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Abbreviation AVcc AVss DA0 DA1 I/O Input Input Output Output Function Analog power supply and D/A converter standard voltage Analog ground Analog output, channel 0 Analog output, channel 1 29.1.4 Register Configuration Table 29.2 summarizes the D/A converter's registers. Table 29.2 D/A Converter Registers Name D/A data register 0 D/A data register 1 D/A control register Abbreviation R/W DADR0 DADR1 DACR R/W R/W R/W Initial Value H'00 H'00 H'1F Address* 1 Access size 8 H'040000A0 2 (H'A40000A0)* H'040000A2 8 2 (H'A40000A2)* H'040000A4 8 2 (H'A40000A4)* Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on, either access these registers from the P2 area of logical space or else make an appropriate setting using the MMU so that these registers are not cached. 1. Lower 16 bits of the address 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 880 of 1034 REJ09B0254-0500 Section 29 D/A Converter 29.2 29.2.1 Register Descriptions D/A Data Registers 0 and 1 (DADR0/1) Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W The D/A data registers (DADR0 and DADR1) are 8-bit read/write registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset. 29.2.2 D/A Control Register (DACR) Bit: Initial value: R/W: 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R DACR is an 8-bit read/write register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset. Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7: DAOE1 0 1 Description DA1 analog output is disabled Channel-1 D/A conversion and DA1 analog output are enabled (Initial value) Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6: DAOE0 0 1 Description DA0 analog output is disabled Channel-0 D/A conversion and DA0 analog output are enabled (Initial value) Rev. 5.00 Dec 12, 2005 page 881 of 1034 REJ09B0254-0500 Section 29 D/A Converter Bit 5--D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 0 and 1. When this LSI enters standby mode while D/A conversion is enabled, the D/A output is held and the analog power-supply current is equivalent to that during D/A conversion. To reduce the analog power-supply current in standby mode, clear the DAOE0 and DAOE1 bits and disable the D/A output. Bit 7: DAOE1 0 0 0 1 1 1 Bit 6: DAOE0 0 1 1 0 0 1 Bit 5: DAE -- 0 1 0 1 -- Description D/A conversion is disabled in channels 0 and 1 (Initial value) D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is enabled in channels 0 and 1 When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D and D/A conversion. Bits 4 to 0--Reserved: Read-only bits, always read as 1. Rev. 5.00 Dec 12, 2005 page 882 of 1034 REJ09B0254-0500 Section 29 D/A Converter 29.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 29.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The converted result is output after the conversion time. The output value is (DADR0 contents/256) x AVcc. Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0. 3. If the DADR0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle P Address bus DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion result 2 DA0 High-impedance state Legend: tDCONV : D/A conversion time tDCONV Conversion result 1 tDCONV Figure 29.2 Example of D/A Converter Operation Rev. 5.00 Dec 12, 2005 page 883 of 1034 REJ09B0254-0500 Section 29 D/A Converter Rev. 5.00 Dec 12, 2005 page 884 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Section 30 PC Card Controller (PCC) 30.1 Overview The PC card controller (PCC) controls the external buffer, interrupts, and exclusive ports of the PC card interface to be connected to the SH7727. Using the PCC enables two slots of PC cards that conform to the PCMCIA Rev. 2.1/JEIDA Ver. 4.2 standard to be easily connected to the SH7727. 30.1.1 Features The PCC has the following features: * As a PC card interface to be connected to physical area 6, an IC memory card interface and an I/O card interface are supported. * Outputs control signals for the external buffer (PCC0DRV). * Supports a preemptive operating system by switching attribute memory, common memory, and I/O space by using addresses. * Provides a segment bit (an address bit for the PC card) for common memory, enabling access to a 64-MB space fully conforming to PCMCIA specifications. * Disables the PCC operation and supports only a bus interface of a PC card interface which is same as the SH7709/SH7729 Series (by using the P0USE bit of PCC0GCR). Rev. 5.00 Dec 12, 2005 page 885 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.1.2 Block Diagram Figure 30.1 shows a block diagram of the PC card controller. PC card controller (PCC) PCC0RESET Register selection PCC0DRV IOIS16(PCC0WP) PCC0RDY(IREQ) Area 6 PCC0BVD1(STSCHG) PCC0BVD2(SPKR) Register (0:3) and register control PCC0CD1 PCC0CD2 PCC0VS1 PCC0VS2 PCCREG Internal bus control signal Internal data bus Area 6 internal interrupt signals Battery dead Battery warning RDY/BSY signal change Card detection signal change STSCHG signal change IREQ signal Software interrupt Area 6: An IC memory card interface and an I/O card interface are supported. Figure 30.1 PC Card Controller Block Diagram Rev. 5.00 Dec 12, 2005 page 886 of 1034 REJ09B0254-0500 Interrupt controller Area 6 PC card interface signals PCC0WAIT Bus interface Section 30 PC Card Controller (PCC) 30.1.3 Register Configuration Table 30.1 lists the PC card controller registers. Table 30.1 PC Card Controller Registers Physical Area Physical area 6 (PCC0) Register Name Area 6 interface status register Area 6 general control register Area 6 card status change register Area 6 card status change interrupt enable register Symbol PCC0ISR PCC0GCR PCC0CSCR Read/ Write R R/W R/W Initial Value *1 H'00 H'00 H'00 Address Access Size H'04000160 8 bits 2 (H'A4000160)* H'04000162 8 bits 2 (H'A4000162)* H'04000164 8 bits 2 (H'A4000164)* H'04000166 8 bits 2 (H'A4000166)* PCC0CSCIER R/W Notes: 1. Depends on the PC card status. 2. When address translation by the MMU does not apply, the address in parentheses should be used. Rev. 5.00 Dec 12, 2005 page 887 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.1.4 PCMCIA Support The SH7727 supports an interface based on PCMCIA specifications for physical areas 6. Interfaces supported are the IC memory card interface and I/O card interface defined in the PCMCIA Rev. 2.1/JEIDA Ver. 4.2 standard. Both the IC memory card interface and I/O card interface are supported in area 6. Table 30.2 Features of the PCMCIA Interface Item Access Data bus Memory type Common memory capacity Attribute memory capacity I/O space capacity Others Feature Random access 8/16 bits Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Maximum 64 Mbytes (Supports full PCMCIA specifications by using a segment bit (an address bit for the PC card)) Maximum 32 Mbytes Maximum 32 Mbytes Dynamic bus sizing for I/O bus width* The PCMCIA interface can be accessed from the addressconversion region and non-address-conversion region. Note: * Dynamic bus sizing for the I/O bus width is supported only in little-endian mode. The SH7727 can directly access 32- and 64-MB physical areas in a 64-MB memory space and an I/O space of the PC card (continuous 32/16-MB area mode). The SH7727 provides a segment bit (an address bit for the PC card) in the general control register for area 6 to support a common memory space with full PCMCIA specifications (64 MB). Rev. 5.00 Dec 12, 2005 page 888 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Continuous 32-MB Area Mode: Setting 0 (initial value) in bit 3 (P0MMOD) of the general control register enables the continuous 32-MB area mode. In this mode, the attribute memory space and I/O memory space are 32 MB and the common memory space is 64 MB. In the common memory space, set 1 in bit 2 (P0PA25) of the general control register to access an address of more than 32 MB. By this operation, 1 is output to A25 pin, enabling an address space of more than 32 MB to be accessed. When an address of 32 MB or less is accessed, no setting is required (initial value: 0). This bit does not affect access to attribute memory space or I/O memory space. Figure 30.2 shows the relationship between the memory space of the SH7727 and the memory and I/O spaces of the PC card in the continuous 32-MB area mode. Although memory space and I/O space are supported in area 6. In area 6, set 1 in bit 0 (P0REG) of the general control register to access the common memory space of the PC card, and set 0 in bit 0 to access the attribute memory space (initial value: 0). By this operation, the set value is output to PCCREG pin, enabling any space to be accessed. When the I/O space is accessed in area 6, the output of PCCREG pin is always 0 regardless of the value of bit 0 (P0REG). See the register descriptions in section 30.2, Register Descriptions for details of register settings. SH7727 memory space PC card address space General control register bit settings P0MMOD = 0 P0PA24 = x H'18000000 Area 6 H'1A000000 Attribute memory Attribute memory/ common memory 32 MB I/O space 32 MB P0REG 32 MB P0PA25 = x P0REG = 0 (attribute) P0PA25 = 0 P0REG = 1 (common memory) P0PA25 = 0 P0REG = 1 (common memory) P0PA25 = x P0REG = x Pin PCCREG is always 0 P0PA25 Common mermoy Total 64 MB I/O space 32 MB x: Don't care Figure 30.2 Continuous 32-MB Area Mode Rev. 5.00 Dec 12, 2005 page 889 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Continuous 16-MB Area Mode: Setting 1 in bit 3 (P0MMOD) of the general control register enables the continuous 16-MB area mode. In this mode, the attribute memory space and I/O memory space are 16 MB, and the common memory space is 64 MB. In the common memory space, set the PC card address in bit 2 (P0PA25) and bit 1 (P0PA24) of the general control register to access an address of more than 16 MB. By this operation, values are output to A25 and A24 pins, enabling an address space of more than 16 MB to be accessed (initial value: 0 for P0PA25 and P0PA24). When an address of 16 MB or less is accessed, no settings are required. This bit does not affect access to attribute memory space or I/O memory space. Figures 30.3 and 30.4 show the relationship between the memory space of the SH7727 and the memory and I/O spaces of the PC card in the continuous 16-MB area mode. Although memory space and I/O space are supported in area 6. The attribute memory space, common memory space, and I/O space of the PC card are provided as 16-MB physical spaces in this mode. Therefore, the SH7727 automatically controls PCCREG pin (the value of bit 0 (P0REG) in the general control register is ignored). In area 6, the output of PCCREG pin is 0 when the attribute memory space or I/O space is accessed, and 1 when the common memory space is accessed. See the register descriptions in section 30.2, Register Descriptions for details of register settings. SH7727 memory space PC card address space General control register bit settings P0MMOD = 1 P0REG = x Attribute memory 16 MB (Pin PCCREG is alwys 0) P0PA25 = x, P0PA24 = x H'18000000 Attribute memory 16 MB Common memory 16 MB P0PA25 = 0, P0PA24 = 0 P0PA25 P0PA24 Common mermoy (Pin PCCREG is always 1) P0PA25 = 0, P0PA24 = 1 P0PA25 = 1, P0PA24 = 0 Area 6 H'1A000000 I/O space 16 MB Not used Total 64 MB P0PA25 = 1, P0PA24 = 1 I/O space 16 MB (Pin PCCREG is alwys 0) P0PA25 = x, P0PA24 = x x: Don't care Figure 30.3 Continuous 16-MB Area Mode (Area 6) Rev. 5.00 Dec 12, 2005 page 890 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.2 30.2.1 Register Descriptions Area 6 Interface Status Register (PCC0ISR) Bit: 7 6 5 4 P0VS1 * R 3 P0CD2 * R 2 1 0 Bit name: P0RDY/ P0MWP P0VS2 IREQ Initial value: R/W: * R * R * R P0CD1 P0BVD2 P0BVD1 SPKR STSCHG * R * R * R Note: * Depends on the PC card status. The area 6 interface status register (PCC0ISR) is an 8-bit read-only register which is used to read the status of the PC card connected to area 6. The initial value of PCC0ISR depends on the PC card status. Bit 7--PCC0 Ready (P0RDY/IREQ): The value of RDY/BSY pin of the PC card connected to area 6 is read when the IC memory card interface is connected. The value of IREQ pin of the PC card connected to area 6 is read when the I/O card interface is connected. This bit cannot be written to. Bit 7: P0RDY/IREQ 0 Description Indicates that the value of RDY/BSY pin is 0 when the PC card connected to area 6 is the IC memory card interface type. Indicates that the value of IREQ pin is 0 when the PC card connected to area 6 is the I/O card interface type Indicates that the value of RDY/BSY pin is 1 when the PC card connected to area 6 is the IC memory card interface type. Indicates that the value of IREQ pin is 1 when the PC card connected to area 6 is the I/O card interface type 1 Rev. 5.00 Dec 12, 2005 page 891 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 6--PCC0 Write Protect (P0MWP): The value of WP pin of the PC card connected to area 6 is read when the IC memory card interface is connected. 0 is read when the I/O card interface is connected. This bit cannot be written to. Bit 6: P0MWP 0 Description Indicates that the value of WP pin is 0 when the PC card connected to area 6 uses the IC memory card interface. The value of bit 6 is always 0 when the PC card connected to area 6 is the I/O card interface type Indicates that the value of WP pin is 1 when the PC card connected to area 6 is the IC memory card interface type 1 Bit 5--PCC0 Voltage Sense 2 (P0VS2): The value of VS2 pin of the PC card connected to area 6 is read. This bit cannot be written to. Bit 5: P0VS2 0 1 Description The value of VS2 pin of the PC card connected to area 6 is 0 The value of VS2 pin of the PC card connected to area 6 is 1 Bit 4--PCC0 Voltage Sense 1 (P0VS1): The value of VS1 pin of the PC card connected to area 6 is read. This bit cannot be written to. Bit 4: P0VS1 0 1 Description The value of VS1 pin of the PC card connected to area 6 is 0 The value of VS1 pin of the PC card connected to area 6 is 1 Bit 3--PCC0 Card Detect 2 (P0CD2): The value of CD2 pin of the PC card connected to area 6 is read. This bit cannot be written to. Bit 3: P0CD2 0 1 Description The value of CD2 pin of the PC card connected to area 6 is 0 The value of CD2 pin of the PC card connected to area 6 is 1 Rev. 5.00 Dec 12, 2005 page 892 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 2--PCC0 Card Detect 1 (P0CD1): The value of CD1 pin of the PC card connected to area 6 is read. This bit cannot be written to. Bit 2: P0CD1 0 1 Description The value of CD1 pin of the PC card connected to area 6 is 0 The value of CD1 pin of the PC card connected to area 6 is 1 Bits 1 and 0--PCC0 Battery Voltage Detect 2 and 1 (P0BVD2, P0BVD1): The values of BVD2 and BVD1 pins of the PC card connected to area 6 are read when the IC memory card interface is connected. The values of SPKR and STSCHG pins of the PC card connected to area 6 are read when the I/O card interface is connected. These bits cannot be written to. * IC Memory Interface Bit 1: P0BVD2 1 0 1 0 Bit 0: P0BVD1 1 1 0 0 Description The battery voltage of the PC card connected to area 6 is normal (Battery Good) The battery must be changed although data is guaranteed for the PC card connected to area 6 (Battery Warning) The battery voltage is abnormal and data is not guaranteed for the PC card connected to area 6 (Battery Dead) The battery voltage is abnormal and data is not guaranteed for the PC card connected to area 6 (Battery Dead) * I/O Card Interface Bit 1: P0SPKR 0 1 Bit 0: P0STSCHG 0 1 Description The value of SPKR pin of the PC card connected to area 6 is 0 The value of SPKR pin of the PC card connected to area 6 is 1 Description The value of STSCHG pin of the PC card connected to area 6 is 0 The value of STSCHG pin of the PC card connected to area 6 is 1 Rev. 5.00 Dec 12, 2005 page 893 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.2.2 Area 6 General Control Register (PCC0GCR) Bit: 7 6 5 4 3 2 1 0 Bit name: P0DRVE P0PCCR P0PCCT P0USE P0MMO D Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W P0PA25 P0PA24 P0REG 0 R/W 0 R/W 0 R/W The area 6 general control register (PCC0GCR) is an 8-bit readable/writable register which controls the external buffer, resets, address A25 and A24 pins, and REG pin, and sets the PC card type for the PC card connected to area 6. PCC0GCR is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. Bit 7--PCC0 Buffer Control (P0DRVE): Controls the external buffer for the PC card connected to area 6. Bit 7: P0DRVE 0 1 Description High-level setting for control PCC0DRV pin of the external buffer for the PC card connected to area 6 (Initial value) Low-level setting for control PCC0DRV pin of the external buffer for the PC card connected to area 6 Bit 6--PCC0 Card Reset (P0PCCR): Controls resets for the PC card connected to area 6. Bit 6: P0PCCR 0 1 Description Low-level setting for reset PCC0RESET pin for the PC card connected to area 6 (Initial value) High-level setting for reset PCC0RESET pin for the PC card connected to area 6 Bit 5--PCC0 Card Type (P0PCCT): Specifies the type of the PC card connected to area 6. Cleared to 0 when the PC card is the IC memory card interface type; set to 1 when the PC card is the I/O card interface type. Bit 5: P0PCCT 0 1 Description The PC card connected to area 6 is handled as the IC memory card interface type (Initial value) The PC card connected to area 6 is handled as the I/O card interface type Rev. 5.00 Dec 12, 2005 page 894 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 4--PCC0 USE/NOT USE (P0USE): Specifies that the PC Card Controller to be work or not work. Bit 4: P0USE 0 1 Description PC Card Controller doesn't work. PC Card Controller works. Bit 3--PCC0 Mode (P0MMOD): Controls PCCREG and A24 pins for the PC card connected to area 6. Specifies either A24 of the address to be accessed or bit P0REG for outputting to PCCREG pin. When the common memory space is accessed, specifies either A24 of the address to be accessed or bit P0PA24 for outputting to A24 pin. By this operation, continuous 32 or 16 Mbytes can be selected for the address area of the common memory space of the PC card. Bit 3: P0MMOD 0 1 Description Bit P0REG is output to PCCREG pin, and A24 of address to be accessed is output to A24 pin (continuous 32-MB area mode) (Initial value) A24 of address to be accessed is output to PCCREG pin. When the common memory space is accessed, P0PA24 is output to A24 pin (continuous 16-MB area mode) Bit 2--PC Card Address (P0PA25): Controls A25 pin for the PC card connected to area 6. When the common memory space is accessed for the PC card connected to area 6, this bit is output to A25 pin. When the attribute memory space or I/O space is accessed, this bit is meaningless. Bit 2: P0PA25 0 1 Description When the common memory space is accessed for the PC card connected to area 6, 0 is output to A25 pin (Initial value) When the common memory space is accessed for the PC card connected to area 6, 1 is output to A25 pin Rev. 5.00 Dec 12, 2005 page 895 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 1--PC Card Address (P0PA24): Controls A24 pin for the PC card connected to area 6. When bit P0MMOD is 1 and the common memory space is accessed for the PC card connected to area 6, this bit is output to A24 pin. When bit P0MMOD is 0 or the attribute memory space or I/O space is accessed, this bit is meaningless. Bit 1: P0PA24 0 1 Description When bit P0MMOD is 1 and the common memory space is accessed for the PC card connected to area 6, 0 is output to A24 pin (Initial value) When bit P0MMOD is 1 and the common memory space is accessed for the PC card connected to area 6, 1 is output to A24 pin Bit 0--PCC0REG Space Indication (P0REG): Controls PCCREG pin for the PC card connected to area 6. When bit P0MMOD is 0, this bit is output to PCCREG pin for the PC card connected to area 6. When bit P0MMOD is 1 or the I/O card interface is accessed, this bit is meaningless. Bit 0: P0REG 0 1 Description When bit P0MMOD is 0 and the PC card connected to area 6 is accessed, 0 is output to PCCREG pin (Initial value) When bit P0MMOD is 0 and the PC card connected to area 6 is accessed, 1 is output to PCCREG pin 30.2.3 Area 6 Card Status Change Register (PCC0CSCR) Bit: Initial value: R/W: 7 0 R/W 6 -- 0 -- 5 P0IREQ 0 R/W 4 P0SC 0 R/W 3 P0CDC 0 R/W 2 P0RC 0 R/W 1 P0BW 0 R/W 0 P0BD 0 R/W Bit name: P0SCDI The area 6 card status change register (PCC0CSCR) is an 8-bit readable/writable able register. PCC0CSCR bits are set to 1 by interrupt sources of the PC card connected to area 6 (only bit 7 can be set to 1 as required). PCC0CSCR is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. Rev. 5.00 Dec 12, 2005 page 896 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 7--PCC0 Software Card Detect Change Interrupt (P0SCDI): A PCC0 software card detect change interrupt can be generated by writing 1 to this bit. When this bit is set to 1, the same interrupt as the PCC0 card detect change interrupt (bit 3 set status) occurs if bit 3 (PCC0 card detect change enable) in the area 6 card status change interrupt enable register (PCC0CSCIER) is set to 1. If bit 3 is cleared to 0, no interrupt occurs. Bit 7: P0SCDI 0 1 Description No software card detect change interrupt occurs for the PC card connected to area 6 (Initial value) Software card detect change interrupt occurs for the PC card connected to area 6 Bit 6--Reserved: Always reads 0. The write value should always be 0. Bit 5--PCC0IREQ Request (P0IREQ): Indicates the interrupt request for the IREQ pin of the PC card when the PC card connected to area 6 is the I/O card interface type. The P0IREQ bit is set to 1 when an interrupt request signal in pulse mode or level mode is input to the IREQ pin. The mode is selected by bits 5 and 6 (PCC0IREQ interrupt enable bits) in the area 6 card status change interrupt enable register (PCC0CSCIER). This bit can be cleared to 0 only in pulse mode. Write 0 to bit 5 to clear the bit to 0. This bit is not changed if 1 is written. In level mode, bit 5 is a read-only bit which reflects the IREQ pin state (if the IREQ pin is low, 1 is read). This bit always reads 0 on the IC memory card interface. Bit 5: IREQ 0 1 Description No interrupt request on the IREQ pin of the PC card when the PC card is on the I/O card interface (Initial value) An interrupt request on the IREQ pin of the PC card has occurred when the PC card is on the I/O card interface Rev. 5.00 Dec 12, 2005 page 897 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 4--PCC0 Status Change (P0SC): Indicates a change in the value of the STSCHG pin of the PC card when the PC card connected to area 6 is the I/O card interface type. When the STSCHG pin is changed from 1 to 0, the SC bit is set to 1. When STSCHG pin is not changed, the P0SC bit remains at 0. Write 0 to bit 4 when this bit is set to 1 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the IC memory card interface. Bit 4: P0SC 0 1 Description STSCHG pin of the PC card is not changed when the PC card is on the I/O card interface (Initial value) STSCHG pin of the PC card is changed from 1 to 0 when the PC card is on the I/O card interface Bit 3--PCC0 Card Detect Change (P0CDC): Indicates a change in the value of the CD1 and CD2 pins in the PC card connected to area 6. When the CD1 and CD2 values are changed, the P0CDC bit is set to 1. When the values are not changed, the P0CDC bit remains at 0. Write 0 to bit 3 in order to clear this bit to 0. This bit is not changed if 1 is written. Bit 3: P0CDC 0 1 Description CD1 and CD2 pins in the PC card are not changed CD1 and CD2 pins in the PC card are changed (Initial value) Bit 2--PCC0 Ready Change (P0RC): Indicates a change in the value of the RDY/BSY pin of the PC card when the PC card connected to area 6 is the IC memory card interface type. When the RDY/BSY pin is changed from 0 to 1, the P0RC bit is set to 1. When the RDY/BSY pin is not changed, the P0RC bit remains at 0. Write 0 to bit 2 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the I/O card interface. Bit 2: P0RC 0 1 Description RDY/BSY pin in the PC card is not changed when the PC card is on the IC memory card interface (Initial value) RDY/BSY pin in the PC card is changed from 0 to 1 when the PC card is on the IC memory card interface Rev. 5.00 Dec 12, 2005 page 898 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 1--PCC0 Battery Warning (P0BW): Indicates whether the BVD2 and BVD1 pins of the PC card are in the state in which "the battery must be changed although the data is guaranteed" when the PC card connected to area 6 is on the IC memory card interface. When the BVD2 and BVD1 pins are 0 and 1, respectively, the P0BW bit is set to 1; in other cases, the P0BW bit remains at 0. This bit is updated when the BVD2 and BVD1 pins are changed. Write 0 to bit 1 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the I/O card interface. Bit 1: P0BW 0 1 Description BVD2 and BVD1 of the PC card are not in the battery warning state when the PC card is in the IC memory card interface (Initial value) BVD2 and BVD1 of the PC card are in the battery warning state and "the battery must be changed although the data is guaranteed" when the PC card is on the IC memory card interface Bit 0--PCC0 Battery Dead (P0BD): Indicates whether the BVD2 and BVD1 pins of the PC card are in the state in which "the battery must be changed since the data is not guaranteed" when the PC card connected to area 6 is on the IC memory card interface. When the BVD2 and BVD1 pins are 1 and 0 or 0 and 0, the P0BD bit is set to 1; in other cases, the P0BD bit remains at 0. This bit is updated when the BVD2 and BVD1 pins are changed. Write 0 to bit 0 in order to clear this bit to 0. This bit is not changed if 1 is written. This bit always reads 0 on the I/O card interface. Bit 0: P0BD 0 Description BVD2 and BVD1 of the PC card are not in the state in which "the battery must be changed since the data is not guaranteed" when the PC card is on the IC memory card interface (Initial value) BVD2 and BVD1 of the PC card are in the state in which "the battery must be changed since the data is not guaranteed" when the PC card is on the IC memory card interface 1 Rev. 5.00 Dec 12, 2005 page 899 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.2.4 Area 6 Card Status Change Interrupt Enable Register (PCC0CSCIER) Bit: Bit name: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 P0CDE 0 R/W 2 P0RE 0 R/W 1 0 R/W 0 0 R/W P0CRE IREQE1 IREQE0 P0SCE P0BWE P0BDE The area 6 card status change interrupt enable register (PCC0CSCIER) is an 8-bit readable/writable register. PCC0CSCIER enables or disables interrupt requests for interrupt sources for the PC card connected to area 6. When a PCC0CSCIER is set to 1, the corresponding interrupt is enabled, and when the bit is cleared to 0, the interrupt is disabled. PCC0CSCIER is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. Bit 7--PCC0 Card Reset Enable (P0CRE): When this bit is set to 1, and when the CD1 and CD2 pins detect that a PC card is connected to area 6, the area 6 general control register (PCC0GCR) is initialized. Bit 7: P0CRE 0 1 Description The area 6 general control register (PCC0GCR) is not initialized even if a PC card is detected in area 6 (Initial value) The area 6 general control register (PCC0GCR) is initialized when a PC card is detected connected to area 6 Rev. 5.00 Dec 12, 2005 page 900 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bits 6 and 5--PCC0IREQ Request Enable (IREQE1, IREQE0): These bits enable or disable IREQ pin interrupt requests and select the interrupt mode when the PC card connected to area 6 is the I/O card interface type. Note that bit 5 (P0IREQ) in the area 6 card status change register (PCC0CSCR) is cleared if the values in bits 6 and 5 in this register are changed. These bits have no meaning on the IC memory card interface. Bit 6: IREQE1 0 Bit 5: IREQE0 0 Description IREQ requests are not accepted for the PC card connected to area 6. Bit 5 in the status change register (PCC0CSCR) functions as a read-only bit (Initial value) that indicates the inverse of the IREQ pin signal. The level-mode IREQ interrupt request signal is accepted for the PC card connected to area 6. In level mode, an interrupt occurs when level 0 of the signal input from the IREQ pin is detected. The pulse-mode IREQ interrupt request signal is accepted for the PC card connected to area 6. In pulse mode, an interrupt occurs when a falling edge from 1 to 0 of the signal input from the IREQ pin is detected. The pulse-mode IREQ interrupt request signal is accepted for the PC card connected to area 6. In pulse mode, an interrupt occurs when a rising edge from 0 to 1 of the signal input from the IREQ pin is detected. 0 1 1 0 1 1 Bit 4--PCC0 Status Change Enable (P0SCE): When the PC card connected to area 6 is on the I/O card interface, bit 4 enables or disables the interrupt request when the value of the BVD1 pin (STSCHG pin) is changed. This bit has no meaning in the IC memory card interface. Bit 4: P0SCE 0 1 Description No interrupt occurs for the PC card connected to area 6 regardless of the value of the BVD1 pin (STSCHG pin) (Initial value) An interrupt occurs for the PC card connected to area 6 when the value of the BVD1 pin (STSCHG pin) is changed from 1 to 0 Bit 3--PCC0 Card Detect Change Enable (P0CDE): Bit 3 enables or disables the interrupt request when the values of the CD1 and CD2 pins are changed. Bit 3: P0CDE 0 1 Description No interrupt occurs for the PC card connected to area 6 regardless of the values of the CD1 and CD2 pins (Initial value) An interrupt occurs for the PC card connected to area 6 when the values of the CD1 and CD2 pins are changed Rev. 5.00 Dec 12, 2005 page 901 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Bit 2--PCC0 Ready Change Enable (P0RE): When the PC card connected to area 6 is on the IC memory card interface, bit 2 enables or disables the interrupt request when the value of the RDY/BSY pin is changed. This bit has no meaning on the I/O card interface. Bit 2: P0RE 0 1 Description No interrupt occurs for the PC card connected to area 6 regardless of the (Initial value) value of the RDY/BSY pin An interrupt occurs for the PC card connected to area 6 when the value of the RDY/BSY pin is changed from 0 to 1 Bit 1--PCC0 Battery Warning Enable (P0BWE): When the PC card connected to area 6 is on the IC memory card interface, bit 1 enables or disables the interrupt request when the BVD2 and BVD1 pins are in the state in which "the battery must be changed although the data is guaranteed". This bit has no meaning on the I/O card interface. Bit 1: P0BWE 0 1 Description No interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed although the data is guaranteed" (Initial value) An interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed although the data is guaranteed" Bit 0--PCC0 Battery Dead Enable (P0BDE): When the PC card connected to area 6 is on the IC memory card interface, bit 0 enables or disables the interrupt request when the BVD2 and BVD1 pins are in the state in which "the battery must be changed since the data is not guaranteed". This bit has no meaning on the I/O card interface. Bit 0: P0BDE 0 1 Description No interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed since the data is not guaranteed" (Initial value) An interrupt occurs when the BVD2 and BVD1 pins are in the state in which "the battery must be changed since the data is not guaranteed" Rev. 5.00 Dec 12, 2005 page 902 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.3 30.3.1 Operation PC card Connection Specification (Interface Diagram, Pin Correspondence) A25 to A0 PCC0DRV D7 to D0 D15 to D0 RD/WR G DIR G A25 to A0 D15 to D0 SH7727 G DIR CE1 CE2 OE WE/PGM (IORD) (IOWR) RESET REG G CE1B CE2B RD WE ICIORD ICIOWR PCC0RESET PCCREG PCC0WAIT IOIS16 PCC0RDY PCC0BVD1 PCC0BVD2 G PCC0CD1/CD2 PCC0VS1/VS2 WAIT WP(IOIS16) RDY/BSY(IREQ) BVD1 (STSCHG) BVD2 (SPKR) CD1 CD2 VS1 VS2 Figure 30.4 SH7727 Interface Rev. 5.00 Dec 12, 2005 page 903 of 1034 REJ09B0254-0500 Area 6 PC card (memory or I/O) D15 to D8 Section 30 PC Card Controller (PCC) Table 30.3 PCMCIA Support Interface IC Memory Card Interface Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Signal Name GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM RDY/BSY VCC VPP1 I/O I/O I/O I/O I/O I I I I I I I I I O I/O Function Ground Data Data Data Data Data Card enable Address Output enable Address Address Address Address Address Write enable Ready/busy Power supply Programming power supply I I I I I I I I I I Address Address Address Address Address Address Address Address Address Address I/O Card Interface Signal Name GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM IREQ VCC VPP1 I/O I/O I/O I/O I/O I I I I I I I I I O I/O Function Ground Data Data Data Data Data Card enable Address Output enable Address Address Address Address Address Write enable Interrupt request Power supply SH7727 Corresponding Pin -- D3 D4 D5 D6 D7 CE1B A10 RD A11 A9 A8 A13 A14 WE PCC0RDY -- Programming -- and peripheral power supply I I I I I I I I I I Address Address Address Address Address Address Address Address Address Address A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 19 20 21 22 23 24 25 26 27 28 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 Rev. 5.00 Dec 12, 2005 page 904 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) IC Memory Card Interface Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Signal Name A0 D0 D1 D2 WP GND GND CD1 D11 D12 D13 D14 D15 CE2 VS1 RFU RFU A17 A18 A19 A20 A21 VCC VPP2 I I I I I O I/O I/O I/O I/O I/O I O I/O I I/O I/O I/O O Function Address Data Data Data Write protect Ground Ground Data Data Data Data Data Card enable Reserved Reserved Address Address Address Address Address Power supply Programming power supply I I I I O Address Address Address Address I/O Card Interface Signal Name A0 D0 D1 D2 IOIS16 GND GND O I/O I/O I/O I/O I/O I O I I I I I I I D11 D12 D13 D14 D15 CE2 IORD IOWR A17 A18 A19 A20 A21 VCC VPP2 I/O I I/O I/O I/O O Function Address Data Data Data 16-bit I/O port Ground Ground Data Data Data Data Data Card enable I/O read I/O write Address Address Address Address Address Power supply SH7727 Corresponding Pin A0 D0 D1 D2 IOIS16 -- -- D11 D12 D13 D14 D15 CE2B ICIORD ICIOWR A17 A18 A19 A20 A21 -- Card detection CD1 Card detection PCC0CD1 Voltage sense VS1 Voltage sense PCC0VS1 Programming -- and peripheral power supply I I I I O Address Address Address Address A22 A23 A24 A25 53 54 55 56 57 A22 A23 A24 A25 VS2 A22 A23 A24 A25 Voltage sense VS2 Voltage sense PCC0VS2 Rev. 5.00 Dec 12, 2005 page 905 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) IC Memory Card Interface Pin 58 59 60 61 Signal Name RESET WAIT RFU REG I I/O I O Function Reset Wait request Reserved I/O Card Interface Signal Name RESET WAIT INPACK I/O I O O I Function Reset Wait request Input acknowledge SH7727 Corresponding Pin PCC0RESET PCC0WAIT -- Attribute REG memory space select Battery voltage detection Battery voltage detection Data Data Data Ground SPKR Attribute PCCREG memory space select Digital sound signal Card status change Data Data Data Ground PCC0BVD2 62 BVD2 O O 63 BVD1 O STSCHG O PCC0BVD1 64 65 66 67 68 D8 D9 D10 CD2 GND I/O I/O I/O O D8 D9 D10 GND I/O I/O I/O O D8 D9 D10 -- Card detection CD2 Card detection PCC0CD2 Rev. 5.00 Dec 12, 2005 page 906 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.3.2 PC Card Interface Timing (1) Memory card interface timing Tpcm1 CKIO PCC0DRV A25 to A0 0 Tpcm2 CExx RD/WR PCCREG RD (read) D15 to D0 (read) WE (write) D15 to D0 (write) PCC0RESET 0 Figure 30.5 PCMCIA Memory Card Interface Basic Timing Rev. 5.00 Dec 12, 2005 page 907 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO PCC0DRV A25 to A0 0 CExx RD/WR PCCREG RD (read) D15 to D0 (read) WE (write) D15 to D0 (write) PCC0WAIT PCC0RESET 0 Figure 30.6 PCMCIA Memory Card Interface Wait Timing Rev. 5.00 Dec 12, 2005 page 908 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Tpci1 CKIO PCC0DRV A25 to A0 Tpci2 CExx RD/WR PCCREG ICIORD (at read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) PCC0RESET 0 Figure 30.7 PCMCIA I/O Card Interface Basic Timing Rev. 5.00 Dec 12, 2005 page 909 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Tpci0 CKIO PCC0DRV A25 to A0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w 0 CExx RD/WR PCCREG ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) PCC0WAIT IOIS16 PCC0RESET 0 Figure 30.8 PCMCIA I/O Card Interface Wait Timing Rev. 5.00 Dec 12, 2005 page 910 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Tpci0 CKIO PCC0DRV A25 to A1 A0 CExx Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w 0 RD/WR PCCREG ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) PCC0WAIT IOIS16 PCC0RESET 0 Figure 30.9 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Refer to section 12, Bus State Controller (BSC), and section 32, Electrical Characteristics, for more details. Rev. 5.00 Dec 12, 2005 page 911 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) 30.3.3 Usage Notes External Bus Frequency Limit when Using PC Card: According to the PC card standard, the attribute memory access time is specified as 600 ns (3.3 V)/300 ns (5 V). Therefore, when the SH7727 accesses attribute memory, the bus cycle must be coordinated with the PC card interface timing. In the SH7727, the timing can be adjusted by setting the TED and TEH values in the PCR register, and the number of waits and number of idle states in the WCR1 and WCR2 registers, allowing a PC card to be used within the above frequency ranges. The common memory access time and I/O access time (based on the IORD and IOWR signals) are also similarly specified (see table below), and a PC card must be used within the above ranges in order to satisfy all these specifications. PC Card Space Attribute memory Common memory Access Time (5 V Operation) 300 ns 250 ns Access Time (3.3 V Operation) 600 ns 600 ns 165 ns 165 ns I/O space (-IORD/-IOWR pulse width) Pin Function Control and Card Type Switching: When setting pin function controller pin functions to dedicated PC card use ("other function"), the disabled state should first be set in the card status change interrupt enable register (PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the setting has been made. However, this restriction does not apply to the card detection pins (CD1, CD2). When changing the card type bit (P0PCCT) in the area 6 general control register (PCC0GCR), the disabled state should first be set in the card status change interrupt enable register (PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the setting has been made. Reason: When PC card controller settings are modified, the functions of PC card pins that generate various interrupts change, with the result that unnecessary interrupts may be generated. Rev. 5.00 Dec 12, 2005 page 912 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Setting Procedure when Using PC Card Controller: The following steps should be followed when using a card controller: 1. Drive pin ASEMD0 high. 2. Set bit 0 (A6PCM) in bus control register 1 (BCR1) in the bus state controller to 1. 3. Set bit 4 (P0USE) in the area 6 general control register in the PC card controller to 1. 4. Set the pin function controller to custom PC card pin functions ("other functions"). Rev. 5.00 Dec 12, 2005 page 913 of 1034 REJ09B0254-0500 Section 30 PC Card Controller (PCC) Rev. 5.00 Dec 12, 2005 page 914 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Section 31 User-Debugging Interface (H-UDI) 31.1 Overview The SH7727 incorporates a user-debugging interface (H-UDI) and advanced user debugger (AUD) for program debugging. 31.2 User Debugging Interface (H-UDI) The H-UDI (user-debugging interface) performs on-chip debugging which is supported by the SH7727. The H-UDI described here is a serial interface which is compatible with JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and BoundaryScan Architecture) specifications. The H-UDI in the SH7727 supports a boundary scan mode, and is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator. 31.2.1 Pin Description TCK: H-UDI serial data input/output clock pin. Data is serially supplied to the H-UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. TMS: Mode select input pin. The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol conforms to the JTAG standard (IEEE Std. 1149.1). TRST: H-UDI reset input pin. Input is accepted asynchronously with respect to TCK, and when TRST low, the H-UDI is reset. See section 31.4.2, Reset Configuration, for more information. TDI: H-UDI serial data input pin. Data transfer to the H-UDI is executed by changing this signal in synchronization with TCK. TDO: H-UDI serial data output pin. Data output from the H-UDI is executed by reading this signal in synchronization with TCK. ASEMD0: The ASE mode select pin. If a low level is input to the ASEMD0 pin while the ASEMD0 RESETP pin is asserted, ASE mode is entered, and if a high level is input, normal mode is Rev. 5.00 Dec 12, 2005 page 915 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) entered. When using the user system alone and not using an emulator or the H-UDI, a high level should be input. In ASE mode, boundary scan and emulator functions can be used. Hold the input level to the ASEMD0 pin for at least one cycle after the RESETP pin is negated. ASEBRKAK: ASEBRKAK Dedicated emulator pin. 31.2.2 Block Diagram Figure 31.1 shows the block diagram of the H-UDI. TDI Shift register SDIR SDID TDO MUX TCK TMS TRST TAP controller Decoder Local bus Figure 31.1 H-UDI Block Diagram 31.3 Register Descriptions The H-UDI has the following registers. * SDIR: instruction register * SDID: device identification register * SDBSR: boundary-scan register Rev. 5.00 Dec 12, 2005 page 916 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Table 31.1 shows H-UDI register configuration. Table 31.1 H-UDI Registers CPU Side Name Instruction register Abbreviation R/W SDIR R -- -- Size 16 -- -- Address H'04000200 -- -- H-UDI Side R/W R/W R R/W Size 16 32 -- Initial Value* H'FFFF H'0004200F Undefined Device Identification SDID register Boundary-scan register SDBSR Note: * Initialized when TRST pin is low or when TAP is in the test-logic-reset state. 31.3.1 Bypass Register (SDBPR) The bypass register (SDBPR) is a 1-bit register that cannot be accessed by the CPU. Setting the SDIR register to the bypass mode makes the SDBPR register to be connected between the TDI and TDO H-UDI pins. 31.3.2 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its initial state. It is initialized by TRST or in the TAP test-logic-reset state, and can be written by the H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is set to this register. Bit: Initial value: Bit: Initial value: 15 TI3 1 7 -- 1 14 TI2 1 6 -- 1 13 TI1 1 5 -- 1 12 TI0 1 4 -- 1 11 -- 1 3 -- 1 10 -- 1 2 -- 1 9 -- 1 1 -- 1 8 -- 1 0 -- 1 Bits 15 to 12--Test Instruction Bits (TI3 to TI0): Cannot be written by the CPU. Rev. 5.00 Dec 12, 2005 page 917 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Table 31.2 H-UDI Commands TI3 0 0 0 0 0 1 1 1 1 1 0 TI2 0 1 1 1 1 0 0 1 1 1 0 TI1 0 0 0 1 1 0 1 0 1 1 0 TI0 0 0 1 0 1 -- -- -- 0 1 1 Description EXTEST SAMPLE/PRELOAD Reserved H-UDI reset negate H-UDI reset assert Reserved H-UDI interrupt Reserved Reserved Bypass mode (initial value) Recovery from sleep Bits 11 to 0--Reserved: Always read 1. 31.3.3 Boundary-Scan Register (SDBSR) Boundary-scan register (SDBSR) is a shift register allocated on the PAD to control the I/O pins in this LSI. The boundary-scan test is available in compliance with the JTAG standard by using the EXTEST and SAMPLE/PRELOAD instructions. Table 31.3 lists the correspondence between the SH7727 pins and the boundary-scan register. Rev. 5.00 Dec 12, 2005 page 918 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Table 31.3 Correspondence between SH7727 Pins and Boundary-Scan Register Bit from TDI 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 D26/PTB2 D25/PTB1 D24/PTB0 D23/PTA7 D22/PTA6 D21/PTA5 D20/PTA4 D19/PTA3 D18/PTA2 D17/PTA1 D16/PTA0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Pin Name I/O Bit 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 Pin Name MD1 MD2 NMI IRQ0/IRL0/PTH0 IRQ1/IRL1/PTH1 IRQ2/IRL2/PTH2 IRQ3/IRL3/PTH3 IRQ4/PTH4 MD5 BREQ VEPWC VCPWC BACK D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 D26/PTB2 D25/PTB1 D24/PTB0 D23/PTA7 D22/PTA6 D21/PTA5 D20/PTA4 D19/PTA3 D18/PTA2 D17/PTA1 D16/PTA0 D15 D14 D13 D12 I/O IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 5.00 Dec 12, 2005 page 919 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Bit 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 Pin Name D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VEPWC VCPWC BACK D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 D26/PTB2 D25/PTB1 D24/PTB0 D23/PTA7 D22/PTA6 D21/PTA5 D20/PTA4 D19/PTA3 D18/PTA2 D17/PTA1 D16/PTA0 D15 D14 D13 D12 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control 265 264 263 262 261 260 269 268 267 266 Bit 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 Pin Name D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BS/PTK4 WE2/DQMUL/ICIORD/PTK6 WE3/DQMUU/ICIORD/PTK7 AUDSYNC/PTE7/PCC0RDY CS4/PTK2 CS5/CE1A/PTK3 CE2A/PTE4 CE2B/PTE5 AFE_HC1/USB1d_DPLS/PTK0 AFE_RLYCNT/USB1d_DMNS/ PTK1 AFE_SCLK/USB1d_TXDPLS PTM7/PINT7/AFE_FS/ USB1d_RCV PTM6/PINT6/AFE_RXIN/ USB1d_SPEED PTM5/PINT5/AFE_TXOUT/ USB1d_TXSE0 A0 A1 A2 A3 A4 A5 I/O Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT Rev. 5.00 Dec 12, 2005 page 920 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Bit 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 Pin Name A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 BS/PTK4 RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/PTK6 WE3/DQMUU/ICIOWR/PTK7 RD/WR AUDSYNC/PTE7/PCC0RDY CS0 CS2 CS3 CS4/PTK2 CS5/CE1A/PTK3 CS6/CE1B CE2A/PTE4 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 221 220 219 218 Bit 224 223 222 Pin Name CE2B/PTE5 AFE_HC1/USB1d_DPLS/PTK0 AFE_RLYCNT/USB1d_DMNS/ PTK1 AFE_SCLK/USB1d_TXDPLS PTM7/PINT7/AFE_FS/ USB1d_RCV PTM6/PINT6/AFE_RXIN/ USB1d_SPEED PTM5/PINT5/AFE_TXOUT/ USB1d_TXSE0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 I/O OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Rev. 5.00 Dec 12, 2005 page 921 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Bit 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 Pin Name A25 BS/PTK4 RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/PTK6 WE3/DQMUU/ICIOWR/PTK7 RD/WR AUDSYNC/PTE7/PCC0RDY CS0 CS2 CS3 CS4/PTK2 CS5/CE1A/PTK3 CS6/CE1B CE2A/PTE4 CE2B/PTE5 AFE_HC1/USB1d_DPLS/PTK0 AFE_RLYCNT/USB1d_DMNS/ PTK1 AFE_SCLK/USB1d_TXDPLS PTM7/PINT7/AFE_FS/ USB1d_RCV PTM6/PINT6/AFE_RXIN/ USB1d_SPEED PTM5/PINT5/AFE_TXOUT/ USB1d_TXSE0 PTM4/PINT4/AFE_RDET Reserved/USB1d_SUSPEND0 USB1_ovr_crnt/USBF_VBUS USB2_ovr_crnt RTS2/USB1d_TXENL PTE2/USB1_PWR_EN PTE1/USB2_PWR_EN CKE/PTK5 RAS3/PTJ0 I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN Bit 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 Pin Name Reserved/PTJ1 Reserved/CAS/PTJ2 Reserved/PTJ3 Reserved/PTJ4 ReservedPTJ5 CL1/PTD5 DON/PTD7 M_DISP/PTE6 FLM/PTE3 WAIT AUDCK/PTH6/PCC0WAIT IOIS16/PTG7 ASEBRKAK/PTG5 PTG4 AUDATA3/PTG3/PCC0BVD2 AUDATA2/PTG2/PCC0BVD1 AUDATA1/PTG1/PCC0CD2 AUDATA0/PTG0/PCC0CD1 PTH5/ADTRG PTF3/PINT11/Reserved PTF2/PCCREG/Reserved PTF1/PCC0VS1/Reserved PTF0/PCC0VS2/Reserved MD0 PTM4/PINT4/AFE_RDET Reserved/USB1d_SUSPEND0 RTS2/USB1d_TXENL PTE2/USB1_PWR_EN PTE1/USB2_PWR_EN CKE/PTK5 RAS3/PTJ0 Reserved/PTJ1 Reserved/CAS/PTJ2 Reserved/PTJ3 Reserved/PTJ4 I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 5.00 Dec 12, 2005 page 922 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Bit 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 Pin Name Reserved/PTJ5 CL1/PTD5 DON/PTD7 M_DISP/PTE6 FLM/PTE3 PCC0RESET/DRAK0 PCC0DRV/DACK0 ASEBRKAK/PTG5 AUDATA3/PTG3/PCC0BVD2 AUDATA2/PTG2/PCC0BVD1 AUDATA1/PTG1/PCC0CD2 AUDATA0/PTG0/PCC0CD1 PTF3/PINT11/Reserved PTF2/PCCREG/Reserved PTF1/PCC0VS1/Reserved PTF0/PCC0VS2/Reserved PTM4/PINT4/AFE_RDET Reserved/USB1d_SUSPEND0 RTS2/USB1d_TXENL PTE2/USB1_PWR_EN PTE1/USB2_PWR_EN CKE/PTK5 RAS3/PTJ0 Reserved/PTJ1 Reserved/CAS/PTJ2 Reserved/PTJ3 Reserved/PTJ4 Reserved/PTJ5 CL1/PTD5 DON/PTD7 M_DISP/PTE6 FLM/PTE3 PCC0RESET/DRAK0 PCC0DRV/DACK0 ASEBRKAK/PTG5 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Bit 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 Pin Name AUDATA3/PTG3/PCC0BVD2 AUDATA2/PTG2/PCC0BVD1 AUDATA1/PTG1/PCC0CD2 AUDATA0/PTG0/PCC0CD1 PTF3/PINT11/Reserved PTF2/PCCREG/Reserved PTF1/PCC0VS1/Reserved PTF0/PCC0VS2/Reserved PTM3/LCD15/PINT10 PTM2/LCD14/PINT9 PTM1/LCD13/PINT8 PTM0/LCD12 STATUS0/PTJ6 STATUS1/PTJ7 CL2/PTH7 SCK0/SCPT1 SIOMCLK/SCPT3 SCK_SIO/SCPT5 SIOFSYNC/SCPT6 RxD0/SCPT0 RxD2/SCPT4 LCD7/PTD3 LCD6/PTD2 LCD1/PTD1 LCD0/PTD0 DREQ0/PTD4 LCLK/UCLK/PTD6 RxD_SIO/SCPT2 CTS2/IRQ5/SCPT7 LCD11/PTC7/PINT3 LCD10/PTC6/PINT2 LCD9/PTC5/PINT1 LCD8/PTC4/PINT0 LCD5/PTC3 LCD4/PTC2 I/O Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Rev. 5.00 Dec 12, 2005 page 923 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) Bit 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 Pin Name LCD3/PTC1 LCD2/PTC0 MD3 MD4 PTM3/LCD15/PINT10 PTM2/LCD14/PINT9 PTM1/LCD13/PINT8 PTM0/LCD12 STATUS0/PTJ6 STATUS1/PTJ7 CL2/PTH7 TxD0/SCPT0 SCK0/SCPT1 TxD_SIO/SCPT2 SIOMCLK/SCPT3 TxD2/SCPT4 SCK_SIO/SCPT5 SIOFSYNC/SCPT6 LCD11/PTC7/PINT3 LCD10/PTC6/PINT2 LCD9/PTC5/PINT1 LCD8/PTC4/PINT0 LCD7/PTD3 LCD6/PTD2 LCD5/PTC3 LCD4/PTC2 LCD3/PTC1 LCD2/PTC0 LCD1/PTD1 I/O IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Bit 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to TDO Pin Name LCD0/PTD0 PTM3/LCD15/PINT10 PTM2/LCD14/PINT9 PTM1/LCD13/PINT8 PTM0/LCD12 STATUS0/PTJ6 STATUS1/PTJ7 CL2/PTH7 TxD0/SCPT0 SCK0/SCPT1 TxD_SIO/SCPT2 SIOMCLK/SCPT3 TxD2/SCPT4 SCK_SIO/SCPT5 SIOFSYNC/SCPT6 LCD11/PTC7/PINT3 LCD10/PTC6/PINT2 LCD9/PTC5/PINT1 LCD8/PTC4/PINT0 LCD7/PTD3 LCD6/PTD2 LCD5/PTC3 LCD4/PTC2 LCD3/PTC1 LCD2/PTC0 LCD1/PTD1 LCD0/PTD0 I/O OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Note: Control is a signal that is active in its low level. Setting the control signal to low level drives the corresponding pin with the OUT value. Rev. 5.00 Dec 12, 2005 page 924 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) 31.4 31.4.1 H-UDI Operations TAP Controller Figure 31.2 shows the internal states of TAP controller. State transitions basically conform with the JTAG standard. 1 Tset-logic-reset 0 0 Run-test/idle 1 Select-DR-scan 1 Select-IR-scan 0 1 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 0 Figure 31.2 TAP Controller State Transitions Note: The transition condition is the TMS value on the rising edge of TCK. The TDI value is sampled on the rising edge of TCK; shifting occurs on the falling edge of TCK. The TDO value changes on the TCK falling edge. The TDO is at high impedance, except with shiftDR (shift-SR) and shift-IR states. During the change to TRST = 0, there is a transition to test-logic-reset asynchronously with TCK. Rev. 5.00 Dec 12, 2005 page 925 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) 31.4.2 Reset Configuration Table 31.4 Reset Configuration ASDMD0* H 1 RESETP L H TRST L H L H L H Chip State Normal reset and H-UDI reset Normal reset H-UDI reset only Normal operation 2 Reset hold* ASE user mode* : Normal reset 3 ASE break mode* : RESETP assertion masked 3 L L H L H H-UDI reset only Normal operation Notes: 1. Performs main chip mode and ASE mode settings ASEMD0 = H, main chip mode ASEMD0 = L, ASE mode When user system is used alone without using emulator or H-UDI, set ASEMD0 to H. 2. During ASE mode, reset hold is enabled by setting RESETP and TRST pins at low level for a constant cycle. In this state, the CPU does not start up, even if RESETP is set to high level. When TRST is set to high level, H-UDI operation is enabled, but the CPU does not start up. The reset hold state is cancelled by the following: * Boot request from H-UDI (boot sequence) * Another RESETP assert (power-on reset) 3. There are two ASE modes, one for executing software in the emulator's firmware (ASE break mode) and one for executing user software (ASE user mode). Rev. 5.00 Dec 12, 2005 page 926 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) 31.4.3 H-UDI Reset An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset negate command. SDIR H-UDI reset assert H-UDI reset negate Chip internal reset CPU state Branch to H'A0000000 Figure 31.3 H-UDI Reset 31.4.4 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the VBR value plus offset, and return by the RTE instruction. This interrupt request has a fixed priority level of 15. H-UDI interrupts are not accepted in sleep mode or standby mode. 31.4.5 Bypass Setting the command from H-UDI to SDIR allows to set the H-UDI pins to the bypass mode that conforms with the JTAG standard. 31.4.6 Using H-UDI to Recover from Sleep Mode It is possible to recover from sleep mode by setting a command (0001) from the H-UDI in SDIR. Rev. 5.00 Dec 12, 2005 page 927 of 1034 REJ09B0254-0500 Section 31 User-Debugging Interface (H-UDI) 31.5 Usage Notes 1. An H-UDI command other than an H-UDI interrupt, once set, will not be modified as long as another command is not re-issued from the H-UDI. An H-UDI interrupt command, however, will be changed to a bypass command once set. 2. Because chip operations are suspended in standby mode, H-UDI commands are not accepted. However, the TAP controller remains in operation at this time. 3. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator. 31.6 Advanced User Debugger (AUD) The AUD is a function exclusively for use by an emulator. Refer to the User's Manual for the relevant emulator for details of the AUD. Rev. 5.00 Dec 12, 2005 page 928 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Section 32 Electrical Characteristics 32.1 Absolute Maximum Ratings Table 32.1 shows the absolute maximum ratings. Table 32.1 Absolute Maximum Ratings Item Power supply voltage (I/O) Symbol VccQ Rating -0.3 to 4.2 -0.3 to 2.5 Unit V V Power supply voltage (internal) Vcc Vcc - PLL1 Vcc - PLL2 Vcc - RTC Input voltage (except port L) Input voltage (port L) Analog power-supply voltage USB power-supply voltage Analog input voltage Operating temperature Storage temperature Vin Vin AVcc AVcc_USB VAN Topr Tstr -0.3 to VccQ + 0.3 -0.3 to AVcc + 0.3 -0.3 to 4.6 -0.3 to 4.2 -0.3 to AVcc + 0.3 -20 to 75 -55 to 125 V V V V V C C Caution: Operating the chip in excess of the absolute maximum rating may result in permanent damage. * Order of turning on 1.9 V power (Vcc, Vcc-PLL1, Vcc-PLL2, Vcc-RTC) and 3.3 V power (VccQ, AVcc, AVcc_USB): 1. First turn on the 3.3 V power, then turn on the 1.9 V power within 1 ms. This interval should be as short as possible. 2. Until Voltage is applied to all power supplies, a low level is input at the RESETP pin and, a maximum of 4 CKIO clock cycles have been generated, internal circuits remain unsettled, and so pin states are also undefined. The system design must ensure that these undefined states do not cause erroneous system operation. Note that the RESETP pin will not accept low level input while the CA pin is low level. 3. The state of pins MD5 to MD0 should be established after power supply startup and maintained until after the RESETP pin is negated. Read-in of pins MD5 to MD0 is always performed while the RESETP pin is asserted. Waveforms at power-on are shown in the following figure 32.1. Rev. 5.00 Dec 12, 2005 page 929 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics (Max. 1 ms) 3.3 V 3.3 V power 1.9 V 1.9 V power RESETP Pin states undefined All other pins* Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Figure 32.1 Power-On Sequence * Power-off order 1. In the reverse order of powering-on, first turn off the 1.9 V power, then turn off the 3.3 V power within 1 ms. This interval should be as short as possible. 2. Pin states are undefined while only the 1.9 V power is off. The system design must ensure that these undefined states do not cause erroneous system operation. Rev. 5.00 Dec 12, 2005 page 930 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.2 DC Characteristics Tables 32.2 and 32.3 list DC characteristics. Table 32.2 DC Characteristics (1) Condition: Item Power supply voltage Ta = -20 to 75C Symbol VCCQ VCC, VCC-PLL1, VCC-PLL2, VCC-RTC*1 Min 3.0 2.6 1.70 1.60 Typ -- -- -- -- Max 3.6 3.6 2.05 2.05 Unit V Measurement Conditions 160 MHz products 100 MHz products 160 MHz products 100 MHz products Analog (A/D, D/A) powersupply voltage Analog USB power-supply voltage Analog (A/D, During A/D D/A) power- conversion supply During A/D current and D/A conversion Idle Current dissipation Normal operation AVCC*2 3.0 3.3 3.3 0.8 2.4 3.6 3.6 2 6 V V mA mA Same potential as VccQ when not used Same potential as VccQ when not used AVCC_USB 3.0 AICC -- -- -- ICC*3 -- 0.01 330 5.0 650 mA mA Ta = 25C Ta = 25C, Vcc = 1.9 V, I = 160 MHz, X/Y memory on, cache on, and Renesas test program operating Ta = 25C, Vcc = 1.9 V, I = 160 MHz, X/Y memory off, cache on, and Renesas test program operating -- 260 -- Rev. 5.00 Dec 12, 2005 page 931 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Measurement Conditions Ta = 25C, Vcc = 1.9 V, I = 100 MHz, X/Y memory on, cache on, and Renesas test program operating Ta = 25C, Vcc = 1.9 V, I = 100 MHz, X/Y memory off, cache on, and Renesas test program operating VCCQ = 3.3 V B = 33 MHz In sleep mode*1 ISLEEP -- 40 50 mA Total Vcc + VccQ, Vcc = 1.9 V, VccQ = 3.3 V, B = 33 MHz, and no external bus cycles except refresh cycles Ta = 25C (with RTC clock input)*4 Ta = 25C (with RTC clock input)*4 Item Current dissipation Normal operation Symbol ICC*3 Min -- Typ 250 Max 450 Unit mA -- 190 -- ICCQ -- 20 -- In standby mode ICC ICCQ -- -- 30 10 120 30 A Notes: 1. Regardless of whether the PLL or RTC is used, connect Vcc-PLL and Vcc-RTC to Vcc, and Vss-PLL and Vss-RTC to Vss. 2. AVcc conditions must be: VccQ - 0.3 V AVcc VccQ + 0.3 V. If the A/D and D/A converters are not used, do not leave the AVcc and AVss pins open. Connect AVcc to VccQ, and connect AVss to VssQ. 3. Current dissipation values are for VIH min = VccQ - 0.5 V and VIL max = 0.5 V with all output pins in the no-load state. 4. There is no stipulation regarding the power supply in standby mode when there is no RTC clock input. Rev. 5.00 Dec 12, 2005 page 932 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Table 32.2 DC Characteristics (2) Condition: Item Input high voltage Ta = -20 to 75C Symbol RESETP, VIH RESETM, NMI, IRQ5 to IRQ0, MD5 to MD0, IRL3 to IRL0, PINT15 to PINT0, ASEMD0, ADTRG, TRST, EXTAL, CKIO, CA EXTAL2 Min Typ Max Unit Measurement Conditions VCCQ x 0.9 -- VCCQ + 0.3 V -- -- -- Connect to Vcc when no crystal oscillator is connected Port L Other input pins Input low voltage RESETP, RESETM, NMI BREQ, IRQ5 to IRQ0, MD5 to MD0 Port L Other input pin Input leak current Three-state leak current Output high voltage All input pins |Iin| VIL 2.0 2.0 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- 2.4 2.0 -- -- -- -- -- -- -- -- -- -- -- -- AVCC + 0.3 VCCQ + 0.3 VCCQ x 0.1 V 0.5 VCCQ x 0.2 AVCC x 0.2 VCCQ x 0.2 1.0 1.0 -- -- 0.55 A A V V V Vin = 0.5 to VCCQ - 0.5 V Vin = 0.5 to VCCQ - 0.5 V VCCQ = 3.0 V, IOH = -200 A VCCQ = 3.0 V, IOH = -2mA VCCQ = 3.6 V, IOL = 1.6 mA Standby mode Normal operation |Isti| I/O, all output pins (off condition) All output pins VOH Output low voltage All output pins VOL -- Rev. 5.00 Dec 12, 2005 page 933 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Measurement Conditions Item Pull-up resistance Pin capacity Port pin Pins other than analog pins Analog pins* Symbol Ppull C CAN Min 30 -- -- Typ 60 -- -- Max 120 10 20 Unit k pF pF Note: * There are four analog pins, USB1_P, USB2_P, USB1_M, and USB2_M. Table 32.3 Permitted Output Current Values Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.0 to 3.6 V, Ta = -20 to 75C Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL IOL -IOH (-IOH) Min -- -- -- -- Typ -- -- -- -- Max 2.0 120 2.0 40 Unit mA mA mA mA Caution: To ensure LSI reliability, do not exceed the value for output current given in table 32.3. 32.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Regarding the power supply and frequency specifications of the individual products, refer to figure 32.2, tables 32.2 and 32.4. Rev. 5.00 Dec 12, 2005 page 934 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics VccQ (V) 3.6 I = 24 to 100 MHz B = 24 to 50 MHz P = 6* to 33.34 MHz 3.0 I = 24 to 100 MHz B = 24 to 33.34 MHz P = 6* to 33.34 MHz 2.6 1.60 1.70 2.05 Vcc (V) (1) 100 MHz products I = 24 to 144 MHz B = 24 to 50 MHz P = 6* to 33.34 MHz VccQ (V) 3.6 I = 24 to 160 MHz B = 24 to 66.67 MHz P = 6* to 33.34 MHz 3.0 1.70 1.75 2.05 Vcc (V) (2) 160 MHz products Note: * When using the USB function controller, select a peripheral clock (P) setting of 13 MHz or above. Figure 32.2 Power Supply Voltage and Operating Frequency Rev. 5.00 Dec 12, 2005 page 935 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Table 32.4 Maximum Operating Frequencies (1) Item CPU, cache, TLB (I) External bus (B) or CKIO I/O frequency Symbol f Min 24 24 24 6 Max 100 33.34 50 33.34 Unit MHz Power Supply Voltage Conditions VCC = 1.60 to 2.05 V VCCQ = 2.6 to 3.6 V VCC = 1.60 to 2.05 V VCCQ = 2.6 to 3.6 V VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V Peripheral modules (P) VCC = 1.60 to 2.05 V VCCQ = 2.6 to 3.6 V -- Table 32.6 Table 32.5 Reference Products -- 100 MHz products Table 32.4 Maximum Operating Frequencies (2) Item CPU, cache, TLB (I) Symbol f Min 24 24 External bus (B) or CKIO I/O frequency 24 24 6 Max 144 160 50 66.67 33.34 Unit MHz Power Supply Voltage Conditions VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.75 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V VCC = 1.75 to 2.05 V VCCQ= 3.0 to 3.6 V Peripheral modules (P) VCC = 1.70 to 2.05 V VCCQ= 3.0 to 3.6 V -- Table 32.8 Table 32.7 -- Reference Products -- 160 MHz products Rev. 5.00 Dec 12, 2005 page 936 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.1 Clock Timing Table 32.5 Clock Timing (1) Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, 100 MHz products Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time CKIO2 clock output delay time CKIO2 clock output rise time CKIO2 clock output fall time Power-on oscillation settling time RESETP setup time (At power on and cancellation of standby mode) RESETM setup time (At cancellation of standby mode) RESETP assert time (At power on and cancellation of standby mode) RESETM assert time (At cancellation of standby mode) Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 PLL synchronization settling time 1 (At cancellation of standby mode) PLL synchronization settling time 2 (At multiplier change) IRQ/IRL interrupt determination time (RTC used and standby mode) Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tCK2D tCK2OR tCK2OF tOSC1 tRESPS tRESMS tRESPW tRESMW tOSC2 tOSC3 tOSC4 tPLL1 tPLL2 tIRQSTB Min 6 30 9 9 -- -- 24 30 9 9 -- -- 24 30 8 8 -- -- -- -- -- 10 20 0 20 20 10 10 11 100 100 100 Max 33.34 166.7 -- -- 6 6 33.34 41.7 -- -- 6 6 33.34 41.7 -- -- 6 6 2.5 7 7 -- -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ms ns ns tcyc tcyc ms ms ms s s s 32.7 32.8 32.9 32.10, 32.11 32.12 32.11 32.6 32.6, 32.7 32.5 32.4 Figure 32.3 Rev. 5.00 Dec 12, 2005 page 937 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Table 32.6 Clock Timing (2) Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.70 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, 100 MHz products Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time CKIO2 clock output delay time CKIO2 clock output rise time CKIO2 clock output fall time Power-on oscillation settling time RESETP setup time (At power on and cancellation of standby mode) RESETM setup time (At cancellation of standby mode) RESETP assert time (At power on and cancellation of standby mode) RESETM assert time (At cancellation of standby mode) Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 PLL synchronization settling time 1 (At cancellation of standby mode) PLL synchronization settling time 2 (At multiplier change) IRQ/IRL interrupt determination time (RTC used and standby mode) Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tCK2D tCK2OR tCK2OF tOSC1 tRESPS tRESMS tRESPW tRESMW tOSC2 tOSC3 tOSC4 tPLL1 tPLL2 tIRQSTB Min 6 20 4 4 -- -- 24 20 4 4 -- -- 24 20 3 3 -- -- -- -- -- 10 20 0 20 20 10 10 11 100 100 100 Max 50 166.7 -- -- 6 6 50 41.7 -- -- 6 6 50 41.7 -- -- 5 5 2.5 7 7 -- -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ms ns ns tcyc tcyc ms ms ms s s s 32.7 32.8 32.9 32.10, 32.11 32.12 32.11 32.6 32.6, 32.7 32.5 32.4 Figure 32.3 Rev. 5.00 Dec 12, 2005 page 938 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Table 32.7 Clock Timing (3) Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.70 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, 160 MHz products Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time CKIO2 clock output delay time CKIO2 clock output rise time CKIO2 clock output fall time Power-on oscillation settling time RESETP setup time (At power on and cancellation of standby mode) RESETM setup time (At cancellation of standby mode) RESETP assert time (At power on and cancellation of standby mode) RESETM assert time (At cancellation of standby mode) Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 PLL synchronization settling time 1 (At cancellation of standby mode) PLL synchronization settling time 2 (At multiplier change) IRQ/IRL interrupt determination time (RTC used and standby mode) Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tCK2D tCK2OR tCK2OF tOSC1 tRESPS tRESMS tRESPW tRESMW tOSC2 tOSC3 tOSC4 tPLL1 tPLL2 tIRQSTB Min 6 20 4 4 -- -- 24 20 4 4 -- -- 24 20 3 3 -- -- -- -- -- 10 20 0 20 20 10 10 11 100 100 100 Max 50 166.7 -- -- 6 6 50 41.7 -- -- 6 6 50 41.7 -- -- 5 5 2.5 7 7 -- -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ms ns ns tcyc tcyc ms ms ms s s s 32.7 32.8 32.9 32.10, 32.11 32.12 32.11 32.6 32.6, 32.7 32.5 32.4 Figure 32.3 Rev. 5.00 Dec 12, 2005 page 939 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Table 32.8 Clock Timing (4) Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.75 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C, 160 MHz products Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time CKIO2 clock output delay time CKIO2 clock output rise time CKIO2 clock output fall time Power-on oscillation settling time RESETP setup time (At power on and cancellation of standby mode) RESETM setup time (At cancellation of standby mode) RESETP assert time (At power on and cancellation of standby mode) RESETM assert time (At cancellation of standby mode) Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 PLL synchronization settling time 1 (At cancellation of standby mode) PLL synchronization settling time 2 (At multiplier change) IRQ/IRL interrupt determination time (RTC used and standby mode) Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tCK2D tCK2OR tCK2OF tOSC1 tRESPS tRESMS tRESPW tRESMW tOSC2 tOSC3 tOSC4 tPLL1 tPLL2 tIRQSTB Min 6 15 1.5 1.5 -- -- 24 15 1.5 1.5 -- -- 24 15 3 3 -- -- -- -- -- 10 20 0 20 20 10 10 11 100 100 100 Max 66.67 166.7 -- -- 6 6 66.67 41.7 -- -- 6 6 66.67 41.7 -- -- 5 5 2.5 7 7 -- -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ms ns ns tcyc tcyc ms ms ms s s s 32.7 32.8 32.9 32.10, 32.11 32.12 32.11 32.6 32.6, 32.7 32.5 32.4 Figure 32.3 Rev. 5.00 Dec 12, 2005 page 940 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics tEXcyc EXTAL* (input) 1/2 VCCQ tEXH tEXL VIH 1/2 VCCQ tEXR VIH VIH VIL tEXF VIL Note: * The clock input from the EXTAL pin. Figure 32.3 EXTAL Clock Input Timing tCKIcyc tCKIH CKIO (input) 1/2 VCCQ VIH VIL tCKIF tCKIL VIH VIL VIH 1/2 VCCQ tCKIR Figure 32.4 CKIO Clock Input Timing Rev. 5.00 Dec 12, 2005 page 941 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics tcyc tCKOH CKIO (output) tCKOL 1/2VCCQ VOH VOH VOL tCKOF VOH VOL 1/2VCCQ tCKOR tCK2D tCK2D CKIO2 (output) VOH VOH VOL tCK2OF VOL VOH tCK2OR Figure 32.5 CKIO Clock Output Timing Stable oscillation CKIO, internal clock VCCQ VCCQ min tOSC1 RESETP Note: Oscillation settling time when built-in oscillator is used tRESP/MW tRESP/MS Figure 32.6 Power-on Oscillation Settling Time Rev. 5.00 Dec 12, 2005 page 942 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Standby CKIO, internal clock tOSC2 RESETP RESETM Note: Oscillation settling time when built-in oscillator is used Stable oscillation tRESP/MW Figure 32.7 Oscillation Settling Time at Standby Return (Return by Reset) Standby CKIO, internal clock tOSC3 Stable oscillation NMI Note: Oscillation settling time when built-in oscillator is used Figure 32.8 Oscillation Settling Time at Standby Return (Return by NMI) Rev. 5.00 Dec 12, 2005 page 943 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Standby CKIO, internal clock tOSC4 Stable oscillation IRQ4 to IRQ0 PINT0/1 Note: Oscillation settling time when built-in oscillator is used Figure 32.9 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0) Reset or NMI interrupt request Stable input clock EXTAL input, CKIO input PLL synchronization PLL output, CKIO output tPLL1 PLL synchronization Stable input clock Internal clock STATUS0 STATUS1 Normal Standby Normal Note: PLL oscillation setting time when clock is input from EXTAL pin or CKIO pin in continuous oscillation mode. Figure 32.10 PLL Synchronization Settling Time by Reset or NMI Interrupt Rev. 5.00 Dec 12, 2005 page 944 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics IRQ4-IRQ0/IRL3-IRL0 interrupt request Stable input clock EXTAL input, CKIO input PLL synchronization PLL output, CKIO output tIRLSTB tPLL1 PLL synchronization Stable input clock Internal clock STATUS0 STATUS1 Normal Standby Normal Note: PLL oscillation setting time when clock is input from EXTAL pin or CKIO pin in continuous oscillation mode. Figure 32.11 PLL Synchronization Settling Time by IRQ/IRL and PINT0/1 Interrupt Multiplier factor change EXTAL input*1 tPLL2 CKIO PLL output output*2, Internal clock Notes: 1. Clock mode 7, CKIO input. 2. Clock mode 7, PLL output. Figure 32.12 PLL Sync Stabilization Time at Frequency Multiplier Factor Change Rev. 5.00 Dec 12, 2005 page 945 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.2 Control Signal Timing Table 32.9 Control Signal Timing Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Min RESETP pulse width 1 RESETP setup time* RESETP hold time RESETM pulse width RESETM setup time RESETM hold time BREQ setup time BREQ hold time 1 NMI setup time * NMI hold time 1 IRQ5-IRQ0 setup time * Max -- -- -- tcyc ns ns tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 32.13 32.14 tRESPW tRESPS tRESPH tRESMW tRESMS tRESMH tBREQS tBREQH 2 20* 23 2 12 3 34 10 3 10 4 10 4 -- -- 0 0 0 0 *3 -- -- -- -- -- -- -- -- -- 10 16 15 15 15 15 32.15 32.14 tNMIS tNMIH tIRQS tIRQH tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2 IRQ5-IRQ0 hold time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer-on time 1 Bus buffer-on time 2 32.15 32.16 Notes: 1. RESETP, NMI and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock falls. When using as IRL, please observe the setup time. 2. In the standby mode, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100 s). When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 s). 3. In the standby mode, tRESMW = tOSC2 (10 ms). In the sleep mode, RESETM must be kept low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH). Rev. 5.00 Dec 12, 2005 page 946 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics CKIO tRESPS/MS tRESPW/MW RESETP RESETM tRESPS/MS Figure 32.13 Reset Input Timing CKIO tRESPH/MH RESETP RESETM tNMIH NMI tIRQH IRQ5 to IRQ0 VIL tRESPS/MS VIH VIL tNMIS VIH VIL tIRQS VIH Figure 32.14 Interrupt signal Input Timing Rev. 5.00 Dec 12, 2005 page 947 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics CKIO tBREQH tBREQS BREQ tBACKD BACK RD, RD/WR, RAS, CAS, CSn, WEn, BS, MCSn A25 to A0, D31 to D0 tBOFF2 tBON2 tBACKD tBREQH tBREQS tBOFF1 tBON1 Figure 32.15 Bus Release Timing Normal mode Standby mode Normal mode CKIO tSTD STATUS 0 STATUS 1 tBOFF2 RD, RD/WR, RAS, CAS, CSn, WEn, BS, MCSn A25 to A0, D31 to D0 tBON2 tSTD tBOFF1 tBON1 Figure 32.16 Pin Drive Timing at Standby Rev. 5.00 Dec 12, 2005 page 948 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.3 AC Bus Timing Table 32.10 Bus Timing Conditions: Clock Modes 0/1/2/7, VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Address delay time Symbol Min tAD 1.5 1.5 Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read/write delay time Read/write hold time tAS tAH *1 tBSD tCSD1 tCSD2 tRWD tRWH 0 7 -- 1.5 1 1.5 0 -- 6 7 0 2 1 -- Max 13 16 -- -- 12 12 12 10 -- 10 -- -- -- -- 10 14 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns Conditions Figure Vcc = 1.70 to 2.05 V 32.17 to 32.30, VccQ = 3.0 to 3.6 V 32.33 to 32.40 Other than the above 32.17 to 32.19 32.17 to 32.22 32.17 to 32.30, 32.34 to 32.40 32.17 to 32.40 32.17 to 32.22 32.17 to 32.40 32.17 to 32.22 32.17 to 32.22, 32.34 to 32.37 32.17 to 32.22, 32.34 to 32.40 32.23 to 32.26 32.17 to 32.22, 32.34 to 32.40 32.23 to 32.26 32.17 to 32.19, 32.34, 32.35 32.17 to 32.19, 32.34, 32.35, 32.38 to 32.40 32.27 to 32.30 Read strobe delay time tRSD Read data setup time 1 tRDS1 Read data setup time 2 tRDS2 Read data hold time 1 Read data hold time 2 2 tRDH1* tRDH2 Write enable delay time tWED Write data delay time 1 tWDD1 Write data delay time 2 tWDD2 -- 13 ns Rev. 5.00 Dec 12, 2005 page 949 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Item Write data hold time 1 Symbol Min tWDH1 1.5 Max -- Unit ns Conditions Figure 32.17 to 32.19, 32.34, 32.35, 32.38 to 32.40 32.27 to 32.30 32.17 to 32.19 32.34, 32.35, 32.38 to 32.40 Vcc = 1.70 to 2.05 V 32.18 to 32.22, VccQ = 3.0 to 3.6 V 32.35, 32.37, 32.39, 32.40 Other than the above 32.18 to 32.22, 32.35, 32.37, 32.39, 32.40 32.23 to 32.33 32.23 to 32.33 32.23 to 32.30 32.32 32.38 to 32.40 32.38 to 32.40 32.39, 32.40 32.39, 32.40 32.17 to 32.30, 32.33 to 32.40 Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time tWDH2 tWDH3 tWDH4 tWTS 1.5 2 2 5 6 -- -- -- -- -- -- ns ns ns ns WAIT hold time tWTH 0 ns RAS delay time 2 CAS delay time 2 DQM delay time CKE delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time DACK delay time 1 tRASD2 tCASD2 tDQMD tCKED tICRSD tICWSD tIO16S tIO16H tDAKD1 1.5 1.5 1.5 1.5 -- -- 12 4 -- 12 12 10 12 12 12 -- -- 10 ns ns ns ns ns ns ns ns ns Notes: 1. tAH: This is to deal with the latest negate timing of CSn, RD, or WEn. 2. tRDH1: This is to deal with the earliest negate timing of CSn or RD. Rev. 5.00 Dec 12, 2005 page 950 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.4 Basic Timing T1 CKIO tAD A25 to A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31 to D0 (read) tAH tWED WEn (write) tWDD1 D31 to D0 (write) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tWED tRWH tWDH3 tWDH1 tRSD tRWH tCSD2 tRWH tAS tAD T2 tRDH1 tRWD tRDH1 Figure 32.17 Basic Bus Cycle (No Wait) Rev. 5.00 Dec 12, 2005 page 951 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics T1 Tw T2 CKIO tAD A25 to A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31 to D0 (read) tWED WEn (write) tWDD1 D31 to D0 (write) tBSD BS tDAKD1 DACKn tAS tAD tCSD2 tRWH tRDH1 tRWD tRSD tRWH tRDH1 tWED tAH tRWH tWDH3 tWDH1 tBSD tDAKD1 tWTS tWTH WAIT Figure 32.18 Basic Bus Cycle (One Wait) Rev. 5.00 Dec 12, 2005 page 952 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics T1 Tw Tw T2 CKIO tAD A25 to A0 tAH tCSD1 CSn tRWD RD/WR tAH tRSD RD (read) tRDS1 D31 to D0 (read) tAH tWED WEn (write) tWDD1 D31 to D0 (write) tBSD BS tDAKD1 DACKn tAS tAD tCSD2 tRWH tRDH1 tRWD tRSD tRWH tRDH1 tWED tRWH tWDH3 tWDH1 tBSD tDAKD1 tWTS tWTH WAIT tWTS tWTH Notes: tRDH1: Specified based on the earliest negate timing of CSn or RD. tAH: Specified based on the latest negate timing of CSn, RD, or WEn. Figure 32.19 Basic Bus Cycle (External Wait, WAITSEL = 1) Rev. 5.00 Dec 12, 2005 page 953 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.5 Burst ROM Timing T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO tAD A25 to A4 tAD A3 to A0 tAH tCSD1 CSn tRDH1 tRWD RD/WR tRSD RD tRDH1 tRDS D31 to D0 tBSD BS tDAKD1 DACKn tAD tAD tCSD2 tRWH tRWD tAH tRSD tAH tRSD tRSD tRWH tRDH1 tRDS1 tBSD tBSD tBSD tDAKD1 tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 32.20 Burst ROM Bus Cycle (No Wait) Rev. 5.00 Dec 12, 2005 page 954 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics T1 Tw Tw TB2 TB1 Tw TB2 T2 T2 CKIO tAD A25 to A4 tAD A3 to A0 tAH tCSD1 CSn tRDH1 tRWD RD/WR tRSD RD tRDH1 tRDS1 D31 to D0 tBSD BS tDAKD1 DACKn tAD tCSD2 tRWH tRWD tAH tRSD tAH tRSD tRSD tRSD tRWH tRDH1 tRDS1 tRDH1 tBSD tBSD tBSD tDAKD1 tWTS tWTH tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 32.21 Burst ROM Bus Cycle (Two Waits) Rev. 5.00 Dec 12, 2005 page 955 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics T1 CKIO tAD A25 to A4 Tw Tw TB2 TB1 TBw T2 tAD tAD A3 to A0 tAH tCSD1 CSn tRDH1 tRWD RD/WR tRSD RD tRDH1 tRDS1 D31 to D0 tBSD BS tDAKD1 DACKn tCSD2 tRWH tRWD tAH tRSD1 tAH tRSD1 tRSD tRWH tRDH1 tRDS tBSD tBSD tBSD tDAKD1 tWTS tWTH tWTS tWTH WAIT tWTS tWTH tWTS tWTH Note: In the write cycle, the basic bus cycle is performed. Figure 32.22 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) Rev. 5.00 Dec 12, 2005 page 956 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.6 Synchronous DRAM Timing Tr CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS tBSD tDQMD tCASD2 tRASD2 tRWD Row address tAD Row address Tc1 Tc2 (Tpc) tAD tAD Read A command tAD Column address tCSD1 tAD Row address CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.23 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) Rev. 5.00 Dec 12, 2005 page 957 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tr CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS Trw Trw Tc1 Tcw Td1 (Tpc) (Tpc) tAD Row address tAD Row address tAD Row address Column address tCSD1 tAD Read A command tAD tRWD tRASD2 tCASD2 CAS tDQMD DQMxx tCASD2 tDQMD tRDS2 tRDH2 D31 to D0 tBSD BS tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.24 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) Rev. 5.00 Dec 12, 2005 page 958 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tr CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 (Tpc) (Tpc) tAD Row address tAD Row address tAD Read command tAD Read A command tAD Row address tAD Column address (1-4) tCSD1 tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD BS tCASD2 tRASD2 tRWD tDQMD tRDS2 tRDH2 tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1) Rev. 5.00 Dec 12, 2005 page 959 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tr CKIO tAD A25 to A16 tAD A12 or A10 Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc) tAD Row address tAD Row address tAD Read command tAD tAD tAD A15 to A0 Row address tAD Column address (1-4) tAD tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 (read) BS tCASD2 tRASD2 tCSD1 tRWD tDQMD tRDS2 tRDH2 tBSD tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.26 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0) Rev. 5.00 Dec 12, 2005 page 960 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tr CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS tRWD Row address Tc1 (Trwl) (Tpc) tAD tAD Row address Write A command tAD tAD Row address Column address tAD tCSD1 tRWD tRASD2 tCASD2 CAS tDQMD DQMxx tWDD2 D31 to D0 tBSD BS tCASD2 tDQMD tWDH2 tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.27 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0) Rev. 5.00 Dec 12, 2005 page 961 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tr CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 tCSD1 CSn tRWD RD/WR tRASD2 RAS Trw Trw Tc1 (Trwl) (Trwl) (Tpc) (Tpc) tAD Row address tAD Row address tAD tAD Write A command tAD Row address tAD tAD Column address tCSD1 tRWD tRWD tRASD2 tCASD2 CAS tDQMD DQMxx tWDD2 D31 to D0 tBSD BS tCASD2 tDQMD tWDH2 tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.28 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1) Rev. 5.00 Dec 12, 2005 page 962 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tr CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) (Tpc) tAD Row address tAD Row address tAD Write command tAD Write A command tAD Row address tAD Column address (1-4) tCSD1 tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tWDD2 D31 to D0 tBSD BS tWDD2 tRASD2 tRWD tRWD tCASD2 tDQMD tWDH2 tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0) Rev. 5.00 Dec 12, 2005 page 963 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tr CKIO tAD A25 to A16 tAD A12 or A10 tAD A15 to A0 Trw Tc1 Tc2 Tc3 Td4 (Trwl) (Tpc) tAD Row address tAD Row address tAD Write command tAD Write A command tAD Row address tAD Column address (1-4) tCSD1 tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CAS tDQMD DQMxx tWDD2 D31 to D0 tBSD BS tWDD2 tRASD2 tRWD tRWD tCASD2 tDQMD tWDH2 tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.30 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0) Rev. 5.00 Dec 12, 2005 page 964 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tp Tpc TRr TRrw TRrw TRrw (Tpc) (Tpc) CKIO CKE tCSD1 CSn tRASD2 RAS3 tRASD2 (High) tCSD1 tRASD2 tRASD2 tCASD2 CAS tRWD RD/WR tRWD tCASD2 Figure 32.31 Synchronous DRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1) Rev. 5.00 Dec 12, 2005 page 965 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tp Tpc TRa1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO tCKED CKE tCSD1 CSn tRASD2 RAS3 tCASD2 CAS tRWD RD/WR tRWD tRWD tCASD2 tRASD2 tRASD2 tRASD2 tCSD1 tCKED Figure 32.32 Synchronous DRAM Self-Refresh Cycle (TPC = 0) Rev. 5.00 Dec 12, 2005 page 966 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics TRp1 CKIO TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 tAD A13 or A11 tAD A12 or A10 tAD A11 to A2 or A9 to A2 tCSD1 CSn tRWD RD/WR tRASD2 RAS tCASD2 CASxx tRASD2 tRASD2 tRWD tAD tAD tAD tAD tAD tAD tAD tAD tCSD1 tRWD tRASD2 tCASD2 D31 to D0 CKE tDAKD1 DACKn (High) tDAKD1 Figure 32.33 Synchronous DRAM Mode Register Write Cycle Rev. 5.00 Dec 12, 2005 page 967 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.7 PCMCIA Timing Tpcm1 Tpcm2 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15 to D0 (read) tWED WE1 (write) tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tWED tWDH4 tWDH1 tRSD tRWD tCSD1 tAD tRDH1 Figure 32.34 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 5.00 Dec 12, 2005 page 968 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tpcm0 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w tAD tCSD1 tRWD tRSD RD (read) tRSD tRDH1 tRDS1 D15 to D0 (read) tWED WE1 (write) tWED tWDH4 tWDD1 tWDH1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tBSD tDAKD1 tWTS tWTH tWTS tWTH WAIT Figure 32.35 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) Rev. 5.00 Dec 12, 2005 page 969 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tpcm1 CKIO tAD A25 to A4 tAD A3 to A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 tAD tAD tAD tAD tCSD1 tRWD tRSD tRSD tRSD tRDH1 tRDS1 tRDS1 tRDH1 D15 to D0 (read) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tBSD tBSD Note: Even though burst mode is set, write cycle operation is the same as in normal mode. Figure 32.36 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait) Rev. 5.00 Dec 12, 2005 page 970 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO tAD A25 to A4 tAD A3 to A0 tCSD1 CExx tRWD RD/WR tRSD RD (read) tRDS1 D15 to D0 (read) tBSD BS tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT tWTS tWTH tDAKD1 tBSD tBSD tBSD tRSD tRSD tRSD tRWD tCSD1 tAD tAD tAD tRDH1 tRDS1 tRDH1 Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. Figure 32.37 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1) Rev. 5.00 Dec 12, 2005 page 971 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tpci1 Tpci2 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR tICRSD ICIORD (read) tRDS1 D15 to D0 (read) tICWSD ICIOWR (write) tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tDAKD1 tBSD tICWSD tICRSD tRWD tCSD1 tAD tRDH1 tWDH4 tWDH1 Figure 32.38 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 5.00 Dec 12, 2005 page 972 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tpci0 CKIO tAD A25 to A0 tCSD1 CExx tRWD RD/WR Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w tAD tCSD1 tRWD tICRSD ICIORD (read) tRDS1 D15 to D0 (read) tICWSD ICIOWR (write) tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tWTS tWTH tWTS tWTH WAIT tIO16S tIO16H IOIS16 tBSD tICRSD tRDH1 tICWSD tWDH4 tWDH1 tDAKD1 Figure 32.39 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) Rev. 5.00 Dec 12, 2005 page 973 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Tpci0 CKIO tAD A25 to A4 tAD A0 tCSD1 CExx tRWD RD/WR Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w tAD tAD tAD tCSD1 tCSD1 tRWD tICRSD ICIORD (read) tRDS1 D15 to D0 (read) tICWSD ICIOWR (write) tWDD1 D15 to D0 (write) tBSD BS tDAKD1 DACKn tWTS tWTH WAIT tIO16S tIO16H IOIS16 tBSD tICRSD tICRSD tICRSD tRDH1 tRDS1 tRDH1 tICWSD tICWSD tICWSD tWDH3 tWDD2 tWDH4 tWDH1 tBSD tBSD tDAKD1 tWTS tWTH Figure 32.40 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing, WAITSEL = 1) Rev. 5.00 Dec 12, 2005 page 974 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.8 Peripheral Module Signal Timing Table 32.11 Peripheral Module Signal Timing Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Module RTC SCI Item Oscillation settling time Input clock cycle Asynchronization Clock synchronization tSCKR tSCKF tSCKW tTXD tRXS tRXH tRTSD tCTSS tCTSH tPORTD tPORTS1 tPORTH1 tPORTS2 tPORTH2 tPORTS3 tPORTH3 tDRQS tDREQH tDRAKD Symbol Min tROSC tSCYC -- 4 6 -- -- 0.4 -- 100 100 -- 100 100 -- 15 8 tcyc + 15 8 8 8 8 -- Max 3 -- -- 1.5 1.5 0.6 100 -- -- 100 -- -- 26 -- -- -- -- -- -- -- 14 32.46 ns 32.45 ns 32.44 tScyc ns 32.43 Pcyc* Unit s Pcyc* Figure 32.41 32.42 32.43 32.42 Input clock rise time Input clock fall time Input clock pulse width Transmission data delay time Receive data setup time (clock synchronization) Receive data hold time (clock synchronization) RTS delay time CTS setup time (clock synchronization) CTS hold time (clock synchronization) Port Output data delay time Input data setup time (1) Input data hold time (1) Input data setup time (2) Input data hold time (2) Input data setup time (3) Input data hold time (3) DMAC DREQ setup time DREQ hold time DRAK delay time 3 tcyc + 15 -- Note: * Pcyc stands for "peripheral clock (P) cycle." Rev. 5.00 Dec 12, 2005 page 975 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Stable oscillation RTC crystal oscillator VCC VCCmin tROSC Figure 32.41 Oscillation Settling Time at RTC Crystal Oscillator Power-on tSCKW SCK tScyc tSCKR tSCKF Figure 32.42 SCK Input Clock Timing tScyc SCK tTXD TxD (data transmissiion) RxD (data reception) RTS tCTSS CTS tCTSH tRXS tRXH tRTSD Figure 32.43 SCI I/O Timing in Clock Synchronous Mode Rev. 5.00 Dec 12, 2005 page 976 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics CKIO tPORTS1 tPORTH1 PORT A to H, J to M, SC (read) (bus clock:peripheral clock ratio = 1:1) PORT A to H, J to M, SC (read) (bus clock:peripheral clock ratio = 1:1/2) PORT A to H, J to M, SC (read) (bus clock:peripheral clock ratio = 1:1/4) PORT A to H, J to M, SC (write) tPORTS2 tPORTH2 tPORTS3 tPORTH3 tPORTD Figure 32.44 I/O Port Timing CKIO tDRQS DREQ tDRQH Figure 32.45 DREQ Input Timing CKIO tDRAKD DRAK tDRAKD Figure 32.46 DRAK Output Timing Rev. 5.00 Dec 12, 2005 page 977 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.9 H-UDI-Related Pin Timing Table 32.12 H-UDI-Related Pin Timing Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item TCK cycle time TCK high pulse width TCK low pulse width TCK rise/fall time TRST setup time TRST hold time TDI setup time TDI hold time TMS setup time TMS hold time TDO delay time ASEMD0 setup time ASEMD0 hold time Symbol tTCKcyc tTCKH tTCKL tTCKf tTRSTS tTRSTH tTDIS tTDIH tTMSS tTMSH tTDOD tASEMDH tASEMDS Min 50 12 12 -- 12 50 10 10 10 10 -- 12 12 Max -- -- -- 4 -- -- -- -- -- -- 19 -- -- Unit ns ns ns ns ns tcyc ns ns ns ns ns ns ns Figure 32.50 Figure 32.49 Figure 32.48 Figure Figure 32.47 tTCKcyc tTCKH TCK (input) VIH VIH 1/2 VccQ VIL VIL tTCKf VIH 1/2 VccQ tTCKf tTCKL Figure 32.47 TCK Input Timing Rev. 5.00 Dec 12, 2005 page 978 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics RESETP tTRSTS TRST tTRSTH Figure 32.48 TRST Input Timing (Reset Hold) TCK tTCKcyc tTDIS TDI tTMSS TMS tTDOD TDO tTMSH tTDIH Figure 32.49 H-UDI Data Transfer Timing RESETP tASEMDOS tASEMDOH ASEMD0 Figure 32.50 ASEMD0 Input Timing Rev. 5.00 Dec 12, 2005 page 979 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.10 LCDC Timing Table 32.13 LCDC Timing Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item LCLK input clock frequency LCLK input clock rise time LCLK input clock fall time LCLK input clock duty Clock (CL2/DCLK) cycle time Clock (CL2/DCLK) high-level width Clock (CL2/DCLK) low-level width Clock (CL2/DCLK) transition time (rise, fall) Data (LCD) delay time Data (LCD) transition time (rise, fall) Display enable (M/DISP) delay time Display enable (M/DISP) transition time (rise, fall) Horizontal sync. signal (CL1/Hsync) delay time Horizontal sync. singal (CL1/Hsync) transition time Vertical sync. signal (FLM/Vsync) delay time Vertical sync. signal (FLM/Vsync) transition time Symbol tFREQ tR tF tDUTY tCC tCHW tCLW tCT tDD tDT tID tIT tHD tHT tVD tVT Min -- -- -- 90 25 7 7 -- -3.5 -- -3.5 -- -3.5 -- -3.5 -- Max 50 3 3 110 -- -- -- 3 3 3 3 3 3 3 3 3 Unit MHz ns ns % ns ns ns ns ns ns ns ns ns ns ns ns Figure 32.51 Rev. 5.00 Dec 12, 2005 page 980 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics tCHW CL2/DCLK 0.8Vcc 0.2Vcc tCLW tCT tCT tCC tDD LCDD tDT 0.8Vcc 0.2Vcc tDT tID M/DISP tIT 0.8Vcc 0.2Vcc tIT tHD CL1/Hsync tHT 0.8Vcc 0.2Vcc tVD tVT 0.8Vcc 0.2Vcc tCC tHT tVT FLM/Vsync CL2/DCLK Figure 32.51 LCDC AC Specification Rev. 5.00 Dec 12, 2005 page 981 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.11 SIOF Module Signal Timing Table 32.14 SIOF Module Signal Timing Conditions: VCCQ = 2.6 to 3.6 V, VCC = 1.60 to 2.05 V, AVCC = 3.3 0.3 V, Ta = -20 to 75C Item SIOMCLK clock input cycle time SIOMCLK input high-level width SIOMCLK input low-level width SCK_SIO clock cycle time SCK_SIO output high-level width SCK_SIO output low-level width SIOFSYNC output delay time SCK_SIO input high-level width SCK_SIO input low-level width SIOFSYNC input setup time SIOFSYNC input hold time TXD_SIO output delay time RXD_SIO input setup time RXD_SIO input hold time Symbol tMCYC tMWH tMWL tSICYC tSWHO tSWLO tFSD tSWHI tSWLI tFSS tFSH tSTDD tSRDS tSRDH Min 30 0.4 x tMCYC 0.4 x tMCYC 2 x tPCYC 0.4 x tSICYC 0.4 x tSICYC -- 0.4 x tSICYC 0.4 x tSICYC 20 20 -- 20 20 Max -- -- -- -- -- -- 20 -- -- -- -- 20 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 32.52 32.52 32.52 32.53 to 32.57 32.53 to 32.56 32.53 to 32.56 32.53 to 32.56 32.57 32.57 32.57 32.57 32.53 to 32.57 32.53 to 32.57 32.53 to 32.57 Note: tPCYC is the cycle time (ns) of the peripheral clock (P) tMCYC SIOMCLK tMWH tMWL Figure 32.52 SIOMCLK Input Timing Rev. 5.00 Dec 12, 2005 page 982 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics tSICYC tSWHO SCK_SIO (output) tFSD SIOFSYNC (output) tSTDD TXD_SIO tSRDS RXD_SIO tSRDH tSTDD tFSD tSWLO Figure 32.53 SIOF Transmit/Receive Timing (Master Mode 1: Fall Sampling Time) tSICYC tSWLO tSWHO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD tSTDD TXD_SIO tSRDS tSRDH RXD_SIO Figure 32.54 SIOF Transmit/Receive Timing (Master Mode 1: Rise Sampling Time) Rev. 5.00 Dec 12, 2005 page 983 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics tSICYC tSWHO tSWLO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD TXD_SIO tSRDS RXD_SIO tSRDH tSTDD tSTDD tSTDD Figure 32.55 SIOF Transmit/Receive Timing (Master Mode 2: Fall Sampling Time) tSICYC tSWHO SCK_SIO (output) tFSD SIOFSYNC (output) tSTDD TXD_SIO tSRDS RXD_SIO tSRDH tSTDD tSTDD tSTDD tFSD tSWLO Figure 32.56 SIOF Transmit/Receive Timing (Master Mode 2: Rise Sampling Time) Rev. 5.00 Dec 12, 2005 page 984 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics tSICYC tSWHI SCK_SIO (input) tFSS SIOFSYNC (input) tSTDD TXD_SIO tSRDS RXD_SIO tSRDH tSTDD tFSH tSWLI Figure 32.57 SIOF Transmit/Receive Timing (Slave Mode 1 and Slave Mode 2) 32.3.12 USB Module Signal Timing Table 32.15 USB Module Signal Timing Conditions: VCCQ = 2.6 to 3.6 V, VCC = 1.60 to 2.05 V, AVCC = 3.3 0.3 V, Ta = -20 to 75C Item UCLK external input clock frequency (48 MHz) Clock rise time Clock fall time Symbol tFREQ tR48 tF48 Min 47.9 -- -- Max 48.1 6 6 Unit MHz ns ns Figure 32.58 tFREQ tHIGH UCLK (input) 90% 10% tLOW tR48 tF48 Figure 32.58 USB Clock Timing Rev. 5.00 Dec 12, 2005 page 985 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Table 32.16 USB Electrical Characteristics (Full-Speed) Item Transition time (rise)* 2 Transition time (fall)* 2 Symbol tR tF tRFM VCRS Min 4 4 90 1.3 Max 20 20 111 2.0 Unit ns ns % V State* 1 CL = 50 pF CL = 50 pF (TR/TF) -- Rise/fall time matching Output signal crossover power supply voltage Notes: Measured with edge control CEDGE = 47 pF and connection of direct resister Rs = 27 . 1. Value when CL = 50 pF unless specified otherwise. 2. Value within 10% to 90% of the signal power supply voltage. Table 32.17 USB Electrical Characteristics (Low-Speed) Item Transition time (rise)* Transition time (fall)* Rise/fall time matching Output signal crossover power supply voltage Symbol tR tF tRFM VCRS Min 75 -- 75 -- 80 1.3 Max -- 300 -- 300 125 2.2 Unit ns ns ns ns % V State CL = 200 pF CL = 600 pF CL = 200 pF CL = 600 pF (TR/TF) -- Notes: Measured with edge control CEDGE = 47 pF and connection of direct resister Rs = 27 . * Value within 10% to 90% of the signal power supply voltage. Rev. 5.00 Dec 12, 2005 page 986 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.13 AFEIF Module Signal Timing Table 32.18 AFEIF Module Signal Timing Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item AFE_SCLK clock input cycle time AFE_SCLK input high-level width AFE_SCLK input low-level width AFE_FS input time AFE_TXOUT output delay time AFE_RXIN input setup time AFE_RXIN input hold time AFE_HC1 output delay time AFE_RLYC output delay time Symbol tASCYC tASWH tASWL tAFSD tATDD tARDS tARDH tAHCD tARLYD Min 8 x tPCYC 0.4 x tASCYC 0.4 x tASCYC 0 20 Max 50 tPCYC + 20 3 x tPCYC + 20 tPCYC + 20 Unit ns ns ns ns ns ns ns ns ns 2 x tPCYC + 20 Note: tPCYC is the cycle time (ns) of the peripheral clock (P). Rev. 5.00 Dec 12, 2005 page 987 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics tASCYC tASWH tASWL AFE_SCLK tAFSD tAFSD AFE_FS tATDD AFE_TXOUT tARDS AFE_RXIN tAHCD AFE_HC1 tARLYD AFE_RLYC tAHCD tARDH Figure 32.59 AFEIF Module AC Timing Rev. 5.00 Dec 12, 2005 page 988 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.14 AC Characteristics Measurement Conditions * I/O signal reference level: 1.2 VccQ * Input pulse level: VssQ to 3.0 V (where RESETP, RESETM, ASEMD0, IRL3 to IRL0, ADTRG, PINT[15] to PINT[0], CA, NMI, IRQ5 to IRQ0, CKIO, and MD5 to MD0 are within VssQ to VccQ) * Input rise and fall times: 1 ns IOL LSI output pin CL DUT output VREF IOH Notes: 1. CL is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30pF: CKIO, RASxx, CASxx, CS0, CS2 to CS6, CE2A, CE2B, BACK 50pF: All other pins 2. IOL and IOH are the values shown in table 32.3. Figure 32.60 Output Load Circuit Rev. 5.00 Dec 12, 2005 page 989 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.3.15 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF or 50 pF) is connected to this LSI's pins is shown below. The graph shown in figure 32.61 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. If the connected load capacitance exceeds the range shown in figure 32.61, the graph will not be a straight line. +3 Delay Time [ns] +2 +1 +0 +0 +10 +20 +30 +40 +50 Load Capacitance [pF] Figure 32.61 Load Capacitance vs. Delay Time Rev. 5.00 Dec 12, 2005 page 990 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics 32.4 A/D Converter Characteristics Table 32.19 lists the A/D converter characteristics. Table 32.19 A/D Converter Characteristics Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Resolution Conversion time Analog input capacitance Permissible signal-source (singlesource) impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 15 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 3.0 2.0 2.0 0.5 4.0 Unit bits s pF k LSB LSB LSB LSB LSB 32.5 D/A Converter Characteristics Table 32.20 lists the D/A converter characteristics. Table 32.20 D/A Converter Characteristics Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C Item Resolution Conversion time Absolute accuracy Min 8 -- -- Typ 8 -- 2.5 Max 8 10.0 4.0 Unit bits s LSB 20 pF capacitive load 2 M resistance load Test Conditions Rev. 5.00 Dec 12, 2005 page 991 of 1034 REJ09B0254-0500 Section 32 Electrical Characteristics Rev. 5.00 Dec 12, 2005 page 992 of 1034 REJ09B0254-0500 Appendix A Pin Functions Appendix A Pin Functions A.1 Pin Functions Pin Functions Signal Name (Initial Status: Bold) XTAL2 EXTAL2 XTAL EXTAL CAP1, CAP2 CKIO2 CKIO System control STATUS0/PTJ[6], STATUS1/PTJ[7] RESETP, RESETM RESETP CA Scan_testen MD0 to MD5 ASEMD0 Interrupts NMI IRQ0/IRL0 IRQ0 IRL0/PTH[0] to IRL0 IRQ3/IRL3 IRL3/PTH[3] IRQ3 IRL3 IRQ4/PTH[4] IRQ4 Bus functions BREQ BACK D31/PTB[7] to D24/PTB[0], D23/PTA[7] to D16/PTA[0] D15 to D0 2 3 179 180 171, 174 19 189 185, 186 220, 147 221 224 169, 5, 6, 222, 223, 15 150 7 8, 9, 10, 11 12 16 17 21 to 28, 30, 32 to 34, 36, 38 to 40 41, 43, 45 to 52, 54, 56 to 60 Pin No. (HQFP) I/O O I O I -- O(Z) IO O/IO I I I I I I I/I/I I/I I O IO/IO PowerManual On Reset Reset O I O I -- O IO O I I I I I I V V I H Z O I O I -- O(Z) IO O/P I I I I I I I/I/I I/I I H K/P Standby O I O I -- O(Z) IO O/K I I I I I I I/I/Z I/Z I H Z/K Release/ Open Bus Privileges O I O I -- O(Z) IO O/P I I I I I I I/I/I I/I I L Z/P Table A.1 Type Clock and oscillation related IO Z K Z Z Rev. 5.00 Dec 12, 2005 page 993 of 1034 REJ09B0254-0500 Appendix A Pin Functions Signal Name (Initial Status: Bold) A0 to A25 Pin No. (HQFP) 61 to 63, 65, 67 to 74, 76, 78 to 85, 87, 89, 90, 92, 94 95 96 97 98 99, 101 PowerManual On Reset Reset Z O Release/ Open Bus Privileges Z Type Bus functions I/O O Standby Z(L) BS/PTK[4] BS RD WE0/DQMLL WE0 WE1/DQMLU/WE WE1 WE2/DQMUL/ICIORD/ WE2 PTK[6], WE3/DQMUU/ICIOWR/ WE3 PTK[7] RDWR CS0, CS2, CS0 CS2 CS3 CS4/PTK[2] CS4 CS5/CE1A CS5 CE1A/PTK[3] CE1A CS6/CE1B CS6 CE1B CE2A/PTE[4], CE2B/PTE[5] CKE/PTK[5] Reserved/CAS/PTJ[2] WAIT IOIS16/PTG[7] RAS3/PTJ[0], RAS3 Reserved/PTJ[1], Reserved/PTJ[3]*3, Reserved/PTJ[4]*3, Reserved/PTJ[5]*3 AFE/USB digital/port related AFE_HC1/ USB1d_DPLS/PTK[0] AFE_RLYCNT/ AFE_RLYCNT USB1d_DMNS/PTK[1] AFE_SCLK/ USB1d_TXDPLS O/IO O O/O O/O/O O/O/O/ IO H H H H H O/P O O/O O/O/O Z(H)/K Z(H) Z(H)/Z(H) Z(H)/Z(H)/ Z(H) Z/P Z Z/Z Z/Z/Z Z/Z/Z/P O/O/O/P Z(H)/Z(H)/ O/K 103 105, 106, 107 108 109 110 111, 112 128 131 146 149 129, 130, 133, 135, 136 O O O/IO O/O/IO O/O O/IO O/IO O/O/IO I I/I O/IO H H H H H V H H Z V H O O O/P O/O/P O/O O/P O/P O/O/P Z I/I O/P Z(H) Z(H) Z(H)/K Z(H)/Z(H)/ K Z(H)/Z(H) Z(H)/K O/K O/Z(H)/K Z Z/Z(V) Z(H)/K Z Z Z/P Z/Z/P Z/Z Z/P O/P O/Z(H)/P Z I/I Z(H)/P 113 114 116 O/I/IO O/I/IO I/O L L I O/I/P O/I/P I/O Z/Z/K O/Z/K Z/O O/I/P O/I/P I/O Rev. 5.00 Dec 12, 2005 page 994 of 1034 REJ09B0254-0500 Appendix A Pin Functions Signal Name (Initial Status: Bold) Pin No. (HQFP) PowerManual On Reset Reset V I/I/I/O Release/ Open Bus Privileges I/I/I/O Type AFE/USB digital/port related I/O I/I/I/O Standby Z(V)/I/Z/O PTM[7]/PINT[7]/ 118, 119, AFE_FS/USB1d_RCV, 120 PTM[6]/PINT[6]/ AFE_RXIN/USB1d_SPEED, PTM[5]/PINT[5]/ AFE_TXOUT/ USB1d_TXSE0 PTM[4]/PINT[4]/ AFE_RDET USB1d_SUSPEND 121 122 143 160, 162, 163, 164 I/I/I O IO/O I/I/I V O V/O*1 V/I*1 I/I/I O P/O I/I/I Z(V)/I/Z O K/O Z/I/I I/I/I O P/O I/I/I JTAG PTE[0]/TDO*1 PTF[7]/PINT[15]/TRST*1, TRST PTF[6]/PINT[14]/TMS*1, PTF[5]/PINT[13]/TDI*1, PTF[4]/PINT[12]/TCK*1 DMAC DREQ0/PTD[4] DRAK0/PCC0RESET DACK0/PCC0DRV 218 144 145 104 176 153, 154, 156, 158 I/I O/O O/O IO/I/O I/I/I I/I/O V H H V/O*1 V/V*1 V/O*1 Z/I O/O O/O P/I/O I/I/I I/I/O Z/Z(V) Z(H)/Z Z/Z K/Z/O Z/Z(V)/Z Z/Z(V)/O I/I O/O O/O P/I/O I/I/I I/I/O Port/PCC/ PTE[7]/PCC0RDY/ AUD related AUDSYNC*1 PCC0WAIT/ PTH[6]/AUDCK*1 PCC0BVD2/ PTG[3]/AUDATA[3]*1, PCCBVD1/ PTG[2]/AUDATA[2]*1, PCC0CD2/ PTG[1]/AUDATA[1]*1, PCC0CD1/ PTG[0]/AUDATA[0]*1 PTG[4] PTF[3]/PINT[11] PCCREG/PTF[2] PTG[5]/ASEBRKAK*1 ASEBRKAK PCC0VS1/PTF[1], PCC0VS2/PTF[0] 152 165 166 151 167, 168 I I/I O/I I/O I/I V V V V/O*1 V I I/I O/I I/O I/I Z(V) Z(V)/I Z/Z(V) Z(V)/O Z/Z(V) I I/I O/I I/O I/I Rev. 5.00 Dec 12, 2005 page 995 of 1034 REJ09B0254-0500 Appendix A Pin Functions Signal Name (Initial Status: Bold) PTD[5]/CL1, PTD[7]/DON, PTE[6]/M_DISP, PTE[3]/FLM, PTH[7]/CL2 VEPWC, VCPWC Pin No. (HQFP) 138, 140, 141, 142, 187 PowerManual On Reset Reset V P/L Release/ Open Bus Privileges P/O Type LCDC related I/O IO/O Standby K/L*2 13, 14 O O/I/I O/I O/IO/I O/IO I/I/I I/IO IO/IO IO/IO I/I I/I I/I/I O/O IO/IO O/O O/O IO/O I/I I IO L V V V V V I I I Z I V Z V H L V I I L L L/I/I L/I L/P/I L/P I/I/I Z/P Z/P Z/P Z/I Z/I I/Z/I Z/O Z/P Z/O O/O P/O Z/Z Z L L*2 K /Z(V)/I K*2/Z(V) K*2/K/I K*2/K Z/Z/Z(V) Z/K Z/K K/K Z/Z Z/Z Z(V)/Z/I Z/K V/K Z/K Z/O K/O Z/Z Z K *2 O O/I/I O/I O/P/I O/P I/I/I I/P IO/P IO/P I/Z I/Z I/I/I O/Z IO/P O/O O/O P/O I/I I IO LCD15/PTM[3]/PINT[10] to 181, 182, LCD13/PTM[1]/PINT[8] 183 LCD12/PTM[0] LCD11/PTC[7]/PINT[3] to LCD8/PTC[4]/PINT[0] LCD7/PTD[3] to LCD0/PTD[0] LCLK/UCLK/PTD[6] Serial related SIOMCLK/SCPT[3] SCK_SIO/SCPT[5] SIOFSYNC/SCPT[6] RxD0/SCPT[0], RxD2/SCPT[4] RxD_SIO/SCPT[2] SCPT[7]/CTS2/IRQ5 TxD0/SCPT[0], TxD2/SCPT[4] SCK0/SCPT[1] TxD_SIO/SCPT[2] RTS2/USB1d_TXENL RTS2 USB related PTE[2]/USB1_pwr_en, PTE[1]/USB2_pwr_en USB1_ovr_crnt/ USB1_ovr_crnt USBF_VBUS USB2_ovr_crnt USB1_P(analog), USB1_M(analog), USB2_P(analog), USB2_M(analog) 184 204, 205, 206, 208 210 to 217 219 194 196 197 198, 201 199 203 191, 195 192 193 125 126, 127 123 124 226, 227, 229, 230 Rev. 5.00 Dec 12, 2005 page 996 of 1034 REJ09B0254-0500 Appendix A Pin Functions Signal Name (Initial Status: Bold) ADTRG/PTH[5] ADTRG AN[2]/PTL[2], AN[3]/PTL[3], AN[4]/PTL[4], AN[5]/PTL[5] ADC/DAC Power supply AN[6]/PTL[6]/DA[1], AN[7]/PTL[7]/DA[0] AVcc_USB AVss_USB AVss AVcc Vcc-PLL1, Vcc-PLL2 Vss-PLL1, Vss-PLL2 Vcc-RTC Vss-RTC Vcc Pin No. (HQFP) 148 233, 234, 235, 236 PowerManual On Reset Reset V Z I/I Z/I Release/ Open Bus Privileges I/I I/I Type ADC I/O I/I I/I Standby I/Z Z/Z 238, 239 225, 231 228 232, 240 237 170, 175 172, 173 1 4 37, 93, 139, 157, 178, 202 35, 91, 137, 155, 177, 200 20, 31, 44, 55, 66, 77, 88, 102, 117, 134, 161, 190, 209 18, 29, 42, 53, 64, 75, 86, 100, 115, 132, 159, 188, 207 I/I/O -- -- -- -- -- -- -- -- -- Z -- -- -- -- -- -- -- -- -- Z/I/Z -- -- -- -- -- -- -- -- -- Z/Z/O -- -- -- -- -- -- -- -- -- I/I/O -- -- -- -- -- -- -- -- -- Vss -- -- -- -- -- VccQ -- -- -- -- -- VssQ -- -- -- -- -- Notes: 1. The initial status is determined from the level of ASEMD0 when resetting. 2. In accordance with the power management sequence described in section 25.3.6, Power Management Registers of this manual, make sure to clear the DON register to 0 and interrupt the power supply before entering the standby mode. 3. The initial status of PTJ3 to PTJ5 is high level output, but it may change briefly to low level when resetting. Rev. 5.00 Dec 12, 2005 page 997 of 1034 REJ09B0254-0500 Appendix A Pin Functions I: O: H: L: Z: P: K: V: ( ): Input (input buffer on) Output (output buffer on) High-level output Low-level output High-impedance (input and output buffers off) I or O according to setting of register Input pins are high-impedance, output pin status is retained Input/output buffer off, pull-up MOS on Based on status of internal registers (Refer to the register tables for information on individual pins.) Rev. 5.00 Dec 12, 2005 page 998 of 1034 REJ09B0254-0500 Appendix A Pin Functions A.2 Treatment of Unused Pins Treatment of Unused Pins Signal Name (Initial Status: Bold) XTAL2 EXTAL2 XTAL EXTAL CAP1, CAP2 CKIO2 CKIO 2 3 179 180 171, 174 19 189 185, 186 220, 147 221 224 169, 5, 6, 222, 223, 15 150 7 8, 9, 10, 11 12 16 17 Pin No (HQFP) Pin No (CSP) B4 A2 V4 V2 U3, W4 C7 R1 U1, R2 H1, T11 G4 G1 T5, A3, B5, G3, G2, C6 T10 A4 C4, A5, D4, C5 D5 D6 A7 I/O O I O I -- O IO O/IO I I I I I I I/I/I I/I I O Treatment when Not Used Open Connect to Vcc Open Pull up Open Open Open Open Pull up Pull up Pull up Always used Pull up Pull up Pull up Pull up Pull up Open Table A.2 Type Clock and oscillation related System control STATUS0/PTJ[6], STATUS1/PTJ[7] RESETP, RESETP RESETM CA Scan_testen MD0 to MD5 ASEMD0 Interrupts NMI IRQ0/IRL0 IRQ0 IRL0/PTH[0] to IRL0 IRQ3/IRL3 IRL3/PTH[3] IRQ3 IRL3 IRQ4/PTH[4] IRQ4 Bus functions BREQ BACK D31/PTB[7] to D24/PTB[0], D23/PTA[7] to D16/PTA[0] 21 to 28, 30, 32 to A8, B8, C8, D8, 34, 36, 38 to 40 A9, B9, D9, C9, D10, B10, C11, D11, A11, C12, B12, A12 41, 43, 45 to 52, 54, 56 to 60 D13, D11, D14, C14, B14, A14, D15, C15, C17, A15, A16, A17, B17, A18, B16, B18 IO/IO Open D15 to D0 IO Open Rev. 5.00 Dec 12, 2005 page 999 of 1034 REJ09B0254-0500 Appendix A Pin Functions Type Bus functions Signal Name (Initial Status: Bold) A0 to A25 Pin No (HQFP) Pin No (CSP) I/O O Treatment when Not Used Open 61 to 63, 65, 67 to A19, D18, B19, 74, 76, 78 to 85, C19, D19, D17, 87, 89, 90, 92, 94 E19, D16, E17, E16, F19, F18, F16, G18, G17, G16, H19, H18, H17, H16, J19, J16, K19, K16, K18,L16 95 96 97 98 L18 L19 M16 M17 M18 N18 P16, P17, P18 P19 R16 R17 U17, R19 U16 U15 V11 W10 W15, T16, W14, U14, T14 BS/PTK[4] BS RD/WR WR WE0/DQMLL WE0 WE1/DQMLU/WE WE1 O/IO O O/O Open Open Open O/O/O Open O/O/O/I Open O O O O/IO O/O O/IO O/IO I I/I O/IO Open Open Open Open Open Open Pull up Open Open WE2/DQMUL/ICIORD/PTK[6], 99, 101 WE2 WE3/DQMUU/ICIOWR/PTK[7] WE3 RD/WR WR CS0, CS2, CS0 CS2 CS3 CS4/PTK[2] CS4 CS5/CE1A CS5 CE1A/PTK[3] CE1A CS6/CE1B CS6 CE1B CE2A/PTE[4], CE2B CE2B/PTE[5] CE2A CKE/PTK[5] Reserved/CAS/PTJ[2] WAIT IOIS16/PTG[7] IOIS16 RAS3/PTJ[0], RAS3 Reserved/PTJ[1], Reserved/PTJ[3], Reserved/PTJ[4], Reserved/PTJ[5] 103 105, 106, 107 108 109 110 111, 112 128 131 146 149 129, 130, 133, 135, 136 O/O/IO Open O/O/IO Open Rev. 5.00 Dec 12, 2005 page 1000 of 1034 REJ09B0254-0500 Appendix A Pin Functions Type AFE/USB digital/port related Signal Name (Initial Status: Bold) Pin No (HQFP) Pin No (CSP) T17, T19 I/O Treatment when Not Used AFE_HC1/USB1d_DPLS/ 113, 114 PTK[0], AFE_RLYCNT/USB1d_DMNS/ AFE_RLYCNT PTK[1] AFE_SCLK/USB1d_TXDPLS 116 PTM[7]/PINT[7]/AFE_FS/ 118, 119, 120 USB1d_RCV, PTM[6]/PINT[6]/AFE_RXIN/ USB1d_SPEED, PTM[5]/PINT[5]/AFE_TXOUT/ USB1d_TXSE0 PTM[4]/PINT[4]/AFE_RDET 121 O/I/IO Open U19 V19, T18, V18 I/IO Pull up I/I/I/O Open W19 I/I/I O IO/O I/I/I Open Open Open Pull up JTAG Reserved/USB1d_SUSPEND 122 V16 PTE[0]/TDO*1 143 U12 160, 162, 163, 164 W8, U7, V7, W7 PTF[7]/PINT[15]/TRST*1, TRST PTF[6]/PINT[14]/TMS*1, PTF[5]/PINT[13]/TDI*1, PTF[4]/PINT[12]/TCK*1 DREQ0/PTD[4] DREQ0 DRAK0/PCC0RESET, DACK0/PCC0DRV 218 144, 145 H3 T12, W11 N19 W3 DMAC I/I O/O Pull up Open PTE[7]/PCC0RDY/AUDSYNC 104 Port/PCC/ AUD related PCC0WAIT/PTH[6]/AUDCK*1 176 PCC0BVD2/PTG[3]/ AUDATA[3]*1, PCCBVD1/PTG[2]/ AUDATA[2]*1, PCC0CD2/PTG[1]/ AUDATA[1]*1, PCC0CD1/PTG[0]/ AUDATA[0]*1 PTG[4] PTF[3]/PINT[11] PCCREG/PTF[2] PTG[5]/ASEBRKAK*1 ASEBRKAK PCC0VS1/PTF[1], PCC0VS2/PTF[0] IO/I/O Open I/I/I I/I/O Pull up Open 153, 154, 156, 158 U9, T9, W9, U8 152 165 166 151 167, 168 V10 T6 U6 U10 V6, W6 I I/I O/I I/O I/I Open Open Open Open Open Rev. 5.00 Dec 12, 2005 page 1001 of 1034 REJ09B0254-0500 Appendix A Pin Functions Type LCDC related Signal Name (Initial Status: Bold) Pin No (HQFP) Pin No (CSP) V13, T13, W12, V12, T1 A6, B6 W1, T2, V1 U2 I/O IO/O Treatment when Not Used Open PTD[5]/CL1, PTD[7]/DON, 138, 140, 141, PTE[6]/M_DISP, PTE[3]/FLM, 142, 187 CL2/PTH[7] VEPWC, VCPWC LCD15/PTM[3]/PINT[10] to LCD13/PTM[1]/PINT[8] LCD12/PTM[0] LCD11/PTC[7]/PINT[3] to LCD8/PTC[4]/PINT[0] 13, 14 181, 182, 183 184 O O/I/I O/I Open Open Open 204, 205, 206, 208 M4, L1, L2, L3 K4, K3, K2, J3, J4, J2, J1, H4 H2 P2 P4, N1 N2, M1, N3 O/IO/I Open O/IO I/I/I I/IO Open Pull up Pull up LCD7/PTD[3] to LCD0/PTD[0] 210 to 217 LCLK/UCLK/PTD[6] Serial related SIOMCLK/SCPT[3] SCK_SIO/SCPT[5], SIOFSYNC/SCPT[6] RxD0/SCPT[0], RxD2/SCPT[4], RxD_SIO/SCPT[2] SCPT[7]/CTS2/IRQ5 SCK0/SCPT[1] TxD_SIO/SCPT[2] RTS2/USB1d_TXENL RTS2 USB related PTE[2]/USB1_pwr_en, PTE[1]/USB2_pwr_en USB1_ovr_crnt/USBF_VBUS USB1_ovr_crnt USB2_ovr_crnt USB1_P(analog), USB1_M(analog), USB2_P(analog), USB2_M(analog) ADC ADTRG/PTH[5] ADTRG AN[2]/PTL[2], AN[3]/PTL[3], AN[4]/PTL[4], AN[5]/PTL[5] ADC/DAC AN[6]/PTL[6]/DA[1], AN[7]/PTL[7]/DA[0] 219 194 196, 197 198, 201, 199 IO/IO Pull up I/I Pull up 203 192 193 125 126, 127 123 124 M3 R3, P3, P1 R4 P1 W17 V15, W16 W18 V17 I/I/I O/O O/O O/O IO/O I/I I IO Pull up Open Open Open Open Pull up Pull up Open*2 TxD0/SCPT[0], TxD2/SCPT[4] 191, 195, 193 IO/IO Open 226, 227, 229, 230 F3, F2, E4, E3 148 U11 I/I I/I I/I/O Pull up Open Open*3 233, 234, 235, 236 D3, D1, E2, C1 238, 239 B1, D2 Rev. 5.00 Dec 12, 2005 page 1002 of 1034 REJ09B0254-0500 Appendix A Pin Functions Type Power supply Signal Name (Initial Status: Bold) AVcc_USB AVss_USB AVss AVcc Vcc-PLL1, Vcc-PLL2 Vss-PLL1, Vss-PLL2 Vcc-RTC Vss-RTC Vcc Vss VccQ Pin No (HQFP) 225, 231 228 232, 240 237 170, 175 172, 173 1 4 37, 93, 139, 157, 178, 202 35, 91, 137, 155, 177, 200 Pin No (CSP) F4, C3 F1 E1, B2 C2 U5, V5 W5, U4 A1 B3 D2, L17, U13, T8, W2, M2 B11, K17, W13, V9, V3, N4 I/O -- -- -- -- -- -- -- -- -- -- -- Treatment when Not Used VccQ VssQ VssQ VccQ Vcc Vcc Vcc Vcc Vcc Vss VccQ 20, 31, 44, 55, 66, D7, C10, A13, 77, 88, 102, 117, B15, E18, G19, 134, 161, 190, 209 J17, N17, U18, V14, T7, T4, K1 18, 29, 42, 53, 64, B7, A10, C13, 75, 86, 100, 115, C16, C18, F17, 132, 159, 188, 207 J18, M19, R18, T15, V8, T3, L4 VssQ -- VssQ Notes: For unused pins, the above table shows examples of processing. The indicated settings may not be suitable in some cases. 1. Valid when ASEMD0 is low level. 2. In cases where either USB function is used, this should be fixed as per the not used and not active examples. 3. A/D pin functions are assumed. Rev. 5.00 Dec 12, 2005 page 1003 of 1034 REJ09B0254-0500 Appendix A Pin Functions A.3 Pin Status when Accessing Address Spaces Pin Status (Normal Memory/Little Endian) 8-Bit Bus Width Pin Byte/Word/ Longword Access Enabled R Low W High R High W Low Enabled High High R High W Low R High W High R High W High Byte Access (Address 2n) Enabled Low High High Low Enabled High High High Low High High High High High High High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n+1) Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 Word/Longword Access Enabled Low High High Low Enabled High High High Low High Low High High High High High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 Table A.3 CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R High W High CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Rev. 5.00 Dec 12, 2005 page 1004 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.3 Pin Status (Normal Memory/Little Endian) (cont) 32-Bit Bus Width Pin Byte Word Word Byte Byte Byte Access Access Access Access Access Access Longword (Address (Address (Address (Address (Address (Address Access 4n) 4n+1) 4n+2) 4n+3) 4n) 4n+2) Enabled R Low W High R High W Low Enabled High High R High W Low R High W High R High W High Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Disabled Address Enabled Low High High Low Enabled High High High High High High High Low High High High High Disabled Disabled Address Invalid data Enabled Low High High Low Enabled High High High High High High High High High Low High High Disabled Disabled Address Invalid data Invalid data Enabled Low High High Low Enabled High High High Low High Low High High High High High High Disabled Disabled Address Enabled Low High High Low Enabled High High High High High High High Low High Low High High Disabled Disabled Address Enabled Low High High Low Enabled High High High Low High Low High Low High Low High High Disabled Disabled Address Valid data Valid data CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R High W High CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 High High Disabled Disabled Address Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Valid data Invalid data Invalid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Valid data Valid data Valid data Valid data Invalid data Notes: 1. Disabled when the wait setting of the WCR2 register is 0. 2. Unused pins can be switched to port function, pull-up. Rev. 5.00 Dec 12, 2005 page 1005 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.4 Pin Status (Normal Memory/Big Endian) 8-Bit Bus Width Pin Byte/Word/ Longword Access Enabled R Low W High R High W Low Enabled High High R High W Low R High W High R High W High Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n+1) Enabled Low High High Low Enabled High High High Low High High High High High High High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 Word/Longword Access Enabled Low High High Low Enabled High High High Low High Low High High High High High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R High W High CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Rev. 5.00 Dec 12, 2005 page 1006 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.4 Pin Status (Normal Memory/Big Endian) (cont) 32-Bit Bus Width Pin Byte Word Word Byte Byte Byte Access Access Access Access Access Access Longword (Address (Address (Address (Address (Address (Address Access 4n) 4n+1) 4n+2) 4n+3) 4n) 4n+2) Enabled R Low W High R High W Low Enabled High High R High W High R High W High R High W High Enabled Low High High Low Enabled High High High High High High High Low High High High High Disabled Disabled Address Invalid data Invalid data Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Disabled Address Invalid data Enabled Low High High Low Enabled High High High Low High High High High High High High High Disabled Disabled Address Enabled Low High High Low Enabled High High High High High High High Low High Low High High Disabled Disabled Address Enabled Low High High Low Enabled High High High Low High Low High High High High High High Disabled Disabled Address Enabled Low High High Low Enabled High High High Low High Low High Low High Low High High Disabled Disabled Address CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R High W Low CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 High High Disabled Disabled Address Invalid data Invalid data Invalid data Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Valid data Invalid data Invalid data Valid data Valid data Valid data Valid data Valid data Valid data Invalid data Invalid data Valid data Valid data Valid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Notes: 1. Disabled when the wait setting of the WCR2 register is 0. 2. Unused pins can be switched to port function, pull-up. Rev. 5.00 Dec 12, 2005 page 1007 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.5 Pin Status (Burst ROM/Little Endian) 8-Bit Bus Width Pin Byte/Word/ Longword Access Enabled R Low W-- R High W-- Enabled High High R High W-- R High W-- R High W-- Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n+1) Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 Word/Longword Access Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R High W-- CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Rev. 5.00 Dec 12, 2005 page 1008 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.5 Pin Status (Burst ROM/Little Endian) (cont) 32-Bit Bus Width Pin Byte Word Word Byte Byte Byte Access Access Access Access Access Access Longword (Address (Address (Address (Address (Address (Address Access 4n) 4n+1) 4n+2) 4n+3) 4n) 4n+2) Enabled R Low W-- R High W-- Enabled High High R High W-- R High W-- R High W-- R High W-- High High Disabled Disabled Address Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Invalid data Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Valid data Valid data CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Valid data Invalid data Invalid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Valid data Valid data Valid data Valid data Invalid data Notes: 1. Disabled when the wait setting of the WCR2 register is 0. 2. Unused pins can be switched to port function, pull-up. Rev. 5.00 Dec 12, 2005 page 1009 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.6 Pin Status (Burst ROM/Big Endian) 8-Bit Bus Width Pin Byte/Word/ Longword Access Enabled R Low W-- R High W-- Enabled High High R High W-- R High W-- R High W-- R High W-- High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z*2 16-Bit Bus Width Byte Access (Address 2n+1) Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z*2 Word/Longword Access Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z*2 CS6 to CS2, CS0 RD RD/WR BS RAS3L CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 Rev. 5.00 Dec 12, 2005 page 1010 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.6 Pin Status (Burst ROM/Big Endian) (cont) 32-Bit Bus Width Pin Byte Word Word Byte Byte Byte Access Access Access Access Access Access Longword (Address (Address (Address (Address (Address (Address Access 4n) 4n+1) 4n+2) 4n+3) 4n) 4n+2) Enabled R Low W-- R High W-- Enabled High High R High W-- R High W-- R High W-- Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Invalid data Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Invalid data Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address Enabled Low -- High -- Enabled High High High -- High -- High -- High -- High High Disabled Disabled Address CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R High W-- CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 High High Disabled Disabled Address Invalid data Invalid data Invalid data Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Valid data Invalid data Invalid data Valid data Invalid data Valid data Valid data Valid data Valid data Valid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Notes: 1. Disabled when the wait setting of the WCR2 register is 0. 2. Unused pins can be switched to port function, pull-up. Rev. 5.00 Dec 12, 2005 page 1011 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.7 Pin Status (Synchronous DRAM/Little Endian) 32-Bit Bus Width Pin Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword (Address (Address (Address (Address (Address (Address Access 4n) 4n+1) 4n+2) 4n+3) 4n) 4n+2) Enabled R High W High R High W Low Enabled Low/ High*1 High/ Low*1 R Low W Low R High W High R High W High Enabled High High High Low Enabled Low/ High*1 High/ Low*1 High High Low Low High High High High High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 High High High High Low Low High High High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 High High High High High High Low Low High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 Low Low Low Low High High High High High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 High High High High Low Low Low Low High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 Low Low Low Low Low Low Low Low High High High*2 Disabled Disabled CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R High W High CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 High High High*2 Disabled Disabled Address Address Address Address Address Address Address command command command command command command command Valid data Invalid data Invalid data Invalid data Invalid data Invalid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Valid data Valid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Valid data Valid data Valid data Valid data Invalid data Notes: 1. Low 32MB access/High 32MB access 2. Normally High, but Low during self-refresh. Rev. 5.00 Dec 12, 2005 page 1012 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.8 Pin Status (Synchronous DRAM/Big Endian) 32-Bit Bus Width Pin Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword (Address (Address (Address (Address (Address (Address Access 4n) 4n+1) 4n+2) 4n+3) 4n) 4n+2) Enabled R High W High R High W Low Enabled Low/ High*1 High/ Low*1 R High W High R High W High R High W High Enabled High High High Low Enabled Low/ High*1 High/ Low*1 High High High High Low Low High High High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 High High Low Low High High High High High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 Low Low High High High High High High High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 High High High High Low Low Low Low High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 Low Low Low Low High High High High High High High*2 Disabled Disabled Enabled High High High Low Enabled Low/ High*1 High/ Low*1 Low Low Low Low Low Low Low Low High High High*2 Disabled Disabled CS6 to CS2, CS0 RD RD/WR BS RAS3 CAS WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD WE3/DQMUU/ICIOWR R Low W Low CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 High High High*2 Disabled Disabled Address Address Address Address Address Address Address command command command command command command command Valid data Invalid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Invalid data Invalid data Valid data Valid data Valid data Invalid data Invalid data Invalid data Invalid data Valid data Valid data Valid data Valid data Valid data Valid data Notes: 1. Low 32MB access/High 32MB access 2. Normally High, but Low during self-refresh. Rev. 5.00 Dec 12, 2005 page 1013 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.9 Pin Status (PCMCIA/Little Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n+1) High Low High High Low Enabled High High High High High Low High High High High Low High Disabled PCMCIA/IO Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High Low High High Low Low High Disabled Word/ Longword Access Enabled High High High Low Enabled High High High High High High Low High High Low Low High Disabled Pin Byte/ Byte Word/ Access Longword (Address Access 2n) Enabled R Low W High Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Byte/ Byte Word/ Word/ Access Longword Longword (Address Access Access 2n) Enabled Low High High Low Enabled High High High High High Low High High High High Low High Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled CS6 to CS2, CS0 RD RD/WR R High W Low BS RAS3 CAS WE0/DQMLL Enabled High High R High W High WE1/DQMLU/WE R High W Low WE2/DQMUL/ICIORD R High W High WE3/DQMUU/ICIOWR R High W High CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 High High Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Enabled Address Invalid data Valid data High-Z* 2 Enabled Address Valid data Valid data High-Z* 2 Rev. 5.00 Dec 12, 2005 page 1014 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.9 Pin Status (PCMCIA/Little Endian) (cont) PCMCIA Memory Interface (Area 6) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n+1) High Low High High Low Enabled High High High High High Low High High High High High Low Disabled PCMCIA/IO Interface (Area 6) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High Low High High Low High Low Disabled Word/ Longword Access Enabled High High High Low Enabled High High High High High High Low High High Low High Low Disabled Pin Byte/ Byte Word/ Access Longword (Address Access 2n) Enabled R Low W High Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Byte/ Byte Word/ Word/ Access Longword Longword (Address Access Access 2n) Enabled Low High High Low Enabled High High High High High Low High High High High High Low Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled CS6 to CS2, CS0 RD RD/WR R High W Low BS RAS3 CAS WE0/DQMLL Enabled High High R High W High WE1/DQMLU/WE R High W Low WE2/DQMUL/ICIORD R High W High WE3/DQMUU/ICIOWR R High W High CE2A CE2B CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 High High Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Enabled Address Invalid data Valid data High-Z* 2 Enabled Address Valid data Valid data High-Z* 2 Notes: 1. Disabled when the wait setting of the WCR2 register is 0. 2. Unused pins can be switched to port function, pull-up. Rev. 5.00 Dec 12, 2005 page 1015 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.10 Pin Status (PCMCIA/Big Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width Pin 16-Bit Bus Width Byte Access (Address 2n+1) High Low High High Low Enabled High High High High High Low High High High High Low High Disabled PCMCIA/IO Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High Low High High Low Low High Disabled Word/ Longword Access Enabled High High High Low Enabled High High High High High High Low High High Low Low High Disabled Byte/ Byte Word/ Access Longword (Address Access 2n) Enabled R Low W High Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Byte/ Byte Word/ Word/ Access Longword Longword (Address Access Access 2n) Enabled Low High High Low Enabled High High High High High Low High High High High Low High Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled CS6 to CS2, CS0 RD RD/WR R High W Low BS RAS3 CAS WE0/DQMLL Enabled High High R High W High WE1/DQMLU/WE R High W Low WE2/DQMUL/ICIORD R High W High WE3/DQMUU/ICIOWR R High W High CE2A*3 CE2B*3 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 High High Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 Rev. 5.00 Dec 12, 2005 page 1016 of 1034 REJ09B0254-0500 Appendix A Pin Functions Table A.10 Pin Status (PCMCIA/Big Endian) (cont) PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Pin 16-Bit Bus Width Byte Access (Address 2n+1) High Low High High Low Enabled High High High High High Low High High High High High Low Disabled PCMCIA/IO Interface (Area 6) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High Low High High Low High Low Disabled Word/ Longword Access Enabled High High High Low Enabled High High High High High High Low High High Low High Low Disabled Byte/ Byte Word/ Access Longword (Address Access 2n) Enabled R Low W High Enabled Low High High Low Enabled High High High High High Low High High High High High High Disabled Byte/ Byte Word/ Word/ Access Longword Longword (Address Access Access 2n) Enabled Low High High Low Enabled High High High High High Low High High High High High Low Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled Enabled High High High Low Enabled High High High High High High Low High High Low High High Disabled CS6 to CS2, CS0 RD RD/WR R High W Low BS RAS3 CAS WE0/DQMLL Enabled High High R High W High WE1/DQMLU/WE R High W Low WE2/DQMUL/ICIORD R High W High WE3/DQMUU/ICIOWR R High W High CE2A*3 CE2B*3 CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 High High Disabled Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 Disabled Address Valid data High-Z*2 High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 Notes: 1. Disabled when the wait setting of the WCR2 register is 0. 2. Unused pins can be switched to port function, pull-up. 3. The operation of the CE pin is the same as when operating in little endian mode. Rev. 5.00 Dec 12, 2005 page 1017 of 1034 REJ09B0254-0500 Appendix B Control Registers Appendix B Control Registers B.1 Register Address Map Memory-Mapped Control Registers (Address Map) Module*1 CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC CPG CPG CPG CPG CPG Bus*2 L L L L L L I L L L L L L L L L L L L L L L L L I2 I2 I2 I2 I2 Address*4 H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0 H'FFFFFFEC H'040000B0 H'FFFFFFD0 H'FFFFFFD4 H'FFFFFFD8 H'FFFFFFE4 H'FFFFFFE8 H'FFFFFFB0 H'FFFFFFB4 H'FFFFFFB8 H'FFFFFFA0 H'FFFFFFA4 H'FFFFFFA8 H'FFFFFF90 H'FFFFFF94 H'FFFFFF98 H'FFFFFF9C H'FFFFFFAC H'FFFFFFBC H'FFFFFF80 H'FFFFFF82 H'FFFFFF88 H'FFFFFF84 H'FFFFFF86 Size (Bits) 32 32 32 32 32 32 32 32 32 32 8 8 32 32 16 32 32 16 32 32 32 16 32 32 16 8 8 8 8 Access Size (Bits)*3 32 32 32 32 32 32 32 32 32 32 8 8 32 32 16 32 32 16 32 32 32 16 32 32 16 8 8 16 16 Table B.1 Control Register PTEH PTEL TTB TEA MMUCR CCR CCR2 TRA EXPEVT INTEVT BASRA BASRB BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR BETR BRSR BRDR FRQCR STBCR STBCR2 WTCNT WTCSR Rev. 5.00 Dec 12, 2005 page 1018 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register CKIO2CR BCR1 BCR2 WCR1 WCR2 MCR PCR RTCSR RTCNT RTCOR RFCR SDMR R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 ICR0 IPRA IPRB TSTR TCOR0 TCNT0 Module*1 CPG BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC INTC INTC INTC TMU TMU TMU Bus*2 I2 I I I I I I I I I I I P P P P P P P P P P P P P P P P I2 I2 I2 P P P Address*4 H'0400023A H'FFFFFF60 H'FFFFFF62 H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6C H'FFFFFF6E H'FFFFFF70 H'FFFFFF72 H'FFFFFF74 H'FFFFD000- H'FFFFEFFF H'FFFFFEC0 H'FFFFFEC2 H'FFFFFEC4 H'FFFFFEC6 H'FFFFFEC8 H'FFFFFECA H'FFFFFECC H'FFFFFECE H'FFFFFED0 H'FFFFFED2 H'FFFFFED4 H'FFFFFED6 H'FFFFFED8 H'FFFFFEDA H'FFFFFEDC H'FFFFFEDE H'FFFFFEE0 H'FFFFFEE2 H'FFFFFEE4 H'FFFFFE92 H'FFFFFE94 H'FFFFFE98 Size (Bits) 8 16 16 16 16 16 16 16 16 16 16 -- 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 32 32 Access Size (Bits)*3 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 32 32 Rev. 5.00 Dec 12, 2005 page 1019 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR INTEVT2 IRR0 IRR1 IRR2 ICR1 ICR2 PINTER IPRC IPRD IPRE SAR0 DAR0 DMATCR0 CHCR0 SAR1 DAR1 DMATCR1 CHCR1 SAR2 DAR2 DMATCR2 Module*1 TMU TMU TMU TMU TMU TMU TMU SCI SCI SCI SCI SCI SCI SCI INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Bus*2 P P P P P P P P P P P P P P I2 I2 I2 I2 I2 I2 I2 I2 I2 I2 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 Address*4 H'FFFFFE9C H'FFFFFEA0 H'FFFFFEA4 H'FFFFFEA8 H'FFFFFEAC H'FFFFFEB0 H'FFFFFEB4 H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C H'04000000 H'04000004 H'04000006 H'04000008 H'04000010 H'04000012 H'04000014 H'04000016 H'04000018 H'0400001A H'04000020 H'04000024 H'04000028 H'0400002C H'04000030 H'04000034 H'04000038 H'0400003C H'04000040 H'04000044 H'04000048 Size (Bits) 16 32 32 16 32 32 16 8 8 8 8 8 8 8 32 16 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 32 32 32 Access Size (Bits)*3 16 32 32 16 32 32 16 8 8 8 8 8 8 8 32 8 8 8 16 16 16 16 16 16 16,32 16,32 16,32 8,16,32 16,32 16,32 16,32 8,16,32 16,32 16,32 16,32 Rev. 5.00 Dec 12, 2005 page 1020 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register CHCR2 SAR3 DAR3 DMATCR3 CHCR3 DMAOR CMSTR CMCSR CMCNT CMCOR ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR DADR0 DADR1 DACR SIMDR SISCR SITDAR SIRDAR SICDAR SICTR SIFCTR SISTR SIIER SITDR SIRDR SITCR Module*1 DMAC DMAC DMAC DMAC DMAC DMAC CMT CMT CMT CMT A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D D/A D/A D/A SIOF SIOF SIOF SIOF SIOF SIOF SIOF SIOF SIOF SIOF SIOF SIOF Bus*2 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 Address*4 H'0400004C H'04000050 H'04000054 H'04000058 H'0400005C H'04000060 H'04000070 H'04000072 H'04000074 H'04000076 H'04000080 H'04000082 H'04000084 H'04000086 H'04000088 H'0400008A H'0400008C H'0400008E H'04000090 H'04000092 H'040000A0 H'040000A2 H'040000A4 H'040000C0 H'040000C2 H'040000C4 H'040000C6 H'040000C8 H'040000CC H'040000D0 H'040000D4 H'040000D6 H'040000E0 H'040000E4 H'040000E8 Size (Bits) 32 32 32 32 32 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 32 32 32 Access Size (Bits)*3 8,16,32 16,32 16,32 16,32 8,16,32 8,16 8,16,32 8,16,32 8,16,32 8,16,32 8,16,32*5 *6 8,16*5 8,16,32*5 *6 8,16*5 8,16,32*5 *6 8,16*5 8,16,32*5 *6 8,16*5 8,16,32*5 *6 8,16 8,16,32*5 *6 8,16*5 8,16,32 16 16 16 16 16 16 16 16 16 32 32 32 Rev. 5.00 Dec 12, 2005 page 1021 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register SIRCR PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR PLCR SCPCR PMCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR PLDR SCPDR PMDR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Module*1 SIOF PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT -- -- -- -- -- -- -- -- Bus*2 P2 P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Address*4 H'040000EC H'04000100 H'04000102 H'04000104 H'04000106 H'04000108 H'0400010A H'0400010C H'0400010E H'04000110 H'04000112 H'04000114 H'04000116 H'04000118 H'04000120 H'04000122 H'04000124 H'04000126 H'04000128 H'0400012A H'0400012C H'0400012E H'04000130 H'04000132 H'04000134 H'04000136 H'04000138 H'04000140 H'04000142 H'04000144 H'04000146 H'04000148 H'0400014A H'0400014C H'0400014E Size (Bits) 32 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- Access Size (Bits)*3 32 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 Access prohibited Access prohibited Access prohibited Access prohibited Access prohibited Access prohibited Access prohibited Access prohibited Rev. 5.00 Dec 12, 2005 page 1022 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCSSR2 SCFRDR2 SCFCR2 SCFDR2 PCC0ISR PCC0GCR PCC0CSCR PCC0CSCIER ACTR1 ACTR2 ASTR1 ASTR2 MRCR MPCR DPNQ RCNT ACDR ASDR TDFP RDFP SDIR IPRF IPRG IRR3 IRR4 ICR3 CHRAR Reserved Reserved STBCR3 SRSTR Module*1 SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF PCC PCC PCC PCC AFE AFE AFE AFE AFE AFE AFE AFE AFE AFE AFE AFE H-UDI PPCNT PPCNT PPCNT PPCNT PPCNR PPCNT -- -- PPCNT PPCNT Bus*2 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 I2 P2 P2 P2 P2 P2 P2 -- -- P2 P2 Address*4 H'04000150 H'04000152 H'04000154 H'04000156 H'04000158 H'0400015A H'0400015C H'0400015E H'04000160 H'04000162 H'04000164 H'04000166 H'04000180 H'04000182 H'04000184 H'04000186 H'04000188 H'0400018A H'0400018C H'0400018E H'04000190 H'04000192 H'04000194 H'04000198 H'04000200 H'04000220 H'04000222 H'04000224 H'04000226 H'04000228 H'0400022A H'0400022C H'0400022E H'04000230 H'04000232 Size (Bits) 8 8 8 8 16 8 8 16 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 Access Size (Bits)*3 8 8 8 8 16 8 8 16 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16/32 16/32 16 16 16 16 16 16 16 16 16 8 8 Rev. 5.00 Dec 12, 2005 page 1023 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register Reserved EXPFC EXCPGCR USBIFR0 USBIFR1 USBEPDR0I USBEPDR0O USBTRG USBFCLR USBEPSZ0O USBEPDR0S USBDASTS USBEPDR2 USBISR0 USBEPSTL USBIER0 USBIER1 USBEPDR1 USBEPSZ1 USBISR1 USBDMA USBEPDR3 HcRevision (USBHR) HcControl (USBHC) HcCommandStatus (USBHCS) HcInterruptStatus (USBHIS) HcInterruptEnable (USBHIE) HcInterruptDisable (USBHID) HcHCCA (USBHHCCA) Module*1 -- PPCNT PPCNT USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBH USBH USBH USBH USBH USBH USBH Bus*2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 Address*4 H'04000238 H'04000234 H'04000236 H'04000240 H'04000241 H'04000242 H'04000243 H'04000244 H'04000245 H'04000246 H'04000247 H'04000248 H'04000249 H'0400024A H'0400024B H'0400024C H'0400024D H'0400024E H'0400025F H'04000250 H'04000251 H'04000252 H'04000400 H'04000404 H'04000408 H'0400040C H'04000410 H'04000414 H'04000418 Size (Bits) 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 32 32 32 32 32 32 32 Access Size (Bits)*3 16 16 8 8 8 8 8 8 8 8 8 8 8/32 8 8 8 8 8/32 8 8 8 8 32 32 32 32 32 32 32 Rev. 5.00 Dec 12, 2005 page 1024 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register HcPeriodCurrentED (USBHPCED) HcControlHeadED (USBHCHED) HcControlCurrentED (USBHCCED) HcBulkHeadED (USBHBHED) HcBulkCurrentED (USBHBCED) HcDoneHead (USBHDHED) HcFmlnterval (USBHFI) HcFmRemaining (USBHFR) HcFmNumber (USBHFN) HcPeriodStart (USBHPS) HcLSThreshold (USBHLST) HcRhDescriptorA (USBHRDA) HcRhDescriptorB (USBHRDB) HcRhStatus (USBHRS) HcRhPortStatus1 (USBHRPS1) HcRhPortStatus2 (USBHRPS2) LDPR00 to LDPRFF LDICKR LDMTR LDDFR LDSMR LDSARU Module*1 USBH USBH USBH USBH USBH USBH USBH USBH USBH USBH USBH USBH USBH USBH USBH USBH LCDC LCDC LCDC LCDC LCDC LCDC Bus*2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 Address*4 H'0400041C H'04000420 H'04000424 H'04000428 H'0400042C H'04000430 H'04000434 H'04000438 H'0400043C H'04000440 H'04000444 H'04000448 H'0400044C H'04000450 H'04000454 H'04000458 H'04000800 to H'04000BFC H'04000C00 H'04000C02 H'04000C04 H'04000C06 H'04000C08 Size (Bits) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 32 Access Size (Bits)*3 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 32 Rev. 5.00 Dec 12, 2005 page 1025 of 1034 REJ09B0254-0500 Appendix B Control Registers Control Register LDSARL LDLAOR LDPALCR LDHCNR LDHSYNR LDVDLNR LDVTLNR LDVSYNR LDACLNR LDINTR LDMPPR LDPSPR LDCNTR Module*1 LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC Bus*2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 Address*4 H'04000C0C H'04000C10 H'04000C12 H'04000C14 H'04000C16 H'04000C18 H'04000C1A H'04000C1C H'04000C1E H'04000C20 H'04000C24 H'04000C26 H'04000C28 Size (Bits) 32 16 16 16 16 16 16 16 16 16 16 16 16 Access Size (Bits)*3 32 16 16 16 16 16 16 16 16 16 16 16 16 Notes: 1. Modules CCN: Cache controller UBC: User break controller CPG: Clock pulse generator BSC: Bus state controller RTC: Realtime clock INTC: Interrupt controller TMU: Timer unit SCI: Serial communication interface DMAC: Direct memory access controller CMT: Compare-match timer A/D: A/D converter D/A: D/A converter SIOF: Serial I/O PORT: Port control SCIF: Serial communication interface with FIFO PCC: PC card controller AFE: Analog front end interface H-UDI: User-debugging interface PPCNT: Peripheral bus interface controller USBF: USB function controller USBH: USB host controller LCDC: LCD controller 2. Internal buses: L: CPU, CCN, cache, TLB, and DSP connected I: BSC, cache, DMAC, INTC, CPG, and UDI connected I2: INTC, CPG, and H-UDI connected P: Peripheral modules (RTC, TMU, SCI) connected P1: Peripheral modules (DMAC, CMT, A/D, D/A, PORT, SCIF) connected P2: Peripheral modules (SIOF, PCC, AFE, PPCNT, USBF, USBH, LCDC) connected 3. The access size shown is for control register access (read/write). An incorrect result will be obtained if a different size from that shown is used for access. 4. To exclude area 1 control registers from address translation by the MMU, set the first 3 bits of the logical address to 101, to locate the registers in the P2 space. Rev. 5.00 Dec 12, 2005 page 1026 of 1034 REJ09B0254-0500 Appendix B Control Registers 5. With 16-bit access, it is not possible to read data in two registers simultaneously. 6. With 32-bit access, it is not possible to read data in the register at [accessed address + 2] simultaneously. Rev. 5.00 Dec 12, 2005 page 1027 of 1034 REJ09B0254-0500 Appendix C Product Lineup Appendix C Product Lineup Power Supply Voltages Abbreviation SH7727 I/O 3.30.3 V 3.30.3 V 3.10.5 V 3.10.5 V Internal 1.7 to 2.05 V 1.7 to 2.05 V 1.6 to 2.05 V 1.6 to 2.05 V Operation Frequency 160 MHz 160 MHz 100 MHz 100 MHz Model Name HD6417727F160C HD6417727BP160C HD6417727F100C HD6417727BP100C Package 240-pin plastic HQFP (PRQP0240KC-B) 240-pin CSP (PLBG0240JA-A) 240-pin plastic HQFP (PRQP0240KC-B) 240-pin CSP (PLBG0240JA-A) Rev. 5.00 Dec 12, 2005 page 1028 of 1034 REJ09B0254-0500 Appendix D Package Dimensions Appendix D Package Dimensions The following drawings show the package dimensions of SH7727. JEITA Package Code P-HQFP240-32x32-0.50 RENESAS Code PRQP0240KC-B Previous Code FP-240B/FP-240BV MASS[Typ.] 7.0g HD *1 D 121 120 180 181 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 Reference Symbol Dimension in Millimeters Min Nom 32 32 3.20 34.4 34.4 34.6 34.6 34.8 34.8 3.95 0.25 0.17 0.40 0.22 0.20 0.12 0.17 0.15 0 0.5 0.10 0.10 1.25 1.25 0.3 0.5 1.3 0.7 8 0.22 0.50 0.27 Max c1 HE E c D E A2 *2 Terminal cross section ZE HD HE A A1 bp 240 1 ZD Index mark 60 61 b1 A A2 c c1 F c A1 L L1 e x y ZD ZE L L1 Detail F e *3 y bp x M Figure D.1 Package Dimensions (PRQP0240KC-B) Rev. 5.00 Dec 12, 2005 page 1029 of 1034 REJ09B0254-0500 Appendix D Package Dimensions JEITA Package Code P-LFBGA240-13x13-0.65 RENESAS Code PLBG0240JA-A Previous Code BP-240A/BP-240AV MASS[Typ.] 0.4g wSA D wSB x4 v y1 S S A y S e ZD A V U T R P N M L K J H G F E D e W A1 E Reference Symbol Dimension in Millimeters Min Nom 13.00 13.00 0.15 0.20 1.40 0.28 0.33 0.65 0.35 0.40 0.45 0.08 0.10 0.2 0.38 Max D B E v w A A1 e ZE C B A b x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 y1 SD SE ZD ZE 0.65 0.65 b xM S A B Figure D.2 Package Dimensions (PLBG0240JA-A) Rev. 5.00 Dec 12, 2005 page 1030 of 1034 REJ09B0254-0500 Appendix E Using Versions Previous to the SH7727B Appendix E Using Versions Previous to the SH7727C E.1 Determining the Version Number Based on the Markings on the Chip (1) HQFP-240 Package Version Previous to SH7727B SH7727B "B" indication SH7727C "C" indication 6417727F SH3-DSP 100 HITACHI 0124 BF80128 JAPAN 6417727F SH3-DSP 100 HITACHI B 0124 BF80128 JAPAN 6417727F SH3-DSP C BF80128 100 0124 Note: Once stocks bearing Hitachi markings are exhausted, chips bearing Renesas markings may begin to appear. (2) CSP-240 Package Version Previous to SH7727B 6417727BP 100 BF80128 0124 JAPAN SH7727B 6417727BP 100 B BF80128 0124 JAPAN "B" indication SH7727C 6417727BP 100 C BF80128 0124 JAPAN "C" indication Rev. 5.00 Dec 12, 2005 page 1031 of 1034 REJ09B0254-0500 Appendix F Using Port G Control Register (PGCR) with Versions Previous to the SH7727B Appendix F Using Port G Control Register (PGCR) with Versions Previous to the SH7727B Bit: Initial value: R/W: Bit: Initial value: R/W: 15 1 R/W 7 1/0 R/W 14 0 R/W 6 0 R/W 13 -- 1 R 5 1/0 R/W 12 -- 0 R 4 0 R/W 11 1/0 R/W 3 1/0 R/W 10 0 R/W 2 0 R/W 9 1 R/W 1 -- 1/0 R 8 0 R/W 0 PG0MD0 0 R/W PG7MD1 PG7MD0 PG5MD1 PG5MD0 PG4MD1 PG4MD0 PG3MD1 PG3MD0 PG2MD1 PG2MD0 PG1MD1 PG1MD0 The port G control register (PGCR) is a readable and writeable 16-bit register used to select pin functions. PGCR is initialized to H'AAAA (ASEMD0 = 1) or H'A200 (ASEMD0 = 0) at power-on reset, but it is not initialized by manual resets or in the standby mode or sleep mode. Bits 15, 14: PG7 Mode 1, 0 (PG7MD1, PG7MD0) Bits 13, 12: Reserved Bits 11, 10: PG5 Mode 1, 0 (PG5MD1, PG5MD0) Bits 9, 8: PG4 Mode 1, 0 (PG4MD1, PG4MD0) Bits 7, 6: PG3 Mode 1, 0 (PG3MD1, PG3MD0) Bits 5, 4: PG2 Mode 1, 0 (PG2MD1, PG2MD0) Bits 3, 2: PG1 Mode 1, 0 (PG1MD1, PG1MD0) Bit 1: Reserved Bits 3, 0: PG0 Mode 1, 0 (PG1MD1, PG0MD0) These bits are used to select pin functions and input pull-up MOS control settings. In the PG1 and PG0 modes, bit 3 (PG1MD1) is used to select between "other function" and "port input." When the port input setting is selected (PG1MD1 = 1), pull-up MOS on-off selection is performed using bit 2 (PG1MD0) in the PG1 mode and bit 0 (PG0MD0) in the PG0 mode. Rev. 5.00 Dec 12, 2005 page 1032 of 1034 REJ09B0254-0500 Appendix F Using Port G Control Register (PGCR) with Versions Previous to the SH7727B PG0 Mode Bit 3: PG1MD1 0 1 Bit 0: PG0MD0 0 1 0 1 Pin function Other function (see table 26.1) Reserved Port input (pull-up MOS: on) Port input (pull-up MOS: off) (Initial value) ASEMD0 = 1 (Initial value) ASEMD0 = 0 PG1 to PG5 and PG7 Mode Bit (2n + 1): PGnMD1 0 Bit 2n: PGnMD0 0 1 1 0 1 Bit (2n + 1): PGnMD1 0 1 Bit 2n: PGnMD0 0 1 0 1 Pin function Other function (n = 1, 2, 5) (see table 26.1) (Initial value) ASEMD0 = 0 Reserved Port input (pull-up MOS: on) Port input (pull-up MOS: off) (n = 1, 2, 3, 5) Pin function Other function (see table 26.1) (n = 7), Reserved (n = 4) Reserved Port input (pull-up MOS: on) Port input (pull-up MOS: off) (n = 4, 7) (Initial value) (Initial value) ASEMD0 = 1 Rev. 5.00 Dec 12, 2005 page 1033 of 1034 REJ09B0254-0500 Appendix F Using Port G Control Register (PGCR) with Versions Previous to the SH7727B Rev. 5.00 Dec 12, 2005 page 1034 of 1034 REJ09B0254-0500 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7727 Group Publication Date: 1st Edition, August 2001 Rev.5.00, December 12, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c)2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 5.0 SH7727 Group Hardware Manual |
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